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# CPTR ARCH, NETS & OS ECSE 2660

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This 25 page Class Notes was uploaded by Miss Damien Crooks on Monday October 19, 2015. The Class Notes belongs to ECSE 2660 at Rensselaer Polytechnic Institute taught by Alhussein Abouzeid in Fall. Since its upload, it has received 28 views. For similar materials see /class/224762/ecse-2660-rensselaer-polytechnic-institute in ELECTRICAL AND COMPUTER ENGINEERING at Rensselaer Polytechnic Institute.

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Date Created: 10/19/15

Activity 04 due end of class A The current machine codenamed Jaguar has a clock rate of 750MHz The hardware team claims that it can improve the clock rate to 15GHz The codename for this improved machine is JaguarEH Specs for both the machines are shown in Table 1 below A standard practice in the computer industry is to perform extensive simulations of new designs before producing them For instance we can run a series of benchmark programs on a simulator for a new processor and make valuable measurements Such a study yielded the data shown in the last two columns for JaguarEH Instruction Type CPI for Jaguar CPI for Jaguar EH Frequency of Instruction a 15 points Calculate the average CPI and MIPS ratings for Jaguar b 15 points Calculate the average CPI and MIPS ratings for JaguarEH c 15 points How much faster is JaguarEH compared to Jaguar BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 1 of 2 Meanwhile the compiler team comes up with enhancements that reduce the number of instructions executed They have codenamed their product JaguarEC Their simulation studies produce the following data Instruction Class Percentage of instructions executed CPI for Jaguar by Jaguar EC compared to Jaguar C A 75 3 B 95 5 C 80 4 D 90 6 E 80 2 d 15 points Calculate the average CPI for JaguarEC e 15 points How much faster is JaguarEC compared to Jaguar B Combining Hardware and Software Ideas a 25 points The hardware and software teams decide to combine their enhancements They codename their joint creation JaguarEE Calculate how much faster this machine is compared to Jaguar BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 2 of 2 Activity 2 Solutions Recap of so e basic computer organization concepts 1 20 points What is the difference between an ALU and a CPU What do these acronyms mean Answer The ALU arithmetic logic unit is just a part of the CPU central processing unit speci cally a part of the datapath unit The CPU consists of a datapath unit and a control unit The ALU is a combinational circuit whereas the CPU is a sequential circuit Grading 5 pts for trying 20 pts for correct answer 2 20 points If a computer has 8 megabytes of memory how many bits of memory does it have Answer 8x1024x1024x8 67108864 bits Grading 5 pts for trying 20 pts for correct answer 3 20 points Write a short assembly language program using LOAD and STORE instructions that will swap the contents of two memory locations labeled N1 and N2 respectively Assume that a single accumulator is available LOAD means to take from memory and put in a register STORE is the reverse process Continue on back if you need to We re not looking for exact syntax here Answer We re looking to see if the student has done any assembly language programming at all LOAD and STORE are core instructions that can be expected on just about any CPU We re looking to see if the student remembers what they are and how they are different ie knows which way the data ows in each case To do this question we need a temporary buffer Suppose it is called TEMP LOAD N1 bring Ni into the accumulator STORE TEMP put that in temp LOAD N2 Bring N2 into the accumulator STORE N1 LOAD TEMP STORE N2 HALT Grading 5 pts for trying 20 pts for correct answer BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 1 of 2 4 40 points For the following CPU write down a Register Transfer Language description of the STORE instruction The instructions are 32 bits wide and the leftmost byte is the opcode The remaining bytes are addresses Memory N bits wide Answer We re looking for an indication that the student has encountered a microarchitecture before and remembers some general aspects of RTN or picked it up from the lecture session2 and how a CPU works the instruction fetchdecodeexecute cycle Exact syntax is not expected We first need to fetch the instruction PC MAR Memory Read Memory IR 0r MBUSIR Then increment the PC to point to the next instruction which in simplified form is PC PC 1 In some implementations we have to pass the PC value through the ALU to add 1 This instruction now in IR must next be decoded using the opcode field leftmost 8 bits IF IRlt0p c0degt STORE THEN For the store instruction we need to transfer the contents of accumulator AC to the memory address specified by the remaining 24 bits of the instruction register IR IRltaddrgt MAR or IR230MAR AC RBUS Memory Write Grading 10 points for trying 20 points for partially correct answer 40 points for nearly correct answer BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 2 of 2 Activity 1 solutions A 5 points inistrative matters 1 3 points Click on course syllabus and note the course prerequisites Check off the boxes that apply to you I took ECSE 2610 Computer Components and Operations I took LITEC I took CSCI2500 Computer Organization El Other please see your instructor immediately Grading 5 points for any answer 0 pts for no answer Please hand the activities marked other to Prof Abouzeid after grading 2 2 points Do you have a learning disability that your instructor should be aware of El Nope El Yes I have one Please contactyour instructor immediatelyforfurther guidance Grading 5 points for any answer 0 pts for no answer Please hand the activities marked yes to Prof Abouzeid after grading DUB B 30 points Recap of binary number representation Grading policy for all questions 2 pts for trying 5 pts for correct answer 1 5 points 5610 001110002 0708 3816 2 5 points 0110 01102 10210 1468 6616 3 5 points 2210 i1110 1010 ieightbit two s complement 4 5 points If you add 5610 and 72310 using 8bit two s complement arithmetic do you get an over ow Nope 7 we can never get an over ow adding numbers with opposite signs 5 5 pointsWhat is the result of performing an arithmetic right shift on the 8bit number representing 2210 Answer In an arithmetic right shift we shift in the sign bit on the left The result is about half the original number and has the same sign Result 111101012 1110 approximately half of 722 and with the same sign like we expect C 15 points Recap of combinational and sequential logic systems Grading policy for all questions 2 pts for trying 5 pts for correct answer 1 Consider the Boolean function f x y z x y7c z y z a 5 points a 5 points Use Boolean algebra to nd the equivalent canonical sumofproducts expression fSOP Jay Z fyz 9972 fyZ xyz b 5 points Use Boolean algebra to nd the equivalent canonical product of sums expression fposxyz Xyzxyi yz z c 5 points Simplify the above function into a minimal sum of products form fminxayaz xz76y ECSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 1 of 2 D 25 points Logic Systems 1 5 points unit delay 2 5 points What is the difference between a DRAM chip and a SRAM chip What do these chips do DRAM dynamic random access memory chips require periodic refreshing offer high capacities and a variable response time SRAM static random access memory chips are much faster than DRAM offer constant access time but offer lower capacities Both chips are for storage Grading 2 pts for trying 5 pts for noting at least 2 of the 3 features of each 3 10 points Sketch a state diagram for a nitestate machine whose input is a bit stream X and that outputs Z 1 when the 2 previous input bits are 01 you may use a Mealy or a Moore implementation 00 00 1 1 10 1 On the left is a Mealy machine solution and on the right is a Moore machine In the Mealy machine the outputs are indicated on the arrows as inputoutput In a Moore machine the outputs are associated with each state rather than with the transitions Each circle contains the state and the output Grading policy 4 pts for trying 6 pts for partial answer 10 pts full answer 4 5 points If the input X to the following circuit is available at time t0 and the gate delay is lns at what time is the output f ready Answer 3 gate delays we follow the longest path from input to output Grading 2 pts for trying 5 pts for correct answer BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 2 of 2 Activity 06 Solutions 1 50 points Describe what the following MIPS code returns in the output register v0 Assume that a 0 is used for the input and initially contains 17 a positive integer Start by creating a pseudocode description of the MIPS instructions in the righthand column Then create a corresponding CC program below and infer the program s behavior from the C program C program a0 n t0 0 t1 1 t2 0 while a0 gt t2 t0 t0 t1 t1 t1 4 t2 t2 1 V0 tO This program calculates the sum 1 5 9 4n1 Grading There are 3 parts to this question P 1 20 pts C program 20 pts nal answer 10 pts For the 10 pts part give 4 pts for trying and 10 for correct answer For the 20 point parts point out errors and deduct 2 points for each line that is incorrect For this part give 8 points minimum for trying BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 1 of 2 2 50 points For a MIPS CPU write down the compiled instructions for the following code fragment int 139 ex why 32 bit integer variables why l for 1 O i lt 20 i ex ex 2 why why ex i Use register t 0 for i associate ex and why with two memory locations whose addresses are in 5 0 and 5 1 respectively our gene Grading This problem has the following important aspects 39 39 quot 39 10 pts 4 pts for trying this part 2 Setting up the loop structure in pseudo code20 points 6 pts for trying 20 points for setting it up correctly 3 Translating the pseudo code to MIPS Deduct 2 points for each erroneous translation Give minimum of 8 points or trying BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 2 of 2 Activity 2 due in class Last Name First Name Student 1 Number 1 2 3 4 Total Grader Initials I 20 points I 20 points I 20 points I 40 points I 100 points I Recap of some basic computer organization concepts 1 20 points What is the difference between an ALU and a CPU What do these acronyms mean 2 20 points If a computer has 8 megabytes of memory how many bits of memory does it have 3 20 points Write a short assembly language program using LOAD and STORE instructions that will swap the contents of two memory locations labeled N1 and N2 respectively Assume that a single accumulator is available LOAD means to take from memory and put in a register STORE is the reverse process Continue on back if you need to We re not looking for exact syntax here 4 40 points For the following CPU write down a Register Transfer Language description of the STORE instruction The instructions are 32 bits wide and the leftmost byte is the opcode The remaining bytes are addresses Continue on back of this page Memory N bits wide ECSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 1 of l Activity 03 due by end of class Last Name First Name Student 1 Number A B C Total Grader Initials 50 points 10 points 40 points 100 points A 50 points Consider a simple CPU with just the instructions listed below 9 Fquot 0 3 1 ECSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 NOP No l 5 points What is the average number of cycles per instruction CPI for this CPU assuming that all instructions are executed equally often CPI 5 points If the CPU cycle time is 35ns what is the average number of instructions executed per second assuming that all instructions are executed equally often MIPS 5 points Given that cycle time is 35ns and n0 parallelism is possible in the architecture what would the highest quotpeak MIPSquot that a computer salesman could misleadingly claim Peak MIPS 5 points How long would it take to execute a program P with 4 million instructions executed equally often and n0 IO State your answer in seconds Tp seconds Page 1 of 3 e 10 points What is the average number of bytes per instruction if all instructions are executed equally often Average BPI f 10 points Based on the clock rate speci ed in part b and part e above calculate the average data rate that the memory system must support in order to keep the CPU running as fast as possible Average Data Rate bytessec g 10 points If the memory system can handle ie readwrite data at a speed of 1 byte every 80ns what is the maximum number of instructions per second that can be executed assuming that all instructions are executed equally often Maximum IPS B 10 points Moore s Law and Compound Interest Moore s Law the textbook does not attribute it to Moore in Ch 1 is sometimes cited as a A 50 gain in computer performance per year G12 15 and sometimes as b Atwofold gain every 18 months G18 20 Calculate the twentyyear 240 month gain G240 resulting from both of these formulations It is sufficiently accurate to find the compound interest per month with the formula Gquot 1 Iquot where 139 is the monthly interest and n is the number of months Hint First use 7112 for a and 7118 for b to calculate 11 Then n240 to compute G240 G240 based on a G240 based on b ECSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 2 of 3 C 40 points Clock rates and instruction sets A popular database program is taking about 15 seconds to do a benchmark database computation This must be reduced to 5 seconds The CPU is currently running at a cycle rate of 250MHz The 39 J 39 s 39 quot have ii i d anew kind oftechnology that allows clock rates to be increased substantially but this increase will affect the rest of the CPU design causing the new machine to require 25 more clock cycles as the current machine to do the same job a 30 points Calculate the minimum clock rate that must be achieved assuming that the time spent on 10 is negligible Him This problem is similar to the example in Section 14 on page 34 ofPH Cycle time MHz b 10 points Moore s law states that CPU performance doubles every 18 months on average Assuming that our designer s competitors are all improving the performance of their machines at this rate calculate the amount of time available to the designer make the above improvement if it takes the company 2 months to go from design to production Lead time months BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 3 of 3 Activity 3 Solutions A 50 points Consider a simple CPU with just the instructions listed below P Fquot 0 3 1 ECSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 NOP No 5 points What is the average number of cycles per instruction CPI for this CPU assuming that all instructions are executed equally often CPI 51 l Answer amp 425cycles instruction 12instructions Grading 5pts for correct answer 2pts for partial 0 for not trying 5 points If the CPU cycle time is 35m what is the average number of instructions executed per second assuming that all instructions are executed equally often MIPS Answer Execution of a single instruction is 42535 14875nsinstruction 14875 10399sec instruction Reciprocal of this is 00067109 instructionssec 67 million instructions per second 67 S Grading 5pts for correct answer 2pts for partial 0 for not trying 5 points Given that cycle time is 35ns and no parallelism is possible in the architecture what would the highest quotpeak MIPSquot that a computer salesman could misleadingly claim Peak MIPS Answer Since no parallelism is possible salesman can at most claim 1 instruction is executed per cycle That means an instruction takes 3510399secinstruction which means 00286 10 instructions could be executed per second So the peak is 286 MIPS Grading 5pts for correct answer 2pts for partial 0 for not trying 5 points How long would it take to execute a program P with 4 million instructions executed equally often and no IO State your answer in seconds Tp seconds Answer From part b we know that an instruction takes 14875ns for execution which is 014875quot 10396 seconds So the total execution time for the program P will be 40000000 14875 10396 seconds 0595 seconds Grading 5pts for correct answer 2pts for partial 0 for not trying Page 1 of 3 e 10 points What is the average number of bytes per instruction if all instructions are executed equally often Average BPI 33bytes 12instructions Grading 1 Opts for correct answer 5pts for partial 2pts for trying Answer 2 75 bytes instruction quot1 10 points Based on the clock rate speci ed in part b and part e above calculate the average data rate that the memory system must support in order to keep the CPU running as fast as possible Average Data Rate bytessec bytes 67106 instructions sec Answer 2 75 18425000bytessec 1843millionbytessec instruction Grading 1 Opts for correct answer 5pts for partial 2pts for trying g 10 points If the memory system can handle ie readwrite data at a speed of 1 byte every 80ns what is the maximum number of instructions per second that can be executed assuming that all instructions are executed equally often Maximum IPS Answer The memory can support only up to 00125 bytesns 125 million bytessec However the CPU needs 1843millionbytes second with a rating of 6 7MIPS which means the memory is the bottleneck So the maximum number of instructions that can be executed 125 millionbytes sec 1 275 instructionsbyte 455 million instructions per seconds 455 MIPS Grading 1 Opts for correct answer 5pts for partial 2pts for trying B 10 points Moore s Law and Compound Interest Moore s Law the textbook does not attribute it to Moore in Ch 1 is sometimes cited as a A 50 gain in computer performance per year G12 15 and sometimes as b Atwofold gain every 18 months G18 20 Calculate the twentyyear 240 month gain G240 resulting from both of these formulations It is sufficiently accurate to find the compound interest per month with the formula Gquot 1 iquot where i is the monthly interest and n is the number of months Hint First use n12 for a and n18 for b to calculate 11 Then n24O to compute G240 Answer First we need to find interest rate i S11i 1is quot For 1112 1i15 12 G240 151122401520332526 For n18 1i20 18 G24020 1824 204 31032127 G240 based on a 3325 G240 based on b 10321 Grading 2pts for trying plus 3pts for each correct interest rate plus 2pt for each correct twengg year gain BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 2 of 3 C 40 points Clock rates and instruction sets A popular database program is taking about 15 seconds to do a benchmark database computation This must be reduced to 5 seconds The CPU is currently running at a cycle rate of 250MHz The 39 39 39 s 39 quot have ii i d anew kind oftechnology that allows clock rates to be increased substantially but this increase will affect the rest of the CPU design causing the new machine to require 25 more clock cycles as the current machine to do the same job a 30 points Calculate the minimum clock rate that must be achieved assuming that the time spent on 10 is negligible Hint This problem is similar to the example in Section 14 on page 34 ofPampH Grading 3 parts a 10pts each 39 ofN in ation ofN 39 ofC For each part 2pts for partial 5pts for correct answer Let N be the number of cycles to execute the benchmark ie NCPI of instructions Let C be the new required clock rate for achieving 5sec execution time Then 15sec N cycles 1250106 secscycle N375109 cycles For the new machine 5sec l25 375109 cycles lC secscycle C 9375 106 cyclessec 9375MHz Cycle time 9375 MHz b 10 points Moore s law states that CPU performance doubles every 18 months on average Assuming that our designer s competitors are all improving the performance of their machines at this rate calculate the amount of time available to the designer make the above improvement if it takes the company 2 months to go from design to production Grading 1 pt for trying 3pts for partial 5pts for correct answer CPU s performance is 3 times better ie speedup for CPU is 15sec 5sec 3 The total time needed is 2853 months in order to triple the CPU performance More practically 29 months is needed Within 29 months company must design and produce the machine So the designer has a total of 29227months to do his job Since we weren t clear in referring to the improvement based on the execution time an acceptable answer could also be based on the necessary CPU speedup on the frequency speed calculated in 3a That is 9375MHz 250MHz 375 This would result in 375 l0003926 x x 3432 34months So the designers has 342 32 months to do thejob Lead time 27 months BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 3 of 3 Computer Architecture Networks and Operating Systems CANOS EC SE2660 Syllabus Spring 201 1 Catalog Description ECSE2660 Computer Architecture Networks and Operating Systems Quantitative basis of modern computer architecture processor design memory hierarchy and inputoutput methods Layered operating system structures process and storage management Layered network organization network protocols switching local and wide area networks Examples from Unix and the Internet Students cannot receive credit for both this course and ECSE4730 Prerequisite ECSE2610 Spring term annually 4 credit hours Class hours and locations Lectures 200 7 350 pm Mondays and Thursdays SAGE 3303 Instructor Prof Alhussein A Abouzeid ECSE Department Of ce JEC 6038 telephone 518 2766534 Email abouzeidecserpiedu Of ce hours Thursdays 1230130 pm or by appointment Textbooks 0 Computer Organization and Design 4th Edition The H ardwareSoftware Interface David A Patterson and John L Hennessy Morgan Kaufmann 2009 0 Operating System Concepts 8th Edition Avi Silberschatz Peter Baer Galvin Greg Gagne John Wiley amp Sons Inc 2008 o Handouts on Networking Course Objectives As suggested by its title this course has three parts Computer Architecture Computer Networks and Operating Systems These three parts are not as diverse as it may rst appear They are based on a common set of principles based on the concepts of layered structures or hierarchies The purpose of this course is to introduce the student who is expected to have taken COCO Computer Components and Operations to a somewhat more detailed yet broad set of concepts that pervade computer engineering Upon completion of this course the student should be able to make informed choices about subsequent courses that explore speci c areas in depth In this sense we consider this a quot gateway coursequot This course is designed to emphasize quantitative methods of analysis and design whenever possible There is an emphasis on understanding computer performance and relating the measures to market factors and global trends affecting the performance of each component eg Moore39s law for processor performance Speci cally we will teach methods to calculate processor performance multilevel storage system performance inputoutput system performance and network performance You 3911 need to bring your calculator to every class Syllabus by Book Chapters Patterson and Hennessy 0 Chapters 1 through 8 o The following sections will be skipped o 28 215 216 o 35 o 55 59 o 68610 Silberschatz Galvin and Gagne Chapters 13 Chapters 46 Chapters 10 11 Chapters l3 14 Other changes may be made by the instructor as the semester proceeds Course Content by Time Spent approximate Patterson and Hennessey 14 classes Silberschatz and Galvin 7 classes Networks 6 classes Performance Assessment A graded activity in each class session all account for 15 due on the same class session that the activity is assigned Grading will drop the lowest three One homework assignment per week all account for 15 posted each Thursday due the next Thursday Grading will drop the lowest w Two inclass tests each accounts for 20 to be conducted during classes Monday February 28Lh and Monday April 4m One comprehensive Final accounts for 30 of total grade Absence Unapproved absence from an exam or activity will count as zero for that grade item A job interview is not an approved absence unless approved beforehand An approved absence is one that has been approved following Rensselaer s rules and procedures and should be documented and shown beforehand to the instructor In case of approved absence the nal exam will substitute the corresponding activity homework or midterm In case of approved absence for nal exam a makeup nal exam will be scheduled for those individuals Academic Integrity In general all work is to be your own Any collaboration on an exam midterms or nal or copying of an activity or homework will be considered cheating Any student determined to have cheated will receive zero credit for that exam For problem sets activities or homework you may collaborate as required or come for help during office hours You should try to do as much of the problem set on your own as possible and only then seek help from others If you obtain a method from a colleague then please write up your own solution following this method and put a note of acknowledgment Activity 04 Solutions A The current machine codenamed Jaguar has a clock rate of 750MHz The hardware team claims that it can improve the clock rate to 15GHz The codename for this improved machine is JaguarEH Specs for both the machines are shown in Table 1 below A standard practice in the computer industry is to perform extensive simulations of new designs before producing them For instance we can run a series of benchmark programs on a simulator for a new processor and make valuable measurements Such a study yielded the data shown in the last two columns for JaguarEH Instruction Type CPI for Jaguar CPI for Jaguar EH Frequency of Instruction a 15 points Calculate the average CPI and MIPS ratings for Jaguar Answer Average CPI 3040 5025 4015 60 10 20 10 385 cyclesinstruction 750 X106cyclessec 19481gtlt106instrsec 195 MIPS 385 cyclesinstr MIPS Grading Policy 15 pts for correct answer 6 pts partial 0 pts no answer b 15 points Calculate the average CPI and MIPS ratings for JaguarEH Answer Average CPI 2040 4025 2015 60 10 20 10 280 cyclesinstruction 1500 X106cyclessec 280 cyclesinstr MIPS 53571 gtlt 106instrsec 536 MIPS Grading Policy 15 pts for correct answer 6 pts partial 0 pts no answer c 15 points How much faster is JaguarEH compared to Jaguar Answer The improvement is the inverse ratio of the execution times For the processor it is the ratio ofthe MIPS Therefore performance improvement MIPSJaguarEH MIPSazguar 5357119481 275 EH is 175 faster Note that ratio of execution times is equivalent to inverse ratio of MIPS in here because the frequencies of usage of the instructions are the same Grading Policy 15 pts for correct answer 6 pts partial 0 pts no answer BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 1 of 3 Meanwhile the compiler team comes up with enhancements that reduce the number of instructions executed They have codenamed their product JaguarEC Their simulation studies produce the following data Instruction Class Percentage of instructions executed CPI for Jaguar by Jaguar EC compared to Jaguar EC A 75 3 B 95 5 C 80 4 D 90 6 E 80 2 d 15 points Calculate the average CPI for JaguarEC 800 800gtlt21600 So CPI 32675 75 395 Note that calculation of CPI is a little different here because we cannot really use the weighted averaging technique Weighted averaging could only be used when the weights add up to 1 However in this case we have to compute CPI by the ratio of total of cycles total of instructions Note that CPI for this machine is slightly higher than for the base Jaguar This is not surprising since we now have a higher percentage of type B and D instructions that take longer So the compiler team improved type A C and E instructions a lot but they did not follow the Amdahl s Law and ignored improving the more frequently used instructions Grading Policy 15 pts for correct answer 6 pts partial 0 pts no answer e 15 points How much faster is JaguarEC compared to Jaguar The cycle time on Jaguar and JaguarEC is 1750 MHz seconds 00013quot 10396 seconds 13ns cycle Execution time on Jaguar 100 instructionsgtlt385 cyclesinstructiongtlt13nscycle 5005 ns Execution time on JaguarEC 8275 instructionsgtlt395 cyclesinstructiongtlt13nscycle 4249 ns Timemgm 5005 4249 Grading Policy 15 pts for correct answer 6 pts partial 0 pts no answer Therefore performance improvement 118 times faster ie 18 faster Ti meJaguar 7 EC BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 2 of 3 B Combining Hardware and Software Ideas a 25 points The hardware and software teams decide to combine their enhancements They codename their joint creation JaguarEE Calculate how much faster this machine is compared to Jaguar Answer This calculation is similar to the one above except that the number of cycles for instructions 2375gtlt49500 288 75 So CPI 23825 Execution time on Jaguar 100 instructionsgtlt385 cyclesinstructionx13nscycle 5005 501 ns Execution time on EE 8275 instructionsgtlt290 cyclesinstruction gtltll5nscycle 160 ns Time a 501 Therefore performance 1mprovement g 7 313 t1mes faster Time 160 Note that 275xll8325 software and hardware improvements don t multiply exactly Grading Policy 10 pts for correct time on Jaguar 10 for Jaguar EE 5 for ratio 5 pts for trying 0 Qts no answer Page 3 of 3 BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Activity 01 due in class Last Name First Name Student TD Number AC D Total Grader Initials I 50 points I 50 points I 100 points A 5 points Administrative matters 1 3 points Note the course prerequisites Check off the boxes that apply to you I took ECSE 2610 Computer Components and Operations El I took LITEC El I took CSCI2500 Computer Organization El Other please see your instructor after class 2 2 points Do you have a learning disability that your instructor should be aware of Nope El Yes I have one Please contact your instructor after class for further guidance B 30 points Recap of binary number representation l 5 points 5610 2 s 16 2 5 points 0110 01102 10 g 15 3 5 points 2210 eightbit two s complement 4 5 points If you add 5610 and 72210 using 8bit two s complement arithmetic do you get an over ow 5 5 pointsWhat is the result of performing an arithmetic right shift on the 8bit number representing 210 7 10 C 15 points Recap of combinational and sequential logic systems 1 Consider the Boolean function fx y Z x yf zy Z a 5 points Draw the Kamaugh map for this function b 5 points Use Boolean algebra to find the equivalent canonical sumofproducts expression fSOPxayZ c 5 points Use Boolean algebra to find the equivalent canonical product of sums expression fPOSxayZ d 5 points Simplify the above function into a minimal sum of products form fmlnxyaz ECSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 1 of 2 D 50 points Logic Systems 1 10 points A NAND latch is constructed as shown Each gate has a unit delay Given input waveforms m and n determine the waveforms for y and z 0 JLJLLL unit delay 2 10 points What is the difference between a DRAM chip and a SRAM chip What do these chips do 3 20 points Sketch a state diagram for a nitestate machine whose input is a bit stream X and that outputs Z 1 when the 2 previous input bits are 01 You may use a Mealy or a Moore implementation 4 10 points If the input X to the following circuit is available at time F0 and the delay of each gate is 1 ns at what time is the output f ready BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 2 of 2 Activity 05 Solutions 1 20 points Translate the C statement a b 2c to MIPS code Assume that a b c are associated with registers 51 52 53 respectively Use the add instruction only Do NOT use any register other than 51 52 53 add s3s3s3 s3 c c 2c add s1s2s3 sl b2c Grading 20 pts for correct 8pts for partial 4pt for trying 2 20 points Translate the C statement a b c b d to MIPS code without using any temporary registers Assume that the variables a b c d are associated with registers 50 51 52 53 respectively You just need 3 instructions in the code Do NOT use instructions other than add and sub add s0s1sl s0bb sub s0s0s2 s0s0cbbc add s0s0s3 s0s0dbbcd Grading 20pm for correct 1 Opts for any quot correct code The operations can be done in any order 20 points Translate the C statement a b C i to MIPS code Assume that each element of the array C is a word Also assume that C is an array whose base register address ie the address of C O is in 51 and that variables a b and i are in registers 52 53 and 5 4 respectively Use repeated addition to multiply by 4 to obtain the required memory address Your code can include up to 5 instructions any answer with more than 5 instructions will be treated as partially correct Do NOT use instructions other than acidI 5ub L 1w L 5w 3 add tls4s4 Temp reg t12xi add t1tlt1 Temp reg t14Xi add t1t1s1 Temp reg t1address ofCl 4is1 1w t00tl Temp reg t0Ci sub s2s3t0 abCi Grading 20 pts for correct 10 for any quot1 valid code 5 for trying BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 1 of 2 4 20 points Translate the instruction addi t1 t2 80 to binary code Write your answer in hexadecimal notation Registers t0t7 map to 815 from the Green Page 6 bits 5 bits 5 bits 16 bits s ymbo i i c opcode t2 tl constant decimal 8 10 9 80ten hex 001000 01010 01001 0050ihw 21490050h Grading 8 points for the correct number of bits for each eld 8 for correct hex 4 for trying 5 20 points Convert the following simple loop to MIPS assembly code assume that i is associated with 50 k is associated with 51 and j is associated with 52 i and k are initially zero j is positive 3 instructions Start kki ii1 if ia j go to Start Start add slsls0 addi s0s0l bne s0s2Start Grading 202m for correct answer 102m if anything other than branching is correct 5 Qts for trying BOSE2660 Computer Architecture Networks amp Operating Systems Spring 2011 Page 2 of 2

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