CPTR COMPONENTS & OPER
CPTR COMPONENTS & OPER ECSE 2610
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This 34 page Class Notes was uploaded by Immanuel Brakus PhD on Monday October 19, 2015. The Class Notes belongs to ECSE 2610 at Rensselaer Polytechnic Institute taught by Staff in Fall. Since its upload, it has received 234 views. For similar materials see /class/224782/ecse-2610-rensselaer-polytechnic-institute in ELECTRICAL AND COMPUTER ENGINEERING at Rensselaer Polytechnic Institute.
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Date Created: 10/19/15
COCO Class 14 Today Concept of the Finite State Machine Reviewed Basic Design Approach Exam ples Example Odd Parity Checker Asserts output whenever input bit stream has odd of 139s s s i o i o i 1 m o m o m 1 m 1 i 1 Symbolic State Transition Table 5 s o o 1 1 oao o o 1 o 1 1 1 o 1 Encoded State Transition Table Odd Parity Checker Operation ExcitationOutput Functions D P59 Input Output PS Basic Design Approach Six Step Process 1 Understand the statement of the Specification 2 Obtain an abstract specification of the FSM 3 Perform a state minimization 4 Perform state assignment 5 Choose FF types to implement FSM state register 6 Implement the FSM 1 2 covered now 3 4 5 covered later 4 5 generalized from the counter design procedure 4 Vending Machine Concept General Machine Concept deliver package of gum after 15 cents deposited single c oin slot for dimes nickels no change Vending Machine FSM 1 Step 1 Understand the problem INPUTS OUTPUTS Block Diagram Vending Machine FSM 2 Step 2 Ma into more suitable abstract representation rTabTrlate Warinput sequences three nickels nic el 39 dime nickel di s two nickels dime Tbraw state diagram Inputs N D reset Output open Take a minute to do step 2 of the 6 step process Vending Machine FSM 3 Step 3 State Minimization a N Present rpm Bk Output snae E 8029 N M g o n 5 5 10 n g 1 10 10 W W x 1 W reuse states whenever possible Take a minute to do step 3 of the 6 step process J Symbolic State Table I8 Vending Machine FSM 4 Step 4 State Encoding How many ip nps arerneeded Presehstate be Nextstate on 0103 D N D1 DU Opn o o o 1 o gtlt o 1 1 o 1 x 1 o o 1 1 x 1 1 1 1 1 gtlt x Vending Machine FSM 5a Ste 5 Choose FIstorim Iementation D FIF e si sTto us Q1 Q1 Q1130 Q1510 n D an m 11 m D an 101 11110 Vending Machine FSM 6a Step 6 Implementation D FIFs D1Q1DQDN DoN Jao o1N o1D oPENo1oo 8 Gates Vending Machine FSM 5b Step 5 Choose FF for Implementation continued JK FF Presentstate mputs NeXtState t1 K1 t KB 01 On D N 0 0 0 0 0 0 0 X 1 1 X 0 X X X U 1 U 1 X X 1 X 1 U X X X X X X 1 1 U X 0 X 0 X X X Vending Machine FSM 6b Step 6 Implementation JK FIFs Q1 Q1 man man J1D ON D an m 11 m a K10 Jo m o1D Khan r Kmap mm 01 on 01 an m l1 1 Kmap IorJ Kmap mm Deposit Machine Specifications for a deposit return machine The machine returns the 5 deposit on a container to the user For every five containers returned the machine dispenses a quarter If the user has less than five containers credit when the user presses the DONE button the machine dispenses the correct number of nickels If the DONE button is pressed with no containers in the machine no coins are dispensed All outputs should stay on until the DONE button is pressed or a container is inserted Take a minute to do steps 1 thru 4 of the 6 step process 14 Deposit Machine 1 Step 1 Understand the problem INPUTS OUTPUTS Block Diagram Deposit Machine 2 Step 2 Map into more suitable abstract representation 0 cans 0 Done 1 can 5 Done 2 cans 10 Done 5 cans 25 gt 0 cans 0 Assumption can Sensor Input and Done Button cannot be asserted at the same ime Deposit Machine 3 Step 2 Map into more suitable abstract representation Reset Emma not n39 Tants39EEToumf nei 7 quot397 39 Note Reset is used only to start the FSM 39 25 JLJ5 l 17 a Deposrt Machine 4 Step 3 State Minimization All states needed Inputs Outputs Inputs Outputs Inputs Outputs PS D C NS 5 25 PS D C NS 5 25 PS D C NS 5 25 0 0 0 0 0 0 3 0 0 3 0 0 0 1 1 0 I 0 1 4 0 0 1 0 I 0 0 1 0 7 0 0 7 X X 8 1 0 1 1 X X X 1 1 X X X 1 0 0 1 0 0 4 0 0 4 0 0 8 X X 9 1 0 0 1 2 0 0 0 1 5 0 0 1 0 9 0 0 1 0 6 0 0 9 X X 0 1 0 1 1 X X X 1 1 X X X 2 0 0 2 0 0 5 0 0 0 0 1 0 1 3 0 0 0 1 1 0 1 1 0 3 0 0 1 0 0 0 1 Inputs are ignored 1 1 X X X 1 1 X X X Symbolic State Tablel Deposit Machine 5 Step 4 State Encoding How many ps are needed Symbolic Flip ops s 02 Q tat Q3 1 00 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 Any other FIF states 5 0 1 0 1 cares 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 Stacks Subroutines Complete Programmer39s Model 7 A 07 B 15 8bit Accumulators A amp B 16bit Accum ulator D 15 16bit Index Register IX 15 15 16bit Index Register IY Program Counter 0 0 0 0 0 0 15 Stack Pointer S X H N Z V C Condition Code Register A k STOPdisable f I l L CarryborrowMSB oVen low 2s C Xinterrupt mask Zero Negative Half carry bit 354BCD 2 interrupt mask Stacks Stack Area Stacks Grow down toward low memory Data PuSHed on the stack PSH PULled off the stack PUL Stack Pointer Always PUL as many times as PSH The Stack Pointer always points to the next empty cell on the stack 3 PuSHing Data on Stacks Stack Area SP decrements and points to empty cell SP gt empty SP SP points to 39 empty cell Data is PuSHed on the stack 4 PU Lling Data off Stacks Stack Area SP points to empty cell SP increment SP gt empty SP Data is PULled off stack SP points to empty cell Stack Instructions Reserve a Stack Area eg 256 cells STACK RMB 256 INITSP EQU 1 Top of Stack togeiher Initialize the Stack Pointer lNlT LDS INITSP Push Registers on Stack PSHA Push ACCA PSHB Push ACCB PSHX Push IX 2 bytes PSHY Push W 2 bytes Similarly PULA PULB PULX and PULY More Stack Instructions Transfer Registers TSX SP1 gt X TSY SP1 4 Y Notice the TXS lX1 H SP increment SP and decrement X IY TYS lY1 4 SP Increment Decrement Stack Pointer INS SP1 a SP DES SP1 a SP Lots of addressing modes Load IStore Stack Pointer LDS MM1 a SP IMM DIR EXT indX indY STS SP a MM1 DIR EXT indX indY Lec Exercise 1 A Write an assembly language program starting at 6A00 that stores the contents of the ABXY and CCR registers on the stack A 2B B 00001001 X 6F00 Y C000 and CCR 01x0xxxx B Write an assembly language program starting at D300 that loads the contents of the ABXY and CCR registers from the stack SP 01 SP1 02 SP2 03 SP3 04 SP4 05 SP5 06 SP6 07 SP7 08 A 6A00 6A01 6A02 6A03 6A04 6A05 6A06 6A07 6A08 6A09 6AOA Exercise 1 Answer Push ABXYCCR on Stack in that order BE 0 0 4A 36 37 3C 18 3C 07 36 3F LDS 004A Buffalo User Stack area B D300 D301 D302 D303 D304 D305 D306 D307 D308 D309 D30A D30B D3OC D30D TPA use ACCA PSHA HALT Pull ABXYCCR off Stack 32 33 38 18 B7 D3 0D 32 06 B6 D3 0D 3F PULB PULX PULY STAA SAVEA PULA TAP LDAA SAVEA get CCR HALT SAVEA holds ACCA 9 Subroutine Instuctions Stack Area Subroutine call JSR BSR JSR BSR push Return Address on Stack SP Su broutine return RTS RTS pulls Return Address off Stack Subroutine Arguments Pass by value Copy data to a register or location known to the subroutine Accumulators are commonly used to pass values Pass by reference Provide a pointer to the data location Index registers are commonly used to pass pointers Global variables All variables and constants are global when using the Motorola crossassembler All source code is in the same file hence labeled variables and constants are all in the same symbol table 11 Leo Exercise 2 Write a subroutine to reverse the order of a list of length LISTLEN and pointed to by the Xregister Make a flowchart or pseudocode version first SUBROUTINE REVERSE REVERSES A LIST OF LENGTH 39LISTLEN39 X POINTS TO THE LIST RTS SUBROUTINE DATA SECTION TEMP RMB 1 Exercise 2 Answer PC Pseudo Code for SUBROUTINE REVERSE REVERSES A LIST OF LENGTH 39LISTLEN39 X POINTS TO THE LIST Subroutine setup X points to front of list LISTLEN contains number of elements in the list LISTLEN2 gt COUNT truncates if LISTLEN is odd X LISTLEN 1 gt Y Y points to end of list for 1 to COUNT do MX gt A MY gt B A gt MY B gt MX X 1 gt X Y 1 gt Y return swap MX and MY move pointers toward middle Exercise 2 Answer Asm SUBROUTINE REVERSE REVERSES A LIST OF LENGTH 39LISTLEN39 XPOINTS TO THE LIST ORG 7000 LOOP LDAA 0X REVERSE EQU LDAB 0Y LDAB LISTLEN STAB 0X ASRB STAA 0Y STAB COUNT INX STX XSTORE DEY LDY XSTORE DEC COUNT LDAB LISTLEN BNE LOOP RTS DEY COUNT RMB 1 XSTORE RMB 2 END REVERSE A LIST Write a program to test your subroutine to reverse the order of a short list less than 255 elements The list has length LISTLEN The index register X points to the rst element of the original list Do the reversal in place That is swap the rst and last elements the second and nexttolast elements etc Use subroutines to make the program easier to debug TEST PROGRAM FOR SUBROUTINE REVERSE 39REVERSE A LIST39 SUBROUTINE REVERSES A LIST IN PLACE INPUT A LIST OF LENGTH 39LISTLEN39 INPUT PARAMETERS POINTED TO BY IXREGISTER LIST LENGTH 39LISTLEN39 OUTPUT A LIST IN REVERSE ORDER X POINTS TO 39LIST REGISTERS USED OUTPUT REVERSED LIST AUTHORS SAVES AND RESTORES ABXY DATE REVERSE EQU QUATES PSHA OUTSTRG EQU EEC7 PSHB PSHX ORG 6000 PSHY PROGRAM SECTION LDS 004A PUT YOUR SUBROUTINE BODY HERE LDX LIST JSR OUTSTRG LDX LIST RESTORE REGISTERS BSR REVERSE DONE PULY LDX LIST PULX JSR OUTSTRG PULB SWI PULA RETURN MAIN DATA SECTION RTS LIST ECC quot0123456789abcdequot LENGTH EQU LISTI SUBROUTINE DATA SECTION ECB 4 SWAPiNO LISTLEN ECB LENGTH SAVEX RMB 2 CrossAssembler Assembler operations Assembler directives Assembly language basics M6811 CrossAssembler Program assembles on one machine host and runs on another target Source Code DOS instruction ltPr09asmgt quotasm progquot I Assembler Outputs ASSEMBLER V 7 V 7 Listing File Load File Script File ltproglstgt ltprogs19gt ltproggt amp 2 Assembly Language Source Statement Content Numbers Decimal default 1015 Hexadecimal 2C Binary oo1ooooo Symbols 16 Alphanumeric characters 1 character symbols not allowed A B D X orY Avoid symbols that are identical to opcode mnemonics Expressions Symbols and numbers separated by arithmetic operators Arithmetic operators are and I The assembler does the math No embedded spaces are allowed in any base Source Statement Format I Label I Operation I Operand I Comment I I Statement fields are separated by blan ksf I Label a symbol whose first f ACII39auygatbs are character is in column 1 a owe 39 Operation instruction mnemonic for Opcode What about a blank Operand can be empty a symbol a In column 1 number or an expression Comment the remainder of the line may be blank Example START LDAA C200 This is the beginning of the program 4 Special Assembler Directives Behave like operators but are only used by the assembler not processor Asterisk two usages 1 Putting a in column 1 makes the entire line a comment 2 DATA RMB 4A END EQU is a substitute for the current value of the location counter Pound sign Usage LDAA 0A denotes IMM addressing mode Quotes 39 and quot Usage of 39 39a denotes one ASCII character a 61 Usage of quot quotA bquot denotes ASCII string 4120622E Basic Assembler Directives Behave like operators but are only used by the assembler not processor ORG v Origin Sets value of Usage location counter for the following instructiondata ORG Dooo RMB n Reserve memory bytes USTACK RMB 20 2MB n BSZ n Zero memory bytes DATA 2MB 15 DCB vn Define Constant Block MYDATA 352 17 FCB v FDB v Form Constant Byte Form BLOCK DCB FF3912 Double Byte stores ONE FCB 1o constants FCC F C t tCh t TWO FDB 021A c orm ons an arac er THREE FCB 1F3 s EQU v associates a symbol with I the value of an expression QUERY FCC 7 END denotes the end of the MESS FCC quotendquot 5 urce Pr 9ram START EQU 6200 n number of bytes v value of bytes s symbol I Lee Exercise 1 Program starts at D100 L1 0B gt ACCA L2 ACCA 1 gt ACCA if ACCA 05 then go to L1 else go to L2 1 Write this program in assembly language 2 Hand code this program in machine code Exercise 1 Answer D100 86 L1 LDAA 0B OBAACCA D101 0B D102 4A L2 DECA ACCA 1 4gtACCA D103 81 CMPA 05 if ACCA 05 D104 05 D105 27 BEQ L1 then go to L1 D106 F9 D107 20 BRA L2 else go to L2 D108 F9 REVERSE A LIST Write a program to test your subroutine to reverse the order of a short list less than 255 elements The list has length LISTLEN The index register X points to the rst element of the original list Do the reversal in place That is swap the rst and last elements the second and nexttolast elements etc Use subroutines to make the program easier to debug TEST pROGRAM FOR SUBROUTINE REVERSE REVERSE A LIST SUBROUTINE REVERSES A LIST IN pLACE INPUT A LIST OF LENGTH LISTLEN INPUT PARAMETERS POINTED TO BY IX REGISTER LIST LENGTH LISTLEN OUTPUT A LIST IN REVERSE ORDER x POINTS TO LIST REGISTERS USED OUTPUT REVERSED LIST AUTHORS SAVES AND RESTORES ABxy DATE REVERSE EQU E UATES pSHA OUTSTRG EQU FFC7 PSHB PSHX ORG 6000 PSHY pROGRAM SECTION LDS 004A PUT YOUR SUBROUTINE BODY HERE LDX LIST JSR OUTSTRG LDX LIST RESTORE REGISTERS BSR REVERSE DONE PULY LDX LIST PULX JSR OUTSTRG PULB SWI pULA RETURN MAIN DATA SECTION RTS LIST FCC quot0123456789abcdequot LENGTH EQU LIST l SUBROUTINE DATA SECTION FCB 4 SWAPNO RMB LISTLEN FCB LENGTH SAVEX RMB 2 6811 Programming Model Branch Instructions Condition Code Register Comparison Instructions Review 1 Simplified I7 A 0 7 B 0 I 8bit Accumulators A amp B 15 D o 16bitAccumulatorD I 15 PC 0 I Program Counter H N Z V C Condition Code Register A A I L Carryborrow MSB oVen low 25 C Zero Negative Half carry bit 3 4BCD 2 Review 2 Memory Model Memory 64K x 8 0000 Number Notation denotes hexadecimal h oooo 1111 FFFF 15 PC 0 7 ACCx 0 16bit Program Counter 84 Accumulator 3 Review 3 Registers Mnemonic Operation Opcode LOAD memltqhhhgt gt AC 00 STORE AC gt memltqhhhgt 01 ADD AC memltqhhhgt gt AC 10 BRN F AClt15gt 1 THEN qhhh gt PC 11 VVhat registers 15 AC 0 16bit Accumulator dowe 13 PC 0 14blt Program Counter need Review 4 N1 N2 gt SUM Program fragment LDAA 0120 B6 C C ADDA 0123 BB C C STAA 0126 B7 C C HALT 0129 3F N1 0210 12 N2 0211 34 SUM 0212 FF Branch Instructions This is n example of a conditional branch instruction Examples BEQ Branch on Equal to Zero ie Z bit 1 ifZ 1 go to ltaspeci edaddressgt BRA Branch Always lt 39 39 gt go to aspeCIerdaddress These are examples of unconditional branch JMP Jump Alwa instructions ys go to ltaspecifiedaddressgt Now how are these two different Look in the PRG What s Different S39gurce operation Boolean A ngrdeesi g MaChin a Code I orm Expression operand npl n n 39 BRA Branch Always 11 REL 20 rr 2 JMP Jump See Special XT 7E hh ll 3 Operations NDX 6E ff 2 18 6E ff 3 This is a new addressing mode Relative addressing Relative Addressing In this mode addresses are specified relative to the program counter Also known as PCrelative addressing Example 6142 BRA 28 Relative Offset Program branches to address PC 28 To figure out this address we need to know the value in the PC Where is the instruction located in memory BRA is a 2byte instruction After the instruction is fetched Therefore PC 28 6142 28 616A PC 6142 02 6144 Backward Jumps The relative offset is treated as a signed number in two s complement notation Its an infinite op Example 6142 BRA FE quot What does this say about this instruction PC 6144 Relative offset FE Extend the offset to 16 bits gt FFFE PC relative offset 6144 FFFE 6142 0110 0001 0100 0100 1111111111111110 0110 0001 0100 0010 Inherent Addressing Mode Instructions with No Operands Some of the instructions that have no operand ABA A B gt A CLRB 0 gt B INCA A 1 gt A DECB B 1 gt B SEC 1 gt C C CCRlt0gt Lec Exercise 1 Translate the following pseudocode program into M6811 machine code The programs starts at address 6000 Use the SWI instruction to HALT the program BOOO gt IX 0A gt ACCA L1 ACCA 1 gt ACCA IX 1 gt IX 35 gt MX 0 if ACCA 0 then go to L1 else HALT 11 Exercise 1 Answer Address Contents Comments 6000 CE LDX imm BOOO gt IX 6001 BO 6002 00 6003 86 LDAA imm 0A gt ACCA 6004 0A 6005 4A DECA inh L1 ACCA 1 gt ACCA 6006 09 DEX inh IX 1 gt IX 6007 C6 LDAB imm 35 gt ACCB 6008 35 6009 E7 STAB indX ACCB gt MIX 0 600A 00 6003 4D TSTA inh ACCA 0 600C 26 BNE rel if ACCA 0 then go to L1 600D F7 else 600E 3F quotHALTquot Condition Code Register PW Condition Code Register A I Carrylborrow MSB oVerflow 25 C Zero Negative Half carry from bit 3 to 4 used for BCD corrections only These CCR bits are set by ALU operations Simple Branches Test only 1 or 0 Source Boolean Form Operatlon l EX ression Opcode BRA opr Branch Always 1 1 20 BRN opr Branch Never 1 0 21 Simple Conditional Branches Test only one of N Z V C Slgolrrrfie Operation 5522 P de BMI opr Branch if Minus N 1 20 BPL opr Branch if Plus N 0 2A BEQ opr Branch if Equal zero Z 1 27 BNE opr Branch if Not Equal Z 0 26 BVS opr Branch if oVeIflow Set V 1 29 BVC opr Branch if oVeIflow Clear V 0 28 BCS opr Branch if Carry Set C 1 25 BCC opr Branch if Carry Clear C 0 24 Signed Conditional Branches Test combinations of N Z and V Sggrrrf e Operation EBOOIean opcode xpresswn BGT opr Branch if gt Zero Z N lt9 V 0 2E BLE opr Branch if lt Zero Z N V 1 2F BGE opr Branch if gt Zero N lt9 V 0 2C BLT opr Branch if lt Zero N lt9 V 1 2D Unsigned Conditional Branches Test combinations of Z and C 3312 Operation BOOIeaquot Opcode BHI opr Branch if Higher C Z 0 22 BLS opr Branch if Lower or Same C Z 1 23 BHS opr Branch if Higher or Same C 0 24 BLO opr Branch if Lower C 1 25 Same Opcode as BCC Same Opcode as BCS Other Branch Instructions Bit Manipulation Branches Source Form Operation Boolean Ex ression BRCLR oprmskre BRSET oprmskre Branch if bits Set Branch if bits Clear Mmm 0 Mmm 0 Add Mod Opcode DIR 13 NDX 1F NDY 181F DIR 14 NDX 1C NDY 181C Branch to Subroutine BSR opr BranchtoSubroutinJ Special IRELI 8D See Special Operations page in the PRG Comparison Instructions 8 Bit Comparisons Source Form Operation B ean l Anggglomode CMPA opr Compare A to Memory A M IMM 81 DIR 91 EXT B1 DX A1 NDY 18 A1 CMPB opr Compare B to Memory B M IMM C1 DIR D1 EXT F1 NDX E1 NDY 18 E1 Comparison Instructions 16 Bit Comparisons Boolean Addr S ur e F rm I operation IEx ression Mode P de CPD opr Compare D to Memory D MM1 IMM 1A 83 CPX opr Compare X to Memory X MM1 IMM 8C CPY opr Compare Y to Memory Y MM1 Lec Exercise 2 For this program fragment determine the Branch instruction that checks quotN1 3 N2quot for both cases START LDAA N1 CMPA N2 B DONE MORE DONE Suppose N1 42 and N2 BA Case 1 N1 and N2 are unsigned numbers Case 2 N1 and N2 are signed numbers 21 Exercise 2 Answer START LDAA N1 Suppose CMPA 2 m 42 68 and B DONE N2 BA 186 or 70 MORE The Branch instruction that checks N1 3 N2 Case 1 N1 and N2 are unsigned numbers BLS Case 2 N1 and N2 are signed numbers BLE