MICROPROCESSOR SYSTEMS ECSE 4790
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Date Created: 10/19/15
ECSE 4790 Microprocessor Systems Design Motorola 68HC12 User39s Manual Lee Rosenberg Electrical and Computer Systems Engineering Rensselaer Polytechnic Institute Revision 11 81000 Table of Contents page 1 Introduction 2 2 Basic Programming notes for the 68HC12 3 3 DBug 12 Monitor Program 4 4 68HC12 Hardware 7 a Ports 7 b AD Converter 8 c Timer Functions 12 i Timer Output Compare 13 ii Output Compare 7 14 iii Timer Compare Force Register 15 iv Input Capture 15 5 Interrupt Service Routines 16 a Overview 16 b Interrupt Priority 17 c Real Time Interrupt 18 d Timer Overflow Interrupt 19 e Pulse Accumulator Edge Triggered Interrupt 20 f Pulse Accumulator Overflow Triggered Interrupt 22 g Output Compare Interrupt 23 h Input Capture Interrupt 24 i AD Converter Interrupt 25 j IRO Interrupt 26 k Port H Key Wakeup Interrupt 27 1 Port J Key Wakeup Interrupt 28 1 Introduction The Motorola 68H012 is a 16bit microprocessor descended from the 68H011 The design has a number of major improvements over the 6811 and several new features that are not found on the 6811 The biggest change is the expansion from an 8bit bus to a full 16bit bus for both the data and address Other improvements include an increase in the number of AD converter registers Timer output compare and input capture pins and 10 ports Also added is a second SCI connector and a new interrupt called a Key Wakeup interrupt This manual is intended to provide a brief introduction to the 68H012 and how to program it in C using the Introl C compiler 400 This manual is intended primarily for those people who are already familiar with the Motorola 68H011 This manual also assumes that the reader has basic familiarity with the C programming language 2 Basic Programming Notes There are 3 header files that must be included with any code written for the 68HClZ using the Introl C compiler These are HCBlZA4H This file contains all the register declarations for the 6812 INTROLH This file contains several function declarations needed by Introl to compile the program DBUG12H This contains the information need to call the DBung routines and to handle interrupts Omitting this file will result in the calls to the DBung routines being flagged as errors by the compiler Your main function must be of the format void igmain The two 2 underscores before main are necessary as that is the format that Introl uses to recognize the main function of the program 3 DBug12 DBug12 is the monitor program for the 6812 EVB This is similar to the BUFFALO monitor used on the 6811 Unlike the BUFFALO monitor the DBug12 monitor is a series of C functions that are stored in an EPROM on the EVB These functions can be called by the user to handle both IO and several of the common C language ANSI functions All calls to the DBug12 routines follow the same format The format is DB12gtquotroutine namequot The quotDB12gtquot is used as a cast pointer that allows the compiler to reference the EPROM for the different routines The routine name is just the name of the routine and any parameters that are being passed to the function If the function returns a value to the program the return value can be assigned to a variable This is done as follows tempDB12gtquotroutine namequot This assigns the return value of the routine to a variable named temp As always the variable must be declared in the program It is important to note that if you do not include the quotDB12gtquot with the function call the compiler will return an error message The error message that is returned is that the function does not exist Putting the quotDB12gtquot before the function name will solve this problem DBugl2 Functions Readers interested in a more indepth explanation of the DBug12 routines are referred to Motorola Document an1280a quotUsing the Callable Routines in DBug 12quot available on the web at httpwwwecserpieduCoursesCStudioappnotes getchar This function will get a single character of input from the user Function Prototype int getcharvoid Return Value This returns the character from the keyboard in hexadecimal ASCII printf This will display a string of characters to the screen Function Prototype int printfchar 5 Return value The number of characters that were transmitted NOTE The Introl 40 compiler has an error in this function The first parameter in the list is not printed properly There are workarounds for some cases that are given in examples in class handouts In any case simple strings Without variables will work Without problems To display a variable the variable is represented using y in the printf statement where y is chosen from the table below to match the variable type To display a signed decimal integer stored in a variable num the function call would look like DB12gtprintfquotThis is the value of num dquot num decimal number hexadecimal number af for 1015 decimal a from a putchar This will display a single ASCII character on the screen Function Prototype int putcharint Return Value The character that was displayed GetCmdLine This function is used to read in a line of data from the user and store it in an array Each character that is entered is echoed back to the screen using a call to the putchar function Only printable ASCII characters are accepted by the function with the exception of carriage return and backspace Function Prototype int GetCmdLinechar CmdLineStr int CmdLineLen Return Value An error code of NoErr The location where data that is read in is stored and the number of characters that are to be read are determined by CmdLineStr and CmdLineLen respectively CmdLineStr is a char array that is created by the programmer This is where the input line from the user is stored CmdLineLen is the length of the string to be read in A total of CmdLineLen l characters may be entered by the user before the GetCmdLine function exits The user may also use a carriage return to exit before the value of CmdLineLen has been reached Backspace may be used to delete unwanted characters from the line that the user entered The character will be erased from the screen and the memory array isxdigit This routine determines if c is a member of the set O9 Function prototype int isxdigitint c Return Value If c is part of the set the function returns true I if c is not a part of the set the function returns a false 0 az and AmZ toupper This routine is used to convert lower case letters to upper case letters Function Prototype int toupperint c Return Value The uppercase value of c If c is already an uppercase letter it returns c isalpha This routine determines if c is a member of the set amz and AmZ Function Prototype int isalphaint c Return Value If c is part of the set it returns true 1 if it is not a part of the set it returns a false 0 strlen This routine determines the length of the string that is passed in as a parameter The string must be null terminated Function Prototype unsigned int strlenconst char cs Return Value The length of the string pointed to by cs strcpy This routine makes a copy of string two to string one The string to be copied must be null terminated Function Prototype chart strcpychar sl char sZ Return Value A pointer to sl out2hex This outputs an 8bit number on the screen as two hexadecimal numbers Function Prototype void out2hexunsigned int num Return Value None out4hex This outputs a 16bit number on the screen as four hexadecimal numbers Function Prototype void out4hexunsigned int num Return Value None SetUserVector This routine is used for handling Interrupt Service Routines and will be described in the section on interrupts Notes The printf putchar out2hex and out4hex routines do not generate carriage returns or line feeds when they are called To do this you must include nr in either a putchar or a printf statement 4 68HC12 Hardware This section explains the operation of the hardware on the 68HClZ It includes the IO ports the AD converter and the timer functions Hardware interrupts are explained in the next section For more information on this material refer to Motorola document MC68HCBlZA4TSD quotMotorola 68HClZ Technical Summaryquot Ports All port names are of the format iHlZPORTx where x is the capital letter of the port you are trying to access ie Port A is iHlZPORTA Ports A and B are used as the address bus for the 68HClZ They are not usable as 10 by the programmer Port A is the high order byte and port B is the low order byte Ports C and D are used as the data bus for the 68HClZ They are not usable for 10 by the programmer Port C is the high order byte and port D is the low order byte Port E is used to generate control signals needed to access the external memory As a result the programmer can not use it for 10 Port E pin 1 is used as the input for the IRQ and Port E pin 0 is used as the input for the XIRQ Port E is used to control chip selects for the external memory and other chips The programmer can not use it as 10 Port G is a 6bit general purpose lO port The direction of the port is controlled by iHlZDDRG When an iHlZDDRG bit is set to O the port pin is an input and when it is set to 1 it is an output Port H is an 8bit general purpose lO port The direction of the port is controlled by the iHlZDDRH When iHlZDDRH bit is set to O the port pin is an input and when it is set to 1 it is an output Port J is an 8bit general purpose lO port The direction of the port is controlled by the iHlZDDRJ When iHlZDDRJ bit is set to O the port pin is an input and when it is set to 1 it is an output Port S is used for the SCI and the SP1 It can also be used for general lO if the SCI or SPI are not being used Bits O and l are 8010 These are used as the interface to the terminal and can not be used as 10 Bits 2 and 3 are 8011 and bits 47 are the SP1 These can be used as general lO if 8011 and the SP1 are not being used The direction of the port is controlled by iHlZDDRS Port T is used for the timer interrupts and the pulse accumulator If the interrupts are not being used then Port T can be used for general 10 The port direction is controlled by iHlZDDRTT Note The two T39s are not a typo Port AD is used exclusively as the input to the A to D converter It can not be used for any other lO Ports G H and Port E pin 0 have optional pullup resistors inside These are controlled by the iHlZPUCR register To enable the pullup resistor for Port H write a one to bit 7 for Port G write a one to bit 6 for Port E write a one to bit 4 of iHlZPUCR To disable the pullup resistors to a particular port write a O to the appropriate bit A to D Converter This section covers the basic function of the AD converter The AD converter uses a dedicated port port AD for its inputs There are 8 AD converter channels on the H012 and unlike the 6811 there are also 8 AD registers allowing 8 simultaneous readings The implementation of the AD converter allows for two different methods of operating the AD converter This section covers the polling method The interrupt based operation is explained in the section on interrupts The AD converter conversion seguence consists of either 4 or 8 conversions and can convert either one channel or multiple channels In scan mode operation polling based operation the flag is set after the conversions have been completed signaling the completion of the AD cycle Before running the AD converter the system must be initialized by the user There are 4 registers that are used to control the AD Converter These are iHlZADTCTLZ iHlZADTCTL3 iHlZADTCTL4 and iHlZADTCTLS iHlZADTCTLZ contains several of the AD Converter enable bits Bit 7 is the AD power up ADPU When this is set to one the AD converter is enabled when it is zero then the AD converter is disabled Bit 1 is the AD converter interrupt enable ASCIE The interrupt is enabled when the bit eguals one and disabled when the bit is set to zero In scan mode this bit is set to O to disable interrupts Bit O is the interrupt flag ASCIF which is not used in the polling version of the AD converter iHlZADTCTLZ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ADPU AFFC AWAI lunused unused unused ASCIE ASCIF iHlZADTCTL3 should always be set to 0x00 This is used to control several actions that are related to how the AD converter operates in background debug mode As the DBung monitor is being used the background debug mode is not being used and these features should be disabled iHlZADTCTL4 is used to select the sample time of the AD converter and to set the prescalar for the clock iHlZADTCTL4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit l bit 0 unused SMPl SMPO PRS4 PRS3 PRSZ lPRSl PRSO There are four different sample times available for the AD converter The sample time is selected by setting the value of SMPl and SMPO The different sample times that can be used are listed in table 1 Table 1 Sample Times SMP1 SMP0 Sample Time 0 O 2 AD clock periods 0 l 4 AD clock periods 1 O 8 AD clock periods 1 l 16 AD clock periods The prescalar that is used by the AD converter is determined by the value of PRSO PRS4 The clock input to the prescalar is an 8 MHz clock This allows for an AD conversion frequency of 500 kHz to 2 MHZ The different prescalar values are listed in Table 2 Table 2 Prescalar Values Prescale Value Divisor 00 Do not use 00001 4 00010 6 00011 8 00100 10 00101 12 00110 14 00111 16 lexx Do not use 1xxxx Do not use 7H12ADTCTL5 is used to select the conversion mode which channels are to be converted and to initiate the conversions The conversion sequence is started by any write made to this register If a write is made to this register while a conversion sequence is in progress the conversion is aborted and the SCF and CCF flags are reset iHlZADTCTLS bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused SBCM SCAN MULT CD CC CB CA SBCM is used to select between making 4 conversions when the bit is set to zero and 8 conversions when the bit is set to one SCAN is used to select between performing either a single conversion or multiple conversions If SCAN is set to zero then a single conversion will be run and the flag will then be set If SCAN is set to 1 then the AD converter will run continuous conversions on the AD channels MULT determines whether the conversion is run on a single channel or on multiple channels When MULT zero the AD converter runs all the conversions on a single channel which is selected by CDCCCB and CA When MULT is one the conversion is run on several different channels in the group specified by CDCCCB and CA The possible channel combinations are in Table Table 3 AD Converter Settings SBCM CD CC CB CA Channel Signal Result in ADRx if MULT 1 0 0 0 0 ANO ADRO 0 0 0 0 1 AN1 ADR1 0 0 0 1 0 ANZ ADRZ 0 0 0 1 1 AN3 ADR3 0 0 1 0 0 AN4 ADRO 0 0 1 0 1 ANS ADR1 0 0 1 1 0 AN6 ADRZ 0 0 1 1 1 AN7 ADR3 0 1 0 0 0 Reserved ADRO 0 1 0 0 1 Reserved ADR1 0 1 0 1 0 Reserved ADRZ 0 1 0 1 1 Reserved ADR3 0 1 1 0 0 V RH ADRO 0 1 1 0 1 V RL ADR1 0 1 1 1 0 V RH V RL 2 ADRZ 0 1 1 1 1 TESTReserved ADR3 1 0 0 0 0 ANO ADRO 1 0 0 0 1 AN1 ADR1 1 0 0 1 0 ANZ ADRZ 1 0 0 1 1 AN3 ADR3 1 0 1 0 0 AN4 ADR4 1 0 1 0 1 ANS ADRS 1 0 1 1 0 AN6 ADR6 1 0 1 1 1 AN7 ADR7 1 1 0 0 0 Reserved ADRO 1 1 0 0 1 Reserved ADR1 1 1 0 1 0 Reserved ADRZ 1 1 0 1 1 Reserved ADR3 1 1 1 0 0 V RH ADR4 1 1 1 0 1 V RL ADRS 1 1 1 1 0 V RH V RL 2 ADR6 1 1 1 1 1 TESTReserved ADR7 Stared bits are don t care if MULT 1 and the entire block of four or eight channels make up a conversion sequence When MULT 0 all four bits CD CC CB and CA must be specified and a conversion sequence consists of four or eight consecutive conversions of the single specified channel iHlZADSTAT is used to determine the status of the conversion process Unlike most of the registers in the HC12 this is a 16bit register The Seguence Complete Flag SCF is used to signal the completion of the conversion cycle When SCAN 0 the setting of the SCF signals the completion of the cycle when SCAN 1 it signals the completion of the first conversion cycle iHlZADSTAT bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 SCF Iunused Iunused lunused lunused ICCZ ICC1 ICCO CCF7 ICCF6 ICCFS ICCF4 ICCF3 ICCFZ ICCF1 ICCFO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CC2CCO are the conversion counter They are the pointer for the conversion cycle and reflect which result register will be written to next CCF7CCFO are the Conversion Complete Flags CCF for the individual AD channels When the conversion sequence for a channel has been complete the flag is set The flags can be cleared by reading the AD register for the channel and by reading the 7H12STAT register The results of the AD conversions are stored in the AD converter result registers These registers are called 7H12ADR0H through 7H12ADR7H When converting multiple channels the destination register used to store the results of each channel that is converted is listed in Table 3 When converting a single channel the results are in 7H12ADR0H 7H12ADR3H for a 4 conversion sequence and 7H12ADR0H 7H12ADR7H for an eight conversion seguence Sample Code This code turns on the AD converter while disabling the AD interrupt It then performs 4 conversions on channel 0 of the AD converter and displays the result that is stored in the result registers to the screen 7H12ADTCTL20X80 turn on ATD and off the interrupt 7H12ADTCTL30X00 don39t stop at breakpoints 7H12ADTCTL40X43 Set prescalar 8 amp sample time 8 periods 7H12ADTCTL50X00 check ANO 4 conversions and stop whilel7H12ADTSTAT amp 0X8000 wait for flag to be set DB12gtout2hex7H12ADR0H Display AD result registers DB12gtprintfquotnrquot 10 DB12gtout2hex7H12ADRlH DB12gtprintf quotnr DB12gtout2hex7H12ADR2H DB12gtprintf quotnr DB12gtout2hex7H12ADR3H Timer Functions This section covers the operation of the timer module when it is used for non interrupt based operations such as output compare and input capture functions Interrupt based timer features are discussed in chapter 5 The basics of timer module operation There are several basic features of timer module that apply to both the input capture and output compare functions as well as interrupt driven Timer functions In order to make use of any timer based operations the timer module must first be enabled This is done by setting iHlZTSCR to 0x80 This will set the Timer Enable bit TEN which then enables all timer operations iHlZTSCR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TEN ITSWAI TSBCK TEECA unused unused unused unused The Timer uses a counter also called a free running counter that is incremented by one every clock pulse The free running counter on the 68HClZ can be accessed by the user if needed The free running counter is a 16bit value that is stored in the register iHlZTCNT It can be read at anytime but can not be written to by the user Port T is used as 10 pins for the timer input capture and timer output compare Each pin can serve as either an input capture or output compare pin The function of the pin is selected by the state of the iHlZTlOS register Each bit in iHlZTlOS corresponds to a pin of Port T When the bit is set to O the pin is used as an input capture when the bit is set to a one the pin is used as an output compare Any combination of input captures and output compares can be selected by the user iHlZTIOS bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 The data for the input captures and output compares are stored in iHlZTCO to iHlZTC7 These are 16 bit registers For input capture operations the value of the free running counter will be latched into the register when the input capture is triggered For output compare operations the value in the register is used to trigger an action The 68HClZ also allows the user to assign pullup resistors to the timer module inputs This is done by writing a one to TPE in iHlZTMSKZ This will enable the pullups A zero will disable them iHlZTMSKZ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TOIE unused TPE TDRB TCRE PR2 PR1 PRO Timer Output Compare The output compare on the 68HClZ is very similar to that of the 68HCll The user selects an action to occur when the output compare is triggered and the time at which the action occurs The processor will then carry out this action accordingly The first step is to select which channels will be used This is done by using the iHlZTlOS register as explained above Having done this the next step is to select when the output compare will trigger This is done by writing a value to the iHlZTCx registers that correspond to the channels that was selected as an output compare in iHlZTlOS It is then necessary to determine what action will occur when the output compare is triggered There are several different actions that are possible which one occurs is determined by the values in iHlZTCTLl and iHlZTCTLZ These registers contain the control bits for each channel OMn and OLn The effect that the different values have are listed in Table 4 Table 4 Output compare actions OMn OLn Action 0 O Timer disconnected from output logic 0 l toggle Ocn output line 1 0 clear Ocn output line to O l 1 set Ocn output line to l iHlZTCTLl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0M7 0L7 0M6 0L6 OMS 0L5 0M4 0L4 iHlZTCTLZ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0M3 0L3 0M2 0L2 OMl OLl OMO OLO Having determined the action taken on a successful match the next step is to make sure timer interrupts are disabled This is done by writing 0x00 to iHlZTMSKl Lastly the timer module is enabled as shown above allowing the output compare to trigger It is important to note when using the output compare that when an output compare action is triggered the corresponding bit of Port T will automatically be set as an output regardless of the state of DDRTT Sample Code This code sets up an output compare and causes the pin output to toggle when the interrupt is triggered iHlZTIOSOxFF iHlZTMSKlOxOO set up the channels as output compare no hardware interrupts iHlZTCTLlOx5A set 007 006 for toggle 005004 clear iHlZTCTL2Ox5F set 003 002 for toggle OClOCO set iHlZTCOOxOOOO set different trigger times iHlZTClOx2000 7H12T020x4000 iHlZTC3Ox6000 iHlZTC4Ox8000 7H12T050xA000 iHlZTC6OxCOOO iHlZTC7Ox9000 iHlZTSCROx80 turn on the timer l3 Output Compare 7 Output Compare 7 has a special feature that makes it very powerful Output Compare 7 allows the programmer to change the state of any of the output compare pin without changing the operation that is performed by that Output Compare This is particularly useful for generating pulsewidth modulated signals Anyone interested in this particular application should refer to the LITEC manual for more detailed information on pulsewidth modulation The method for using output compare 7 to control the other output compares is set up as follows Just as with any other output compare operation the time at which 007 is triggered must be stored in iHlZTOC7 The next step is to select which channels will be controlled by 007 and what will occur when 007 triggers This is done using the iHlZOC7M and iHlZOC7D registers iHlZOC7M is used to select which channels are controlled by OC7 Writing a one to a bit in iHlZOC7M assigns control of the corresponding channel to OC7 The data that is output by the channel is stored in iHlZOC7D When OC7 is triggered for each bit that is set in iHlZOC7M the corresponding data bit in iHlZOC7D is written to the output compare pin A successful 007 event can be used to cause the free running counter to be reset This is done by writing a one to TCRE in iHlZTMSKZ Note if you write a one and set the OC7 event for 0000 the free running counter will stay at 0000 Similarly if you set OC7 for FFFF the Timer Overflow Flag will never be set See Timer Overflow Interruth iHlZOC7M bit 7 bit 6 bit 5 bit 4 it 3 bit 2 bit 1 bit 0 oc7M7 oc7M6 oc7M5 oc7M4 oc7M3 oc7M2 OC7Ml OC7M0 7H12007D bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OC7D7 OC7D6 oc7D5 OC7D4 OC7D3 OC7D2 OC7Dl OC7D0 iHlZTMSKZ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TOTE unused TPE TDRB TCRE PR2 PR1 PRO Sample Code This code simply shows how to setup OC7 iHlZTC70x4000 Set up the time when the OC triggers iHlZOC7M0x01 select channe O iHlZOC7D0x00 cause channel 0 to output a low when triggered Timer Compare Force Register This is a special register that allows the programmer to cause an output compare to trigger Writing to bit n in this register causes the action which is programmed for output compare n to occur immediately This is the same as if a successful comparison had just taken place with the TCn register iHlZCFORC bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 F007 FOC6 F005 F004 F003 F002 F001 F000 Input Capture The operation of the input capture is similar to that of the output compare The first step is to set up the appropriate Port T bits as input capture pins using HlZTlOS Having done that it is then necessary to select how the input capture will be triggered This is done using iHlZTCTL3 and iHlZTCTL4 Each channel has two control bits EDGXB and EDGXA which determine which edge triggers the input capture The different configurations of these bits are in Table 5 Table 5 Input Capture selects EDGXB EDGXA Configuration 0 0 Capture disabled 0 1 Capture on rising edge 1 0 Capture on falling edge 1 1 Capture on any edge iHlZTCTL3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EDG7B EDG7A EDG6B EDG6A EDGSB EDGSA EDG4B EDG4A iHlZTCTL4 bit 7 bit 6 bi i bit 2 bit 1 bit 0 EDG3B EDG3A EDGZB EDGZA EDGlB EDGlA EDGOB EDGOA Just as with the output compare operation the timer interrupts must be disabled and the timer module must be enabled The values that are read in by the input capture are stored in the appropriate iHlZTCx register Sample Code This code captures the time of iHlZTCNT when a switch is pressed by the user iHlZTMSKlOxOO turn off interrupts iHlZTlOSOxOO Set up Port T for input capture iHlZTCTL3Ox5A 1C7 1C6 rising edge 1C5 1C4 falling edge iHlZTCTL4Ox5F 1C3 1C2 rising edge lCl lCO any edge iHlZTSCROx80 turn on the timer 5 Interrupt Service Routines Overview Overview The 68HClZ provides a wide array of interrupts that can be used by the programmer Some of these are similar to interrupts found on the 68HCll such as the RTI and timer overflow Others are new to the 68HClZ such as the key wakeups and AD converter interrupts This section will cover all the different ISRs and how they operate Interrupts on the 68HClZ are controlled in part through the DBung monitor program The SetUserVector routine in the DBung monitor is used to program the ISR vector table that tells the processor where the different ISRs are located in memory When using a particular interrupt the ISR must be assigned to the interrupt in the beginning of the program Each interrupt has an address offset to the interrupt vector table base address which is stored in the DBung header file When assigning the interrupt SetUserVector is called and the name of the interrupt as well as the ISR name are passed as parameters This will store the address of the ISR in the vector table For example If you are using the Real Time Interrupt RTI and have it call an ISR called RTIInt when it is triggered the code would look like DBlZgtSetUserVectorRTI RTIInt The list below is all of the interrupts and their mnemonics AtoD A to D converter interrupt PAEdge Pulse Accumulator Edge triggered PAva Pulse Accumulator Overflow triggered Timerva Timer Overflow Timer7 Timer 7 Timer6 Timer 6 Timer5 Timer 5 Timer4 Timer 4 Timer3 Timer 3 Timer2 Timer 2 Timerl Timer 1 TimerO Timer 0 RTI Real Time Interrupt IRO IRO interrupt XIRO XIRO interrupt The format of the ISR is show below All ISRs follow this format ifmodegyvoid RTIIntO your code here l It also must include a function prototype of the format ifmodegyvoid RTIInt Note There are 2 underscores both before and after the mod2 Interrupt Priority Interrupts on the 68H012 do not all occur simultaneously Rather there is a hierarchy of priority for the interrupts The default priority order is 1 Reset 2 COP Clock Monitor Eail Reset 3 COP Failure Reset 4 Trap 5 SW1 6 XIRQ 7 IRQ 8 RTI 9 TimerO 10 Timerl 11 Timer2 12 Timer3 13 Timer4 14 TimerS 15 Timer6 16 Timer7 17 Timerva 18 PAOVf 19 PAEdge 20 SP1 21 8010 22 8011 23 AtoD 24 PortJKey 25 PortHKey The priority of these can be changed by using iHlZHPRIO register The first six interrupts are unmaskable and can not have their priority changed The other interrupts are all maskable and may have their priority changed An interrupt may be made the highest priority interrupt by writing its address value to iHlZHPRIO The address values are listed below in hex for each interrupt IRQ F2 RTI F0 TimerO EE Timerl EC Timer2 EA Timer3 E8 Timer4 E6 TimerS E4 Timer6 E2 Timer7 EO Timerva DE PAOVf DC PAEdge DA 1 D8 SCIO D6 SCll D4 AtoD D2 PortJKey DO PortHKey CE Interrupt Service Routines example code and explanations This section includes explanations of all the different interrupts and sample code of the function Real Time Interrupt Operation The operation of the RTI is controlled by iHlZRTICTL Bit 7 is the Real Time Interrupt Enable RTIE Writing a one to this bit will enable the RTI The rate at which the RTI is triggered is determined by the Real Time Interrupt Rate RTR The different rates are listed in Table 6 Table 6 RTI rate RTRZ RTRl RTRO Period 0 off 0 O l 1024ms O l O 2048ms O l l 4096ms l O O 8196ms l O l 16384ms l l O 32768ms l l l 65536ms iHlZRTICTL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RTIE RSWAI RSBCK unused RTBYP IRTRZ lRTRl RTRO After the interrupt is triggered the ISR must clear the flag This is done by writing a one to the Real Time Interrupt Flag RTIF in iHlZRTIFLG register iHlZRTIFLG bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 RTIF unused unused unused unused unused unused unused Sample Code This is a simple program to count the number of RTI interrupts that have occurred iimodzig void RTIInt function prototype int Timecount global variable void igmain DBlZgtSetUserVectorRTIRTIInt set up interrupt vector TimeCount 0 iHlZRTICTLOx87 set up the RTI for 65536ms while 1 DBlZgtout2heXTimecount ifmodegyvoid RTIInt interrupt service routine Timecount iHlZRTIFLGOx80 clear the flag Timer Overflow Interrupt Operation The Timer Overflow Interrupt TOI functions by generating an interrupt every time the quotfree runningquot counter overflows The free running counter is a 16 bit value and is constantly running in the background when the timer is enabled The TOI is set up in the iHlZTMSKZ register by writing a one to Timer Overflow Interrupt Enable TOIE After this has been done the Timer can be enabled Whenever the interrupt is triggered the ISR will be called and executed The ISR must clear the flag by writing a one to the Timer Overflow Flag in the iHlZTFLGZ register iHlZTMSKZ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit I bit 0 TOIE unused TPE TDRB TCRE PR2 PRl PRO iHlZTFLGZ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit I bit 0 TOF unused unused unused unused unused unused unused Sample Code This code calls an interrupt every time the Timer Overflow Interrupt occurs ifmodegyvoid TimervaInt function prototype void igmain DB12gtSetUserVectorTimerva TimervaInt iHlZTMSK2Ox80 enable interrupt iHlZTSCROx80 enable the timer whilel idle loop l ifmodegyvoid TimervaInt Timer Overflow ISR DB12gtprintfquotOverflow interruptquot iHlZTFLG2Ox80 clear the flag Pulse Accumulator Edge Triggered Interrupt Operation This section describes how to set up the Pulse Accumulator for edge triggered operation The Pulse Accumulator is enabled by setting the Pulse Accumulator Enable PAEN in iHlZPACTL to one There are two other control bits in iHlZPACTL PAMOD and PEDGE When PAMOD equals zero the pulse accumulator is in event counter mode when it is one it is in gated time accumulation mode PEDGE has different effects based on the state of PAMOD When PAMOD equals zero If PEDGE equals 0 then falling edges on the pulse accumulator input pin Port T bit 7 causes the count to be incremented If PEDGE equals 1 then rising edges on the input cause the count to be incremented When PAMOD equals one If PEDGE equals 0 when the pulse accumulator input pin goes high it enables an internal clock which is connected to the pulse accumulator and the trailing falling edge on the pulse accumulator input sets the PAIF flag The internal clock used to increment the pulse accumulator is 8MHZ64 If PEDGE equals one when the pulse accumulator input pin goes low it enables an internal clock which is connected to the pulse accumulator and the trailing rising edge on the pulse accumulator input sets the PAIF flag The internal clock used to increment the pulse accumulator is 8MHZ64 The timer must be enable to use these since the clock generated is based on the timer prescaler CLKl and CLKO are used to control the clock rate at which the pulse accumulator is incremented The different options are listed in Table 7 Table 7 Pulse Accumulator Clock Rates CLKl CLKO Selected clock 0 O timer prescaler O l BMHZ clock 1 O 8MHZ256 clock 1 l 8MHZ65536 clock PAI is the Pulse Accumulator Edge triggered interrupt enable This must be set to l to enable edge triggered interrupts iHlZPACTL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused PAEN PAMOD PEDGE CLKl CLKO PAOVI PAI After setting PACTL the hardware will trigger an interrupt whenever the correct edge is detected at Port T The ISR must clear the flag by writing a one to the Pulse Accumulator Interrupt Flag PAIF in iHlZPAFLG iHlZPAFLG bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused unused unused unused unused unused PAOVIF PAIF The value of the pulse accumulator is stored in iHlZPACNT Sample Code This code detects the edge and triggers an interrupt ifmodegrvoid PAEdgelnt function prototype void igmain DBlZgtSetUserVectorPAEdge PAEdgelnt iHlZPACTLOx55 set the pulse accumulator rising edge whilel wait i l l ifmodegrvoid PAEdgelnt Pulse Accumulator ISR DBlZgtprintfquotPulse Accum triggered nquot iHlZPAFLGOxOl clear the flag Pulse Accumulator Overflow Triggered Interrupt Operation This operation triggers an interrupt every time the pulse accumulator overflows Whenever the pulse accumulator overflows from OXFFFF to OXOOOO trigger interrupt the ISR will The set up of this interrupt is very similar to the edge triggered although PAMOD and PAEDGE have no effect on the interrupt Most of the other settings are the same as for the edge triggered operation of the Pulse Accumulator However instead of setting PAI to one for Overflow operation PAOVI 15 set to one The user must clear the flag in the ISR by writing a l to PAOVIF in the iHlZPAFLG register HlZPACTL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused PAEN PAMOD PEDGE CLKl CLKO PAOVI PAI HlZPAFLG bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused unused Unused unused unused unused PAOVIF PAIF Sample Code This code simply displays when the interrupt is triggered ifmodegrvoid PAvalnt function prototype void igmain DBlZgtSetUserVectorPAva PAvaInt iHlZPACTLOx46 whilel set for pulse accumulator overflow wait ifmodegrvoid PAvalnt Pulse Accumulator ISR DBlZgtprintfquottriggeredquot iHlZPAFLGOx02 clear the flag Output Compare Interrupt Operation The output compare interrupt calls an ISR every time a successful output compare is detected The output compare is setup like the non interrupt based output compare with the major difference being that the action which is to occur on a successful compare does not need to be specified Instead iHlZTMSKl is used to determine which channels will be used to generate an interrupts Each bit in iHlZTMSKl corresponds to a different output compare channel When the interrupt is generated the ISR for that channel is called and executed The flag must be cleared by writing a one to the bit iHlZTFLGl register that corresponds to the channel which triggered the interrupt iHlZTMSKl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 071 061 051 041 031 021 011 001 iHlZFLGl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 07F 06F CSF 04F 03F CZF ClF COF Sample Code This code calls the ISR when the Output Compare 0 generates an interrupt ifmodegrvoid TimerOlnt function prototype void igmain DBlZgtSetUserVectorTimerO TimerOInt iHlZTIOSOxFF select output compare iHlZTMSKlOxOl enable the interrupt on pin 0 iHlZTCOOx8000 set the value to be compared against iHlZTSCROx80 enable the timer whilel wait i l l ifmodegrvoid TimerOlnt Output Compare ISR DBlZgtprintfquottimer intquot iHlZTFLGlOxOl clear the flag Input Capture Interrupt Operation Like the output compare interrupt the input capture interrupt is very similar to the noninterrupt based input capture The iHlZTIOS and iHlZTCTL3 and iHlZTCTL4 are set up the same as for the noninterrupt input capture The difference is that iHlZTMSKl is used to determine which channels will be used to generate an interrupts Each bit in iHlZTMSKl corresponds to a different input capture channel When the interrupt is generated the ISR for that channel is called and executed The flag must be cleared by writing a one to the bit in the iHlZTFLGl register that corresponds to the channel which triggered the interrupt iHlZTMSKl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 071 061 051 041 031 021 011 001 iHlZFLGl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 07F 06F CSF 04F 03F CZF ClF COF Sample Code This code calls the ISR when the input capture generates an interrupt ifmodegyvoid TimerOlnt function prototype void igmain DBlZgtSetUserVectorTimerO TimerOInt iHlZTIOSOxOO select input capture iHlZTMSKlOxOl enable the interrupt on pin 0 iHlZTCTL3Ox5A 107 106 rising edge ICS 104 falling edge iHlZTCTL4Ox5F 103 102 rising edge 101 100 any edge iHlZTSCROx80 enable the timer whilel wait i l l ifmodegyvoid TimerOlnt Output Compare ISR DBlZgtprintfquottimer intquot iHlZTFLGlOxOl clear the flag A to D Converter Interrupt Operation This is similar to the noninterrupt based AD converter However instead of having to poll the flag to determine when the AD cycle has been completed an interrupt is generated when the conversion is completed In order to make use of the AD interrupt the ASCIE bit in iHlZADTCTLZ must be set to 1 This way when the conversion is completed the interrupt will be triggered The flag is cleared by writing a one to ASCIF in iHlZADTCTLZ The remainder of the operation is the same as the noninterrupt based AD converter iHlZADTCTLZ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ADPU AFFC AWAI lunused unused unused lASCIE ASCIF Sample Code This sample code calls the AD interrupt when the AD cycle is completed ifmodegrvoid AtoDlnt Function prototype void igmain main program DBlZgtsetUserVectorAtoD AtoDlnt set the vector address iHlZADTCTL2OX82 turn on ATD and on the interrupt iHlZADTCTL3OXOO don39t stop at breakpoints iHlZADTCTL4OX43 Set prescalar 8 amp sample time 8 periods iHlZADTCTL5OXOO check ANo whilel infinite loop l l ifmodegrvoid AtoDInt AD ISR DBlZgtout2hex7HlZADROH DBlZgtprintfquotnrquot DBlZgtout2hex7HlZADRlH DBlZgtprintfquotnrquot DBlZgtout2hex7HlZADR2H DBlZgtprintfquotnrquot DBlZgtout2hex7HlZADR3H iHlZADTCTL2OX83 iHlZADTCTL5OXOO print contents of registers reset the AD converter IRQ Interrupt Operation The IRQ is used to generate external interrupts There are two basic modes of operation for the IRQ One is falling edge triggered the other is low level detection The mode of the IRQ is controlled by iHlZINTCR IRQEN is used to turn on the IRQ When this bit is set to l the IRQ is enabled when it is set to zero the IRQ is disabled IRQE determines whether low level or edge triggered operation will be used When this bit is O the IRQ will use low level detection When it is l the IRQ will be falling edge triggered The IRQ is automatically cleared by the hardware in the 68HClZ There are a few differences between the IRQ on the H011 and the HClZ Unlike the HCll the IRQ is not time protected IRQEN may be written to and read from at any time The value of IRQE however may only be written once in the program iHlZINTCR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IRQE IIRQEN IDLY unused lunused lunused unused unused Sample Code This is sample code that triggers the IRQ every time a falling edge is detected This assumes there is a switch of some sort on the IRQ input to generate the falling edge ifmodegrvoid IRant function prototype void igmain DBlZgtSetUserVectorlRQ IRQInt set up the vector iHlZINTCROxCO set up the IRQ for falling edge triggered whilel infinite loop l l iimodzii IRant IRQ ISR DBlZgtprintfquotIRQ triggeredquot display a message Port H Key Wakeup Interrupt Operation This is a new feature that was incorporated into the HClZ This generates an interrupt when the appropriate edge is detected on the input to the port This is ideal for use with a keypad or can be used as extra IRQ lines for the HClZ Each bit of Port H can be used to generate a Key Wakeup interrupt when a falling edge is detected It is important to note that even though each bit can generate an interrupt independently of the others the same interrupt will be called regardless of which bit triggered it The Key Wakeup Interrupt for each individual bit is enabled using iHlZKWIEH Writing a l to a bit in the register will enable the corresponding bit of Port H to generate an interrupt when a falling edge is detected The flag bits for the Key Wakeup interrupt are located in iHlZKWIFH Multiple flags can be set at the same time although software must be written in order to determine which flags have been set The flags are cleared by writing a one to the flag bits that have been set It is a good idea to clear the flags before the Key Wakeup Interrupt is enabled to prevent any false triggers iHlZKWIEH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iHlZKWIFH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Sample Code This code will trigger a Port H Key Wakeup interrupt when a falling edge is detected on any bit of Port H ifmodegrvoid KeyHvoid function prototype void iimainvoi DBlZgtSetUserVectorPortHKeyKeyH Set Vector address iHlZKWIFHOxFF make sure flags aren39t set iHlZKWIEHOxFF Enable all key wakeups for port H while 1 l l l ifmodegrvoid KeyHvoid Port H Key Wakeup ISR 7H12Kw1FH7H12Kw1FH clear the flags Port J Key Wakeup Interrupt Operation The Port J key Wakeup Interrupt is a more Interrupt Unlike the Port H Key Wakeup rising edge or a falling edge input wakeup but also adds to the complexity powerful version of the Port H Key Wakeup Port J can be set to trigger on either a This adds to the flexibility of the key The selection of which bits will be used to generate interrupts is controlled by iHlZKWIEJ As with port H when a bit is set to l the Key Wakeup for that channel is enabled Also as with the Port H Key Wakeup while each bit can cause an interrupt they all call the same interrupt service routine iHlZKWIEJ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iHlZKWIFJ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Before enabling the Key Wakeup Interrupt it is necessary to set which edge will trigger the interrupt and to select to use either the pullup or pulldown resistors on the input Which edge will be used to trigger an interrupt is determined by the setting of Writing a zero to a bit of iHlZKPOLJ makes that channel falling edge iHlZKPOLJ triggered Writing a one makes the channel rising edge triggered iHlZKPOLJ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 The pullup and pulldown resisters are controlled by iHlZPUPSJ and iHlZPULEJ iHlZPUPSJ selects between using pullup resisters and pulldown resisters bit in iHlZPUPSJ is set to one the channel has a pullup resistor is zero there is a pulldown resistor on pulluppulldown resistors are enabled pulldown resistor zero will disable it Writing a one enables the pullup or pulldown When a When the bit the input This MUST be set before the iHlZPULEJ is used to enable the pullup or while writing a HlZPULEJ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 HlZPUPSJ bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 As with the Port H Key Wakeup the flags Interrupt is triggered This is done by that have been set Sample Code are cleared after a Port J Key Wakeup writing a one to the bits in iHlZKWIFJ This code sets up the Port J Key Wakeup for falling edge operation on all 8 channels and enables the pull up resistors for all the bits ifmodegyvoid KeyJvoid function prototype void iimain void DBlZgtSetUserVectorPortJKey iHlZKPOLJOXOO iHlZKWIFJOXFF iHlZPUPSJOXFF iHlZPULEJOXFF iHlZKWIEJOXFF while 1 l l ifmodegrvoid KeyJvoid iHlZKWIFJ7HlZKWIFJ KeyJ assign the vector address falling edge sets flag clear any flags that may be set pull up pull up enabled all bits Enable all bits of J for keypad Infinite loop function prototype clear the flag 0 push button connection between grid wires W Pins normally pulled high through pullup resistors in I V 6812 switch closure will temporally pull bit low Pins normally grounded held low Keypad Wiring diagram The keypad is a passive device with only switches that connect Wires on the crosspoint matrix of 4 x 4 Wires CONDUCTIVE RUBBER KEYPADS CODE AND TRUTH TABLES Terminals are identified on the keyboard 12 Button Keypads a X h BUTTON LOCATION TERMINAL LOCATION Dots in the chart indicate connected terminals when switch is closed BUTTON LOCATION 16 Button Keypads TERMINAL SPECIFICATIONS Rating Criteria Rating at 12 Vdc 5 milliamps for 5 seconds Contact Bounce lt 12 milliseconds Contact Resistance lt 100 ohms stated operating force Voltage Breakdown 250 Vac between components Mechanical Operation Life 3000000 operations per key Insulation Resistance gt 10 Zohms 500 Vdc Push Out Force Per Pin 5 lbs Operating Features Travel 040 minimum Operating Force 175 x 40 grams Operating Temperature 30 C to 80 C Material and Finishes Terminal Pin Phosphor bronze solder plated PC Board FR4 glass cloth epoxy Keypad Silicone rubber durometer 50 2 5 Housing ABS cycolac KJW Housing Color Black STANDARD LEGENDS 12 Position 102 Legend Black legends on white button 152 Legend White legends on black button 16 Position 0065 Legend Black legends on white button 056 Legend White legends on black button See page 04 for Standard Legend configura tions ORDERING INFORMATION 96A32102F T Grayhill Series Number Size Option A3x4 B4x4 Circuitry BZMatrix terminal pin header 02Single PoleCommon Bus Mounting Option FFront panel mount RRear panel mount Standard Legend Choices 12 Position legends 102Black legends on a white button 152White legends on a black button 16 Position legends 006Black legends on a white button 056White legends on a black button Available from your local Grayhill Distributor For prices and discounts contact a local Sales Office an authorized local Distributor or Grayhill I ruy lll C7 An iso soot Cuntpany 561 Hillgrove Avenue LaGrange Illinois 60525 0 USA Phone 708 3541040 Fax 708 3542820 httpwwwgrayhilleom 31
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