Computer Architecture II
Computer Architecture II ECE 332
Popular in Course
Dr. Reina Hane
verified elite notetaker
Mrs. Demarcus Breitenberg
verified elite notetaker
verified elite notetaker
verified elite notetaker
verified elite notetaker
Mrs. Demarcus Breitenberg
verified elite notetaker
Popular in Electrical Engineering & Computer Science
This 25 page Class Notes was uploaded by Dr. Reina Hane on Monday October 19, 2015. The Class Notes belongs to ECE 332 at Rose-Hulman Institute of Technology taught by Staff in Fall. Since its upload, it has received 8 views. For similar materials see /class/225092/ece-332-rose-hulman-institute-of-technology in Electrical Engineering & Computer Science at Rose-Hulman Institute of Technology.
Reviews for Computer Architecture II
Report this Material
What is Karma?
Karma is the currency of StudySoup.
You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!
Date Created: 10/19/15
A Basic Overview of Commonly Encountered types of Random Access Memory RAM ECE332 B y Peter Haugen Ian Myers Bret Sadler John Whidden x quotm he 3K 1 mquot 39 Scmmxmducnrng mun quotMWquot N Wm Wu K Hand mm mm 5mm i 7 WW Magnum m mm Figure 1 Munury Hizmchy Simuncelli mun Basic RAM Overview RAM Random Access Memory is the hardware location in a computer where the operating system application programs and data in current use are kept so that they can be quickly reached by the computer39s processor RAM is much faster to read from and write to than most other kinds of storage in a computer the hard disk oppy disk and CD ROM However the data in RAM stays there only as long as it has power When you turn the computer off RAM loses its data When you turn your computer on again your operating system and other les are once again loaded into RAM usually from your hard disk RAM can be compared to a person s shortterm memory and the hard disk to the long term memory The shortterm memory focuses on work at hand but can only keep so many facts in view at one time Ifshortterm memory lls up your brain sometimes is able to refresh it from facts stored in longterm memory A computer also works this way If RAM fills up the processor needs to continually go to the hard disk to overlay old data in RAM with new slowing down the computer39s operation Giakamozis 1999 Why Random Access RAM is called quotrandom accessquot because any storage location can be accessed directly Originally the term distinguished regular core memory from of ine memory usually on magnetic tape in which an item of data could only be accessed by starting from the beginning of the tape and finding an address sequentially Perhaps it should have been called quotnonsequential memoryquot because RAM access is hardly random Giakamozis 1999 RAM is organized and controlled in a way that enables data to be stored and retrieved directly to specific locations A term IBM has preferred is direct access storage or memory Giakamozis 1999 Note that other forms of storage such as the hard disk and CD ROM are also accessed directly or quotrandomlyquot but the term random access is not applied to these forms of storage In addition to hard disk oppy disk and CD ROM storage another important form of storage is readonly memory ROM a more expensive kind of memory that retains data even when the computer is turned off Every computer comes with a small amount of ROM that holds just enough programming BIOS so that the operating system can be loaded into RAM each time the computer is turned on What RAM architecture Looks Like In general RAM is much like an arrangement of cells in which each cell can hold a 0 or a 1 Each cell has a unique address that can be found by counting across columns and then counting down by row To find the contents of a cell the RAM controller sends the columnrow address down a very thin electrical line etched into the chip There is an address line for each row and each column in the set of cells Ifdata is being read the bits that are read ow back on a separate data line In describing a RAM chip or module a notation such as 256le6 means 256 thousand columns of cells standing 16 rows deep transistors and the paths that eohheet them fRAM o d u m R M h ll charge helolm somethmg slmllarto an eleetheal capacltor Athahslstoh aets as agate m oletehmmmg whether the value m the capacltor eah be read or wmtteh 1h statae RAM wnh ohe poslhoh meanmg l and the otherposmon meanmg 0 F V m H gge To aolol our RAJ eoh guhatloh These are slngle melme memorymodules SlMMs or dual melme memory modules DJMMs Smee DlMMs have a 64rbltpln eomeehohthey eah replace two 367 Mt 327blts plus 4 panty blts smMs when syhehhohous DRAMls useol Laptop and DLMMs Haw The Data In RAMIs Accessed Figure 2 RAM lmemlim Simmwelli mun th w tm M um controller The RAM controller organlzes the request and sends lt down the appropriate value eah be read In DRAM a capacltor Wth a charge over a certam voltage level 1 y Fordwwl R M r a Han F data called a page 15 read The data that 15 read 15 Lmnsmltted along the dala llrles to the r feveer cache r F ld V M RAM whlle data 15 belng wnden lo vldeo RAM bthe processor dala can A l Fort G Hm the dlsplay Image Cummnn Types uf RAM es 51 mmmmaemmm W a qul lt4 gt Figum 3 Cutan Types nfRAM slmmrelu mun y dl ym la VGA Main RAM Static RAM SRAM word row bit bit Figure 4 SRAM Cell Kubiatowicz 2001 Static random access memory uses multiple transistors typically four to six for each memory cell but doesn t have a capacitor in each cell It is used primarily for cache Static RAM is more expensive requires four times the amount of space for a given amount of data than dynamic RAM but unlike dynamic RAM does not need to be powerrefreshed and is therefore faster to access One source gives atypical access time as 25 nanoseconds in contrast to a typical access time of 60 nanoseconds for dynamic RAM AMT International 2001 More recent advances in dynamic RAM have improved access time Static RAM is used mainly for the level1 and level2 caches that the microprocessor looks in first before looking in dynamic RAM AMT Intemational 2001 Async Static RAM ASRAM Async SRAM has been with us since the days of the 386 and is still in place in the L2 cache of many PCs It s called asynchronous because it39s not in sync with the system clock and therefore the CPU must wait for data requested from the L2 cache However the wait isn39t as long as it is with DRAM AMT Intemational 2001 Burst 0r SynchBurst Static RAM BSRAM Burst SRAM also known as SynchBurst SRAM is synchronized with the system clock or in some cases the cache bus clock This allows it be more easily synchronized with any device that accesses it and reduces access waiting time It is used as the external level2 cache memory for the Pentium II microprocessor chipset AMT Intemational 2001 Async SRAM commonly used for L2 caches with speeds of about 85 ns Unfortunately Sync SRAM isn39t being produced in sufficient quantities to drive its cost down so it seems destined for a relatively short life That39s especially true because it loses the ability to synchronize at bus speeds higher than 66 MHz AMT International 2001 Pipeline Burst Static RAM PB SRAM Using burst technology SRAM requests can be pipelined or collected so that requests within the burst are executed on a nearly instantaneous basis PB SRAM uses pipelining and while it s slightly behind system synchronization speeds it s a possible improvement over Sync SRAM because it39s designed to work well with bus speeds of 75 MHz and higher X2Xtreme 2001 SRAM Comparison The following table shows the capabilities of various SRAM technologies at a number of external bus frequencies The numbers in the table indicate the typical memory access achieved in terms of the number of wait states for initial and subsequent accesses The shaded areas indicate the best performanceprice points for the various bus speeds and technology Note issue to keep in mind is that the most cost effective SRAM technology moves from asynchronous to owthrough synchronous to pipelined synchronous as bus frequencies increase However presently there are fewer suppliers with the underlying SRAM technology required for very fast owthrough synchronous SRAMs As a result in systems where performance is less critical designers are choosing pipelined synchronous for the 50 MHz to 66 MHz bus frequencies to increase the number of possible suppliers and hopefully product availability X2Xtreme 2001 Bus Speed MHz 33 50 60 66 75 83 100 125 211 322 322 322 322 322 322 322 Async SRAM 1 2 2 2 2 2 2 2 Sync Burst SRAM 211 211 211 211 322 322 322 322 1 1 1 1 2 2 2 2 Pipelined Burst 311 311 311 311 311 311 311 311 SRAM 1 1 1 1 1 1 1 1 Figure 5 SRAM Comparison x2xtreme 2001 Dynamic RAMDRAM I39OW RAM CIIKuhiquwicz2 l bit Figure Memory Address Bus W Figure 7 DRAM Amhitzclm muncdli 2m nw m r quota m mu m m R u r dw m M apower holds 5 comaquot in place DRAM must be refreshed about every 15 microseconds This 2001 Parity DRAM Normally you assume 8 bits to one byle in memory However for many years a math bit That W mm M hm ndlnalz bits to slore 32 bits in the larger72 plrl Chips Whlch increases the cost ofthe RAM chip a H V pamy modules Fortunately most systan boards accepted 32 bit modules so this was rarely a major concern AMT Intanatlonal 2001 Fast Page Made DRAM FPM DRAM Fast Page Mode amiss lt m CAC Figure 8 Pas Page Mm le Timing Graph Tang 1m LOW 11m mullalc caumscccsscs maybe exemtndbycydkg CA EachCAS cw nude zyplvmc a calm addxss bmwe ca Low wzml39lg fut vahd chum Lakhmg clau m 3911 system ml bnrorg CA llch a mac nk ml cyclz m dulde ms immune orcms is sllmumlu he llolclluch gmrg chll dusahlg k clau owlls ml ucrcarc mm occur yancnlu vahd cums hklrladbydrlzsystnm 77PM nxlbll 1 111a lepe lu Itwas usually mourned in 11le modules of 2 4 8 16 or 32MB Typically llls found in 60 u l u l l u 3 1 1c 1 11a cup 4 accesses based onLhe lruual selup Tang 1996 Enhanced DRAM EDRAM pairing nai is usually used for a leveer cache Typically 25o byies of siauc RAM is 35 nanoseconds By switching from FPMw EDo one can erpeci aperformance improvanent onLo 5 pemmt Tang 1996 ECC RAM ECC due to 5 h1g1 cost and lower performance Extended Data Output RAM in DRAM EDO RAM Dr EDO DRAM Figum y Exvendzrl Data 0mm RAM Timing Graph Tanng ind which micaca m u ironed 112me was r p r 17PM M F mm 1 rnenr r r r aparncular Tnd ad hi i u a memory cycle with improvemean In memory performance of as much as 40 pacent of 66 MHz and that quickly Being bypassed by the most recmt u op oEAMD Cyrrx and Lniei processors Burst Extended Data Output DRAM BEDO DRAM tCAC Burst EDD H m 2 aaaies Figum 1n BmlEDO Timing Graph Tangmts a iirmuasiaEnoim Mitsasiiisiiha uremia iiitids has have read assesses i5 hat shge is aimed aims iii ieiah 3911 aiawiiiaiiiamm i simian rained iaasi WAYS First the hisieiaiaseaiyiiegsaitie iii e tCAC is show msecmaimme is that because it tats iaaiaiimi 3911 riisica cycle Thebem tm39drns mamhiiaeiiie stag is that as we is m siniiiirisa mam eiaiesmmiiii imam mi 3911 swim iiievents is shmiiii the Fig to provide it W which sent and processed in the form of an uninteimpted burst of walla units What this page L L aiidiii iit Lum t m Together RFUO DRAM promised to offs 4717171 access times BEDO RAM can handle four dam elanmts in on huv c a and Lhen can process the rest at a rate of 10 us each BEDO RAM however despite its BEDO Com teeh RFUO 1996 petitwe With EDO RAM as aresuit more work was done With EDO to add bursting nologl i t Tan i T T eh h aii Tm iami rang Multilevel DRAM MLDRAlVI In MLDRAM data is stored in cells that contain multiple bits This is still an experimental architecture Currently several twobitpercell methods have been proposed The gure on the left shows one of these methods To extract the most signi cant bit MSB the cell voltage is compared to a reference voltage of 12VDD If the cell voltage is larger then the MSB is l and the cell voltage is then compared to a reference voltage of 56VDD to nd the least signi cant bit LSB Ifthe cell voltage is smaller than 12VDD the MSB is 0 and the cell voltage is compared to l6VDD to nd the LSB The difficulty of building this four level MLDRAM is the margins between each level is 13 of conventional DRAM The challenge with MLDRAM will be to make it reliable Birk 2001 Conventional Multilevel Rilnmmn Emil Retlfl u r L WillaJo Wilma Eungry visual 39u anmo 510m L l l L Eii3 l 1jjJ Figure 11 Multilevel DRAM Birk 2001 Synchronous DRAM SDRAM Synchronous dynamic random access memory takes advantage of the burst mode concept to greatly improve performance It does this by staying on the row containing the requested bit and moving rapidly through the columns reading each bit as it goes The idea is that most of the time the data needed by the CPU will be in sequence By keeping the RAM and the clock synchronized it increases the number of instructions that the processor can perform in a given time SDRAM is about ve percent faster than EDO RAM and is the most common form in desktops today Maximum transfer rate to L2 cache is approximately 528 megabytes per second Spock 2001 JEDEC SDRAM JEDEC Joint Electron Device Engineering Council SDRAM is an industry standard synchronous DRAM It has a dualbank architecture and several burst mode accesses that can be preset JEDEC SDRAM chips operate at either 83 MHZ or 100 MHz JEDEC SDRAM is also known as PC66 SDRAM because it was originally rated for 66 MHZ bus operation and to distinguish it from Intel39s PClOO architecture Kent 1998 Pcl SDRAM PC 199 SDRAM 15 SDRAM that states mam meets me PC 99 spe muun rum Intel Kama 1999 Intel Hated me wen muun m enable RAM manu dura s u make Ehps Lhatvmuld vmrk wnb Intel s HAUEX prunessur nhpsel ThexMEIEX was desigqed m aebeye a 199 MHz system bus speed Ida11yFCll SDRAM vmuldvmrk at me 199 MHz speed usmga 4717171 aeeess eyde ws repuned that PCIEIEI SDRAM lmpmves perfmmanceby 1971 5 m an Intel Sunkel 7 system bumu m aFenuum u bemuse 115 L2 eaebe speed ms at unly halfufpmcessur speed Kardu 1999 17cm SDRAM F0133 SDRAM has me me baae architecture as Lhch mu SDRAM wathe added abxhty m suppuna 133MHz bus speed Gary mm PCxxx Cnmparisnn Mu Mummy anA eu sue Hem n max Serb Cnnwuim0ry2 l Dnuhle Data Rave SDRAM DDR SDRAM me nsmg edge p manually duubhng uulpul ws expee1ed that a numba39 ur Sunkist 7 chpset makers will suppun Lhs rum ur SDRAM Kent 1998 Enhancad SDRAM ESDRAM Eubaneed SDRAM ESDRAM madeby Eubaneed Mammy Systems 15 a new JEDEC s39andard type ur DRAM whth altarnpls m lmpmve perfmmance nut by decreasmg latency u mtrasmg bus speed but by lmpmvmg me mma1 runeuun unbe RAM The gual ufESDRAM 15 m ubtam Qatar mruugqpu by remuvmg sume unbe mma1 delays unbe standard SDRAM arebueemre Ths 15 dune by addmg a mwregsler ache RRC which immediately absorbs the data from the Sense amps freeing them to refresh the DRAM cell in parallel with the data release to the cache lines as opposed to in serial as it is usually done FUNCTIUOML EILU EK DM RlHIfJMxW Elam ol Figure 13 Enhanced SDRAM Enhanced Memory Systems 2000 The RRC is really nothing more than an extra bank of SRAM which is used as a buffer to free up the sense amps so that the DRAM cell can be restored to its original state In addition a bit of primitive pipelining is used to increase throughput even further At the release of the third word a bank activate command can be issued and the next read command can occur during the release of the fourth word This translates into at most a onecycle delay when a page miss occurs Random accesses to other banks don t even have any delay What this means is that ESDRAM is able to utilize around 80 of the maximum theoretical bandwidth while standard SDRAM is around 4050 Enhanced Memory Systems 2000 ESDRAM is apparently competing with DDR SDRAM as a faster SDRAM chip for Socket 7 processors Tang 1996 Enhanced DDRRAM Enhanced DRRRAM or EDDR uses a concept similar to that of ESDRAM to improve latency and power consumption when compared to a standard DDRRAM module EDDR takes the approach of replacing the secondary sense amps used to transmit data to global output lines with a small SRAM cache Enhanced Memory Systems 2000 DDR EDDR 1 row 39 1 3 dala lines Che Jepoaap uu1noo rrm won mm Figure 14 Enhanced DDRRAM LostCircuits 2000 When a row page is opened the entire contents of the row are sent by the primary sense amps to the SRAM cache Then when a read command is serviced the column decoder accesses the SRAM instead of activating the required column and waiting for the secondary sense amps to place the data on the global output lines LostCircuits 2000This approach eliminates one set of trace lines into the DRAM cells by attaching the column decoder to the SRAM cache instead This lack of a 2 way trace delay will shave about 2ns off the CAS delay By decreasing the latency of the read process EDDR decreases the time wasted on page misses by about 33 Davis 2000 Rambus Dynamic Random Access Memory RDRAM DRDRAM Figure 15 RDRAM Simoncelli 2000 Rambus dynamic random access memory is a radical departure from the previous DRAM architecture Designed by Rambus in partnership with Intel RDRAM uses a Rambus in line memory module RIMM which is similar in size and pin con guration to a standard DIMM Rambus 2001 What makes RDRAM so different is its use of a special high speed data bus called the Rambus channel Direct Rambus DRDRAM provides a two byte 16bit bus rather than DRAM s 8bit bus or SDRAM s 64bit bus At a RAM speed of 800 megahertz 800 million cycles per second the peak data transfer rate is 16 billion bytes per second Direct Rambus uses pipelining to move data from RAM to cache memory levels that are closer to the microprocessor or display Up to eight operations may be underway at the same time Rambus is designed to fit into existing motherboard standards Kardo 1999 SyncLink DRAM SLDRAM A new standard for SDRAM is being developed by the SCIzzL Association at Santa Clara University California along with many industry leaders Randall 1997 Called SLDRAM this technology improves on SDRAM by offering a higher bus speed and by using packets small packs of data to take care of address requests timing and commands to the DRAM The result is less reliance on improvements in DRAM chip design and ideally a lowercost solution for highperformance memory Randall 1997 SyncLink DRAM is along with Direct Rambus DRAM DRDRAM a protocolbased approach In this approach all signals to RAM are on the same line rather than having separate CAS RAS address and data lines Since access time does not depend on synchronizing operations on multiple lines SLDRAM promises RAM speed of up to 800 MHz Like Double Data Rate SDRAM SLDRAM can operate at twice the system clock rate SyncLink is an open industry standard that is expected to compete and perhaps prevail over Direct Rambus DRAM Virtual Channel RAM Most all modern operating systems are capable of running multiple tasks or threads at one time When running multiple threads at once each thread is a memory master meaning it has its own address locality and tends to access memory in a fairly contiguous manner However since many threads are running at once the RAM bank ends up opening and closing pages frequently even though the same basic address spaces are being accessed This is known as thrashing Virtual Channel Memory architecture however is designed for multithreading VCRAM provides each thread with its own Virtual Channel basically a dedicated port to RAM which allows each thread to access its own virtual memory space as if it were the only thread accessing the RAM bank with up to 16 channels available NEC 1998 vcm mm mum wmmmcmuwmuwx Th Vmul chahh1s mmnm u Jammyan rmm mth thread asssss aha mum amamah dam sluan wnhmn ham external memmymamgemzm Each shahh1 1s qmppa wnh a data mwbn ex aha us awn mdzpndzm apn ng msz Th 5 Ea g5 E 3 3 5 E i i E E Cumsi mum cmmvx Th comm mhnzchlre mumpumzsanSRAMcach wnh DRAM Th separate mnmmls anh m RAM iyps anhw mdzpndzm camml arah Ths iyp afDRAM has been gm m graphms apphsamhs aha PDAs h aJsa sahh used as sah aha mam mzmnxy Knmamgn 1995 Vilm mm 15 RAM as Mdza RAMquot means In hha1 an rams afRAM used m shire hag prfannmce as a result Eycampnnsan SRAM have unlme assss pm hi RAM 1s nauya bn exbethen u pmcessax aha u msplaymm ax aha 1s amh called the frame buffer When images are to be sent to the display they are first read by the processor as data from some form of main storage RAM and then written to video RAM From video RAM the frame buffer the data is converted by a RAM digitalto analog converter RAMDAC into analog signals that are sent to the display presentation mechanism such as a cathode ray tube CRT Usually video RAM comes in a l or 2 megabyte package and is located on the video or graphics card in the computer Randall 1997 RAMDAC RAMDAC random access memory digitaltoanalog converter is a microchip that converts digital image data into the analog data needed by a computer display A RAMDAC microchip is built into the video adapter in a computer It combines a small static RAM SRAM containing a color table with three digitaltoanalog converters DACS that change digital image data into analog signals that are sent to the display s color generators one for each primary color red green and blue Randall 1997 In a cathode ray tube CRT display an analog signal is sent to each of three electron guns With displays using other technologies the signals are sent to a corresponding mechanism The SRAM part of the RAMDAC contains a color palette table A logical color number in the digital data input to SRAM is used to generate three separate values obtained from the table one for each of red green and blue that are output to one of three digitalto analog converters The analog signal output from the converter is input directly to the display electron guns or other image projecting mechanisms For displays with true color the digital color data is fed directly to the DACs bypassing the SRAM table which is not needed Randall 1997 Multiport Dynamic Random access memory MPDRAM MPDRAM multiport dynamic random access memory MPDRAM is another subset of Video RAM This type of RAM used speci cally for video adapters or 3D accelerators The quotmultiportquot part comes from the fact that MPDRAM normally has both random access memory and serial access memory MPDRAM is located on the graphics card and comes in a variety of formats many of which are proprietary The amount of MPDRAM is a determining factor in the resolution and color depth of the display MPDRAM is also used to hold graphicsspecific information such as 3D geometry data and texture maps Randall 1997 Window RAM Window RAM WRAM unrelated to Microsoft Windows is very highperformance video RAM that is dual ported and has about 25 more bandwidth than VRAM in addition to several graphics features that applications developers can exploit but costs less Like VRAM WRAM is a dualported type of RAM and it is used exclusively for graphics performance Additional graphics features include a doublebuffering data system several times faster than VRAM39s buffer resulting in considerably faster screen refresh rates It is often used for very high resolution such as 1600 by 1200 pixels projection using true color Randall 1997 Synchronous Graphics RAM Unlike VRAM and WRAM and despite the fact that its primary use is on video accelerator cards SGRAM is a singleported RAM type It speeds performance through a dualbank feature in which two memory pages can be opened simultaneously it therefore approximates dualporting SGRAM is proving to be a significant player in 3D video technology because of a blockwrite feature that speeds up screen fills and allows fast memory clearing AMT Intemational 2001 Threedimensional video requires extremely fast clearing in the range of 30 to 40 times per second Other features of this type of RAM include 1 l 39 39 ion and a 39 39 1 called masked write which enables selected data to be modified in a single operation rather as a sequence of read update and write operations AMT International 2001 3D RAM 3DRAM is a memory chip that is optimized for high performance graphics systems It stores 3 dimensional data and uses Zcompare and alpha blend units The bandwidth for these chips are as high as 400 Mbytess externally and 16 Gbytess internally This type of RAM is not as effective for nongraphics intensive systems Kumanoya 1995 Multibank Dynamic RAM Multibank Dynamic RAM MDRAM is a highperformance RAM developed by MoSys which divides memory into multiple 32 KB parts or quotbanksquot that can be accessed individually Tyson 2000 Traditional video RAM is monolithic the entire frame buffer is accessed at one time Having individual memory banks allows accesses to be interleaved concurrently increasing overall performance It s also cheaper since unlike other forms of video RAM cards can be manufactured with just the right amount of RAM for a given resolution capability instead of requiring it to be in multiples of megabytes Tyson 2000 Nonvolatile RAM NVRAM Nonvolatile RAM NVRAM is a special kind of RAM that retains data when the computer is turned off or there is a power failure Similar to the computer39s readonly memory ROM NCRAM is powered by a battery within the computer It can also work by writing its contents to and restoring them from an EEPROM Ferroelectric Random Access Memory A type of nonvolatile readwrite random accesses semiconductor memory FRAM combines the advantages of SRAM writing is roughly as fast as reading and EPROM nonvolatility and incircuit programmability Tyson 2000 Current disadvantages are high cost and low density but that may change in the future A ferroelectric memory cell consists of a ferroelectric capacitor and a metal oxide semiconductor MOS transistor Its construction is similar to the storage cell of a DRAM The difference is in the dielectric properties of the material between the capacitor s electrodes This material has a high dielectric constant and can be polarized by an electric field The polarization remains until an opposite electrical field reverses it This makes the memory nonvolatile FRAM has similar applications to EEPROM but can be written much faster The simplicity of the memory cell promises highdensity devices which can compete with DRAM How RAM Effectiveness is measured The amount of time that RAM takes to write data or to read it once the request has been received from the processor is called the access time Typical access times vary from 9 J to 70 J J r J39 on the kind of RAM Although fewer nanoseconds access is better userperceived performance is based on coordinating access times with the computer39s clock cycles Access time consists of latency and transfer time Latency is the time to coordinate signal timing and refresh data after reading it Peak Bandwidth Here you see the maximal peak bandwidth of the three wellknown RAM types The figure illustrates the absolutely maximal transfer from RAM to the L2cache in peaks not as continuously transferred RA Mntypei Max Peakbandvvidth EDQ 254 MET90 so 528MBsec 39 Figure 17 Peak Bandwidth Kardo 1999 DDR RAM RAM type Bandwidth SDRAM 100 MHZ 100 MHZ X 64 bit 800 MBsec SDRAM 133 MHZ 133 MHZ X 64 bit 1064 MBsec DDRAM 100 MHZ 2 X 100 MHZ X 64 bit1600 MBsec DDRAM133 MHZ 2 X 133 MHZ X 64 bit 2128 MBsec RDRAM 800 MHZ 800 MHZ X 16 bit 1600 MBsec Figure 18 Peak Bandwidth of DDR RAM Types Kardo 1999 The RAM Table A lication and Access RAM Technology Cpp Speed Ports Characteristics omputer Location Range LeveH and levela RAM that is continually Static RAM charged SRAM caChe memor FaSt one More expensive than Also used in RAMDAC DRAM Burst SRAM Level2 cache memo Fast One SRAM 1n burst mode BSRAM ry DRAM Lowcost video Slow One y constantly recharged memory RAM FPM Fast Page Main memory Prior to EDO DRAM the M d DRAM Lowcost Video Slow One most common type of 0 e memory DRAM Uses overlapping reads Mainmemo 520 one can be in While EDO EXtended Low cost vidio faSter than One another is fiishi Data Out DRAM 39 FPM g memory DRAM Currently the most common type of DRAM Faster than BEDO Burst Main memo and low EDO Not Widely used because Extended Data cost Video ry DRAM One not supported by processor Out DRAM 4111 at chipset makers 66 MHZ 15 ns EDRAM 2mm Contains a 256byte Enhanced Level2 cache memory 35 ns One SRAM inside a larger DRAM DRAM access to DRAM Preset phone nmnbers Fast One Batterypowered RAM N onvolatile RAM NVRAM and profiles in modems specific forms of Synchronous SDRAM Generic term for DRAMs F I Main memory Rated in One with a synchronous D SD MHZ interface rather than nanosecon ds J EDEC Dualbank architecture Synchronous Burst mo e DRAM J EDEC Mam memory FaSt one Most common form of SDRAM SDRAM Intended to Eggi onous run at 100 An Intel specification DRAM PC 100 Main memory MHZ With One designed to work With SDRAM 4lll their i44OBX timing Double Data Rate Activates output on both the up and the down part Synchronous Up to 200 Main memory One of the clock cycle DRAM DDR MHZ DRAM doubling the data rate of PC100 SDRAM Enhanced Twice as fast as SDRAM Synchronous Fast 100 Main memory Two See Enhanced Memory DR M MHZ H s stems EMS ESDRAM y Open protocolbased R I I Fastest design SS3ng Mainmemory 200 MHZ One Uses quotpacketsquot for address data and control signals Up to 800 Direct Rambus MHZ but DRAM Main memory with a 16 One Eg ffst gmel and DRDRAM bit bus 39 width Uses a small SRAM to store the color palette table RAMDAC Video card Fast One used to provide data for digitaltoanalog c onv ersion Rambus DRAM Video memory for Up to 600 One Intel and Rambus Inc RDRAlVI Nintendo MHZ architecture Synchronous Closer to Has special performance Gmphics RAM Moderate to highend One enhancing features SGRAM v1deo memory than Example Matrox DRAM Mystique Dualported meaning a VRAM d Highercost video Twice the new image can be stored RAM V1 e0 memor speed of Two in RAM while a previous y DRAM image is being sent to the display 25 faster With RAMDAC can m wmdow geesrigfpenslve Vldeo than Two handle true color at 1600 y VRAM by 1200 pixel resolution Interleaved memory accesses between banks Memory has multiple 32 kilobyte banks that can be Multibank DRAM fg gsetr gh nd Faster One accessed independently MDRAM a heationsry Can be manufactured to fit pp the amount of memory the card requires No sizerelated performance penalty Enhanced Twice as fast as SDRAM Synchronous Fast 100 Main memory Two See Enhanced Memory DRAM MHZ S Stems EMS ESDRAM y Fastest Enhanced DDR Mainmemory 200266 One Uses faSt S caChe m MHZ place of Sense Amps Optimized for multi Virtual Channel Main memo 100 l 33 One threaded operation with up RAM ry MHZ to 16 independent channels one per thread Figure 19 RAM comparison table Giakamozis 1999 GLOSSARY Simoncelli 2000 ACCESS TIME 7 The access time is the delay between the time the memory device receives an address and the time when the data from that address is available at the output of the memory This is sometimes also referred to as the read time The access time is usually constant for a particular random access memory RAM device and may be regarded as a specification of the speed of the RAM device For memory other than RAM the access time is often regarded as the time from when an instruction is decoded asking for a memory location until the desired information is found but not read In this case the access time is a function of the location of the data on the medium with reference to the position of the read write transducers It can therefore vary substantially depending on the location of the information being sought and as a consequence the average access time over a short period depends on the pattern of memory references BANDWIDTH Memory bandwidth is the number of bytes per second that the memory can deliver to the processor The bandwidth of a memory is also the amount of information made available to the processor by a single memory access CAPACITY The capacity of a memory module or system is simply the maximum number of bits bytes or words within the module or system Example a 2K x 4 memory can store 2K K 1024 21 words each containing 4 bits ofdata or a total of2 x 1024 x 4 bits 8192 bits CYCLE TIME In general the cycle time is the time interval for which a set of operations is repeated regularly in the same sequence In the area of computers the cycle time is the total time for a program instruction to reference a memory location cad from or write to it and then return to the next instruction The cycle time is also used as a measure of how often a memory can be accessed per unit time For a static random access semiconductor memory SRAM the cycle time is equal to the access time however for a dynamic random access memory DRAM the cycle time is greater than the access time since a DRAM requires a frequent restore period In this latter case the cycle time then consists of the access time plus any additional time after the completion of a memory access until the memory is available again It can be noted that the cycle time for a magnetic disk drive to deliver the contents of its disk is much greater than that of silicon random access memory DATA RATE The data rate is the rate usually bits per second bytes per second or words per second at which data can be read out of a storage device It can be calculated by determining the product of the reciprocal of the access time and the number of bits in the unit of data data word being read The term data rate is usually associated with nonrandom access memory where large pieces of information are stored and read serially and has little significance in random access memory since in such memories an entire word is normally read out in parallel In most cases the data rate is constant for a given memory module DENSITY In the area of magnetic storage density is the number of characters or bits that can be stored on either one inch of magnetic tape or per track on a magnetic disk ERASABLE STORAGE The term erasable storage is given to any memory device whose contents can be modified e g random access memory RAM This is in contrast to read only storage ROM Bibliography AMT International January 2001 Your Complete Memory and Hardware Store lthttpwwwamtiinccomgt Birk G D G Elliot and B F Cockbum 1999 A comparative simulation study of four multilevel DRAMs lthttpwwweeualbertacaNelliottmemory conferences1999mtdt7birk7mldrampdfgt Retrieved 20 January 2001 Davis Brian et al June 2000 DDR2 and low latency variants lthttpwwweecsumichedubtdavispapersgt Enhanced Memory Systems November 2000 ESDRAM Datasheet lthttpwww edram com Li39urar y 39 39 SM2603 2604pb r18pdfgt Gary January 2001 RAM Roundup Overclockin lthttpwwwov 39 39 in Vi w J J 3htmlgt Geer Will July 2000 Memory Guide lthttpwww Qdmoe ygt Giakamozis Con July 1999 A RAM Guide lthttplt ie 39 ackr m39 39 39 391 htmgt Kardo Michael July 1999 About RAM lthttpwwwmkdatadldclicldmodule2ehtmgt Kent Dean October 1998 RAM Guide Tom 3 Hardware lthttDIWWW 39 39 n um I 39 J 8q4981024indeY html Kubiatowicz John Spring 2001 Lecture Notes Copyright 2001 UCR lthttpwwwinsteecsberkeleyeducs152gt Kumanoya M T Ogawa and K Inoue 1995 Advances in DRAM interfaces IEEE Micro 156 3036 LostCircuits November 2000 Inside the EDDR Chip LostCircuits lthttpwww 39 39 quot v gt NEC Electronics Inc 1998 Virtual Channel Memory Product Brief lthttpwww necel 39 nsf Vie 39 M13154EU2VOPB00 le1 3154e20pdfgt N R April 1998 Everything you wanted to know about random access memory lthttp www cyberwalker netcolumnsapr9 80423 htmlgt Rambus INC Janurary 2001 Rambus Home Page lthttpwwwrambuscomgt Randall Neil 102197 A RAM Primer PC Magazine lthttpwww dnet pcmagpctechcontent1618tu1618 001 htmlgt Risley David January 2001 RAM Primer Hardware Central I lthttpwww 39 39 tut ials523gt Risley David January 2001 Video Memory Hardware Central httn39 39 39 39 39 J 39 tut rials682gt Simoncelli Federico July 2000 Types of RAM lthttpwwwscitwlvaculdc992l l90types of ramhtmgt Spock January 2001 RAM Information lthttpWww shock mem html Tang Stanley October 1996 Computer Info lthttpwww core 39 39 39 edn crsovrwebdoc9htmgt Tyson Jeff July 2000 How Random Access Memory RAM Works lthttp WWW howstuffworks com ram3 htmgt X2Xtreme January 2001 RAM Random Access Memory lthttpX2Xtremehomeipnetramhtmgt
Are you sure you want to buy this material for
You're already Subscribed!
Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'