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by: Demetris Rempel

MSEEProjectProposal EE297A

Demetris Rempel
GPA 3.88


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Class Notes
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This 11 page Class Notes was uploaded by Demetris Rempel on Tuesday October 20, 2015. The Class Notes belongs to EE297A at San Jose State University taught by TriCaohuu in Fall. Since its upload, it has received 33 views. For similar materials see /class/225335/ee297a-san-jose-state-university in Electrical Engineering at San Jose State University.


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Date Created: 10/20/15
Schedule of work Date Participant amp 3282011 33 02011 Mohmadshahid amp Sriram amp to extract Mohmadshahid 11 11 amp 10 days scenarios 9262011 1072011 Mohmadshahid amp Sriram amp OLAES AES Core family Rev 15 General Description Applications Features Symbol This core family implements various aspects of the AES Advanced Encryption Standard algorithm Simple fully synchronous design with low gate count Electronic financial transactions Secure communications Secure video surveillance systems Encrypted data storage 999 Implemented according to the FIPS 197 documentation Also available in CBC CFB and OFB modes Key size of 128 192 and 256 bits Both encryption and decryption supported Fully synchronous design Available as fully functional and synthesizable VHDL or Verilog soft core Test benches provided Xilinx and Altera netlists available 99999 99 Data Input AES gt Data Output Key gt Core Input Control Ocean Logic Pty Ltd OLAES AES Cryptoprocessor family General Description The OLAES core family is a hardware implementation of various aspects of the AES algorithm as described in NIST s released documentation suitable for a variety of applications The AES algorithm was selected by NIST on October 20 2000 amongst a group of competing algorithms The algorithm chosen by NIST Rijndael offers strong and secure encryption with the added flexibility of variable key block sizes Compared to the DES and the triple DES algorithms AES provides an even higher level of security An AES encryption operation consists in the transformation of a 128 bits block into a block of the same size The encryption key can be chosen among three different sizes 128 192 or 256 bit The key is expanded during cryptographic operations A block diagram of the AES core is shown below Key Expander AddRoundKey State Storage ByteSub Shi Row Are a Figure 1 AES core block diagram The AES algorithm consists of a series of steps repeated a number of times rounds The number of rounds depends on the size of the key and the data block The intermediate cipher result is known as state KSIZE00 KSIZE01 KSIZE 10 I Rounds I 10 I I I Table 1 Number of rounds as a function of key size Initially incoming data and key are added together in the AddRoundKey module The result is stored in the State Storage area The state information is then retrieved and the ByteSub Shiltrow MixCqumn and AddRoundKey are performed on it in the specified order At the end of each round the new state is stored in the State Storage area These operations are repeated according to the number of rounds The final round is anomalous as the MixCqumn step is skipped Alter the final round the cipher is output Ocean Logic Pty Ltd 2 OLAES AES Cryptoprocessor family Available Options This section summarizes many of the options available when selecting a particular AES core Encryption and Decryption Encryption and decryption in AES are reasonably different procedures Consequently their hardware implementation can be quite different Ocean Logic AES cores that support both encryption and decryption are highly optimized and share a lot of common hardware between the two functions However a core that supports both modes will be generally larger and slower than a core that supports encryption only Key Expansion The AES algorithm requires for the key used for encryption or decryption to be expanded Ocean Logic can provide an AES key expander together with an AES core During decryption the expanded key must be fed to the core backwards A key expander core that can expand the key both forward and backwards is also available Core Throughput The throughput of an Ocean Logic AES core is influenced by the width of the datapath as well as the clock frequency Clock frequencies can be expected to range from over 250 MHZ in 018 micron ASIC to over 100 MHZ in Xilinx FPGA The datapath width can be 32 or 128 bits Fully pipelined designs are also available for a throughput of over 25 Gbps Core Performance The table below provides an indication of the trade off between performance and area that can be expected for some of the options discussed in this section N Table 2 AES core family area performance trade off The following sections show an example of two particular cores available OLAESED and OLKEXPED OLAESED is an encryptiondecryption AES core with no key expander OLKEXPED is an AES key expander core Both cores are illustrated in the 32 bit datapath version AES Encryption Decryption core without Key Expander The OLAESED core supports both encryption and decryption according to the AES algorithm The key must be provided to the core already expanded During decryption this core follows the Ocean Logic Pty Ltd 3 OLAES AES Cryptoprocessor family Equivalent Inverse Cipher algorithm as outlined in the AES documentation Consequently encryption and decryption pre expanded keys are not equivalent Ocean Logic can provide an additional module so that encryption and decryption pre expanded keys are the same The symbol of the core is shown below gt DIN310 DINiREQ gt gt KEY310 gt KSIZE10 AES DOUT310 gt DOUT VLD gt gt RSTN gt CLK Figure 2 OLAESED symbol Pin Description Functional description Rising the input on the GO port triggers the beginning of a cryptographic operation on the data DIN using the KEY as key The key size selection can be performed on the core by the KSIZE input Valid values for KSIZE are 00 01 and 10 selecting 128 192 or 256 bits respectively The KSIZE inputs must not be changed while the data is processed The core then raises the DINREQ signal requesting the data block It then starts to process the state according to the AES algorithm The timing diagram below shows how the data is fed to the core at the start Ocean Logic Pty Ltd 4 OLAES AES Cryptoprocessor family KSIZEU 0 KEY31 0 DINiREQ DIN31 0 Figure 3 Key and data input at the start of encryption The KSIZE parameter is passed to the core alter the GO signal is raised Input of the KEY data continues for all the duration of the cryptographic operation Both data and key are input serially 32 bits at the time The diagram above shows the case where the input data is 128 bits The ordering of the data is shown in the figure below 31 23 15 7 0 D0 D1 D2 D u Word 0 D4 D5 D6 D7 Word 1 D 4n2 D 4n3 Word N D 4n l D 4n1 Figure 4 AES core data ordering When all the rounds are completed the DOUTVLD signal is raised and the encrypted data starts to flow out This is shown in the timing diagram below Ocean Logic Pty Ltd OLAES AES Cryptoprocessor family CLK EiD KIN31 0 DINiREQ DIN31 0 DINO DINl DIN2 DOUT 31 0 DOUT7VLD Figure 5 Cipher text from a previous operation is being output while new plaintext is input It is possible to start a new cryptographic operation as soon as the data from the previous one is output The core can also switch between encryption and decryption with no gaps The absence of gaps allows sustaining the throughput listed in the table below KSIZE 00 KSIZE 01 KSIZE 10 I Cycles 4 I I Table 3 Number of cycles as a function of key size It is possible to order an OLAESED core that supports a slightly higher throughput same as in Error Reference source not found but with different IOs A cryptographic operation can be aborted at any time by lowering the GO signal for at least one clock cycle Two other versions of this core exist OLAESE and OLAESD OLAESE supports encryption only while OLAESD supports decryption only Both cores are slightly smaller and faster than OLAESED AES Key Expander The OLKEXPED core is a highly integrated implementation of the AES key expansion The input key is expanded and it can be used during encryption on the fly without the need to store the whole key in a buffer During decryption the core can expand the same key backwards The symbol of the core is shown below Ocean Logic Pty Ltd 6 OLAES AES Cryptoprocessor family gt KIN310 ADDR50 gt gt KSIZE10 KEXP gt EiD GO KEYiLAST gt EN KEY310 gt gt RSTN gt CLK Figure 6 OLKEXPED symbol Pin Description Functional description Rising the input on the GO port triggers the beginning of the expansion of the KEY input The key size selection can be performed on the core by the KSIZE input Valid values for KSIZE are 00 01 and 10 selecting 128 192 or 256 bits respectively The KSIZE inputs must not be changed while the data is processed The core then raises the KEYREQ signal requesting the key It then starts to expand the key according to the AES algorithm The timing diagram below shows how the data is fed to the core at the start in the case of a 128 bit key Ocean Logic Pty Ltd 7 OLAES AES Cryptoprocessor family b CLK GO KSIZE10 KEYiREQ KINI3101 K2 K3 WW KEY310 Y2 KEY3 KEY4 KEY6 Valid I Figure 7 Key input at the start of expansion During the expansion process the expanded key data is available at the output KEY At the end of the expansion operation the signal KEYLAST is raised The core is immediately ready for another expansion operation and in fact the KEYREQ signal is raised immediately er The diagram below illustrates this CLK KEYiREQ K1N3101 KEY310 KEYl KEY KEYiLAST J Figure 8 Last expanded key data and start of new expansion Edwa Any expansion operation can be aborted at any time by lowering the GO signal Also the core can be stalled at any time by lowering the synchronous enable signal EN Table 3 shows the number of cycles required for a key expansion operation as a function of key size Ocean Logic Pty Ltd 8 OLAES AES Cryptoprocessor family OLKEXPED and OLAESED Performance Performance figures of the cores in ECB mode implemented with some particular technologies are shown in the table below Table 4 Performance of the OLKEXPED core Table 5 Performance of the OLAESED core As signi cantly faster but slightly larger version of OLAESED is also available Available Versions All the Ocean Logic AES cores are available in ECB CFB CBC and OFB mode with or without key schedulerexpander A key expander is available as stand alone core Customizations are welcome Export Permits The core is available for export to all the countries of the world with the exception of the followmg Iran North Korea Libya Cuba Sudan Syria Iraq It is the customer s responsibility to check with relevant authorities regarding the re export of equipment containing this technology Deliverables Netlist available for most Xilinx and Altera devices Synthesizable VHDL or Verilog RTL Complete HDL testbench Ocean Logic Pty Ltd 9 OLAES AES Cryptoprocessor family Ocean Logic Pty Ltd PO BOX 768 Manly NSW 1655 Australia Tel 61299054152 Fax 61299050921 EMail info 0cean 10giccom URL htggWwwoceanlogiccom Ocean Logic Pty Ltd 10


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