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by: Demetris Rempel

HighSpeedCMOSCircuits EE224

Demetris Rempel
GPA 3.88


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About this Document

Class Notes
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This 24 page Class Notes was uploaded by Demetris Rempel on Tuesday October 20, 2015. The Class Notes belongs to EE224 at San Jose State University taught by MorrisJones in Fall. Since its upload, it has received 61 views. For similar materials see /class/225339/ee224-san-jose-state-university in Electrical Engineering at San Jose State University.


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Date Created: 10/20/15
EE 224 Digital Circuit Design A first Look at CMOS CMOS CMOS has both a N and a P transistor Controlled Pullup Controlled Pulldown The P transistors are slower k is slower by 25 to 3 X Loop Us for N transistors Build True Loop 1 s for P transistors Build Comp BB 224 notes 2 Morris Jones CMOS Likes NAND Since P s are slower Placed in Parallel Makes NAND gates VOH N s Off P s Saturated VDD VOL P s Off N s Saturated 0V BB 224 notes Morris Jones Typical CMOS Inverter V00 7 A 7 OUT 7 A 7 GND BB 224 notes Morris Jones Transistor States Critical Point N P VOH Cutoff Linear VIL Saturation Linear Saturation Saturation VIH Linear Saturation VOL Linear Cutoff BB 224 notes Morris Jones vL k 2 IDNSAT 7N VIL VTN VD VOUT 2 1DPLIN kP VDD VIL VTP VD VOUT f dIDNUIL dIDP VILa VOUT I I I deIL 22dVIL aidI0UT dVIL IL OUT BB 224 notes Morris Jones More Vquot dIDN 6le dVOUT dVIL aVIL 1 dVIL 61 aVOUT aDP dIDN aIDP aIOUT dIL a 1L kP VDD VJL VTPVD VOUT kNV1L ITNkPVD VOUT k 2VOUT VDD VTP k7NVTN V P L k Hi kP BB 224 notes Morris Jones vH k IDPSAT 7VDD VIH VTP 2 V 2 IDNLIN kN VTN VOUT dIDP VIH dIDN VIH a VOUT d a a ion1H all1H idVOUT dVIH 1H OUT 8 Morris Jones More Vquotl 61m dIDP dVOUT dVIH aVIH 1 dVIN aIDN 6V0 dIDP 6IDN 61m dVIH aVIH aVOUT kP VDD VIH VTP kNVOUT kN VTN VOUT k V V i V 2V DD TP kp TN OUT OO Great What is 1kiN kP VIH BB 224 notes Morris Jones Finding VOUT for VIH V2 k 1DNLIN kN VTN VOUT IDPSAT 713VDD VIH VTP 2 V2 k kN VIN VOUT 02W 2 71301313 VIH VTP 2 You Can plug in VIH from the previous page and solve using the quadric equation Very Ugly or solve with guesses and plug the improvements into both equations until they converge BB 224 notes 10 Morris Jones Midpoint Voltage V l k k IDNSAT 7N VM VTN 2 IDPSAT 7P VDD VM VTP 2 k VDD VTP VTN k N P VM 1 k N kP BB 224 notes Morris Jones When V l is VDDI2 I Sxmmetricl k VDD VTP VTN k N P VM VDD 2 1 kN k IAssume VTP VTN P V V k k N ZVDD VT VT N 2 2 kp kP kN BB 224 notes 42 Morris Jones Symmetric Conditions BB 224 notes Morris Jones CMOS Design Most CMOS is designed for Symmetric operation VIH and VIL are secondary Are normally OK if VMVDD2 In the Symmetric condition The Value of VDD does not matter VM is always VDD2 Voltage independence BB 224 notes 14 Morris Jones Static Current in CMOS Inverter 6 Conditions VN lt VTN 0 ma VIN gt VTN and VDS lt VIN VTN Saturated Region VDDVIN gt 39VTP and VDSP gt VIN VTP VDDVIN lt 39VTP and VDSP lt VIN VTP BB 224 t no es 45 Morris Jones Spice Current Plot 12m MbreaKP DA UV 1 IVDDJ BB 224 notes Morris Jones VV39i n 16 312 VOU39E 132 Current Symmetric case peaks at VM Both N and P turned on the Hardest Neither one is limiting current Both Matched In other cases either the N or the P is limiting the current to less than the other can supply BB 224 notes 17 Morris Jones CMOS Power No Static Current Static Power 0 Dynamic Power Area Under Current Curve over Time Amount of time input is gtVTN and ltVDDVTP Edge Rate Sensitive Need to add C dVdT current also BB 224 notes 18 Morris Jones CMOS Fall Time This is a long Derivation It is in DIC If you need help see me At N ZCL VIN V1 VDD CL 111 2VDD ZVZN V2 kN VD VIN 2 kN VD VIN V2 V1 is the starting voltage point Normally 9 VDD V2 is the ending voltage point Normally l VDD Notice the gates get faster as kN gets larger WNLN is larger But this also raises CL Best solution is to get larger uN for larger k N BB 224 notes 19 Morris Jones CMOS Rise Time This is a long Derivation It is in DIC If you need help see me N z 2CL VTP V3 CL 2 n VDD2VTPV4 kP VDD VTP kP VDD VTP VD V4 V3 is the starting voltage point Normally l VDD V4 is the ending voltage point Normally 9 VDD Notice the gates get faster as kP gets larger WPLP is larger But this also raises CL Best solution is to get larger uP for larger k P BB 224 notes 20 Morris Jones Example Find Fall Time with k n31 and k p13 WLN132 WLP312 CL1pf V1 95V45V V2 15V5V At 21pf1V 45V 5V 1 pf In 25 21 5 2015u5V 1V2 2015u5V 1V 5 367ps BB 224 notes 21 Morris Jones Spice Results III III L011 E vmauca Vtii in BB 224 notes 22 Morris Jones Noise Margins Amount of Noise the input can tolerate before the output will change Normally VOL to VIL and VOH to VIH VM quotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquot 39 39 VIL AM In BB 224 notes Morris Jones What if VIH and Vquot Could Cross Low to High High To Low BB 224 notes Morris Jones


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