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# FundamentalsComp Design ECE 4120

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This 33 page Class Notes was uploaded by Miss Alysha Stroman on Wednesday October 21, 2015. The Class Notes belongs to ECE 4120 at Tennessee Tech University taught by Roger Haggard in Fall. Since its upload, it has received 44 views. For similar materials see /class/225742/ece-4120-tennessee-tech-university in ELECTRICAL AND COMPUTER ENGINEERING at Tennessee Tech University.

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Date Created: 10/21/15

FloatingPoint Computer Arithmetic ECE 4120 Fundamentals of Computer Design Dr Roger L Haggard Associate Professor Department of Electrical and Computer Engineering Tennessee Technological University Spring 2004 RLH Spring 2004 ECE 4120 FloPt 1 Floating Point Numbers Systems Introduction 0 Can represent both integers and fractions With much Wider range of values 0 N bits still represent up to 2N values but interpret differently 0 Scienti c notation in base 10 FPNS 234 1012 234 E12 234 10 12 Mantissa Base Exponent sign 10 sign mag 234 mag 12 gt radix 10 gt radix 10 usually assumed not written with number can be assumed Every number M contain mantissa sign mag 234 exponent sign mag 12 RLH Spring 2004 ECE 4120 FloPt 2 FPNS Basics 1 o For Computer gt Binary values most ef cient VFPN Mantissa BaseExponent usually SM usually excess code VFPN 1SIGN gtllt VM gtllt rbVE value 0 baJe ofme of exponent in base rb in base re m digits e digits lt lt lt lt VMMIN VM VMMAX VMMIN VE VEMAX RLH Spring 2004 ECE 4120 FloPt 3 FPNS Basics 2 o Mantissa is xed point gt assume value of p Normalization convert number so that the msd 7t 0 giving maximum pre01s1on for the number Usually p m so mantissa is a pure fraction VMMIN 01000 l rb 139 I39b39m 0 Number of legal mantissas NLM rb l rbm391 possible lst othei digits 0 Number of legal exponents NLE ree codedependent 0 Number of representable values NRV NLM NLE 2 signed 0 Min FP value VMIN VMMIN rbVEaMIN 0 Max FP value VMAX VMMAX rbVEJVIAX RLH Spring 2004 ECE 4120 FloPt 4 7Blt Example 1 O FPNSwith rb2 r2 m4 e2 pm4 SM unsigned normalized msd 1 so value sign 0mmmm 2ee VMMINO10002 12 NLM8 VMMAXO11112 1516 NRV 84264 VEMIN 002 0 NLE4 VEMAX112 3 VMAX 111122112 15168 712 VMIN 100022002 121 12 IF Ve3 gtAr 0001 23 12 RLH Spring 2004 ECE 4120 FloPt 5 RLH Spring 2004 7 Bit Example 2 o FPNSWith rb4 re4 m2 el pm2 SM unsigned normalized so msd 012102112 so value Sign 0mm 46 VM 001002 104 14 NLM 12 MIN VMMAX 011112 334 1516 NRV 12 4 2 96 VEMIN 002 04 NLE 4 VEMAX 112 34 VMIN 01002 400 104 40 14 VMAX 11112411 33443 330460 if Ve3 gt Ar 104 4 More values wider range more widely spaced ECE 412 F0Pt6 IEEE Floating Point Standard Std 754 orb 2 re2 m24 68 pm23 SM unsigned excess 127 MSB hidden not stored 31 30 23 22 1 0 IS leeeeeeee mmmmmmmmmmmmmmmmmmmmmmm V 1 S 1mmmm 2XXXXXXXX SE VE 127 V 1SgtXltVMgtXlt2VE SE gt VFPNOifVMO SE gt VE 126 Normal SE 127 gt VE O SE254 3 VE127 SE 255 3 VFPN NaN or in nty RLH Spring 2004 ECE 4120 FloPt 7 IEEE Floating Point Standard Std 754 VMMIN 100 02 1 NLM223 VM 11112 223923 NRV2232542 MAX VEMIN 1 127 126 NLE28 2 254 42 109 V 254 127 127 EMAX VMIN 100 O 239126 E 12 gt 103938 VMAX 11112127 E341038 o 223 E 8 106 E 7 signi cant decimal digits Ar 23923 2VE o Gradual under ow V lt 239126 denormalized when SE 0 VM 7 0 Hidden bit O 0 Error reporting NaN Not a Number 00 00 00 000 NaN op X gt SE 255 VM 7 O In nity when V gt 2 2127 gt SE 255 VM O RLH Spring 2004 ECE 4120 FloPt 8 IEEE FPNS Conversion Example 0 Convert IEEE value COSOOOOO16 to its decimal value 3130 27 23 l8 14 10 1V10000000 0100000 000000000000000 C 0 5 0 0 0 0 016 s1 SE128 vE1 vM11010 02 162510 v11 1625 21 325010 RLH Spring 2004 ECE 4120 FloPt 9 IEEE FPNS Addition Floating Point Add Positive Operands Align smaller value 12 102 12 103 Shift Right 1 24 103 lgt 24 103 252 103 101quot 23 101 23 11122 gt 111quot 23 SR1 10001 23 l Post Normalize SR1 10001 24 RLH Spring 2004 ECE 4120 FloPt 10 IEEE FPNS Addition Hardware Diagram Databus 310 33 l 23 1 23 8 s 1 I 1 I I MA I I MB I I EA I I EB I I 24 I 24 8 8 I Align MA I I Align MB I SR 11 24 I 24 A B I D I Cout F cm I M 24 7 Adjust 5616 24 MM 0 E Incremant for I Normalize M I SR 1 Nonnallze 8 23 38 Reg sY 35 Reg 35 Reg 23 Databus 310 32 ECE 4120 FloPt11 RLH Spring 2004 IEEE FPNS Addition Algorithm Version 1 1 0 Add positive normalized operands o Omit gradual under ow NaN 00 1 LoadA B Ahgned 2 Align l l FPADD V1 3 Add Mantissas M MA MB overall 4 Normalize 5 Store Y RLH Spring 2004 ECE 4120 FloPt 12 Version 1 2 EA DB3023 MA l DB220 hidden bit MSB 139 LoadA B EB DB3023 MB l DB220 hidden bit MSB F D EA EB If D lt 0 then A smaller E EB Shift Right MA by D gt MA 2 Ahgn lt Else D Z 0 B smaller E EA Shift Right MB by D gt MB k Endif RLH Spring 2004 ECE 4120 FloPt 13 Version 1 3 If M24 1 then Shift Right M by 1 4 Normalize E E 1 Endif MY M 5 Store Y EY E SY lt 0 RLH Spring 2004 ECE 4120 FloPt 14 IEEE FPNS Addition Algorithm Version 18 1 o More efficient with special case than Version 1 0 Special Case Exponents differ by gt 24 o All steps except 2 align are the same as Version 1 RLH Spring 2004 ECE 4120 FloPt 15 Version 18 2 D EA EB IF D Z 24 then B very small MB 0 E E A Elseif D Z 0 then B smaller Shift Right MB by D gt MB E E A 2 Align Elseif DS 24 then A very small MA 0 E EB Else D lt 0 A smaller Shift Right MA by D gt MA E EB Endif RLH Spring 2004 ECE 4120 FloPt 16 IEEE FPNS AdditionSubtraction Solve Need 2 extra bits iA 110 22 2 s comp 00110 i iB gt 111 quot 22 gt 11001 iY 01 quot 22 1111 Negate 00001 22 Mantissa amp Sign Nomahze 1 SL2 100 20 S 1 RLH Spring 2004 ECE 4120 FloPt 17 IEEE FPNS AdditionSubtraction Hardware Databus 310 32 8 8 1 l 23 1123 IEA EB llsAllsBl 39MA quot MB39 s s AlignMA AlignMB SRn Add MA 24 MB 24 gt 00 00 8611 SignLogic GA E D AS 26ng gdsub j l T Msign 26 Adjust E 8 ES SR1 or SL 11 Databus 310 32 RLH Spring 2004 ECE 4120 FloPt 18 IEEE FPNS AdditionSubtraction Algorithm Version 2 1 1 Load A B 2 Align FP ADDSUB 3 Add or Sub Mantissas overall 4 Normalize 5 Store Y RLH Spring 2004 ECE 4120 FloPt 19 Version 2 2 F SA DB31 EA DB3023 MA 1 DB220 hidden bit MSB 1L0adAB lt SB DB31 EB DB3023 K MB 1 DB220 hidden bit MSB 2 Align Same as VIS Align RLH Spring 2004 ECE 4120 FloPt 20 Version 2 3 MYlt M 5 StoreY BY 13 SYlt S Steps 3 and 4 are discussed on the following pages RLH Spring 2004 ECE 4120 FloPt 21 Version 2 4 Possible Add Sub Combinations A A A A B 3913 B B AB AB AB AB A B A B gt Basica11y A A 39A A AB or B 3913 39B B AB or AB AB AB AB 39 MB or AB ABJ AB RLH Spring 2004 ECE 4120 FloPt 22 Version 2 5 CASE Sub amp SAOamp SB 1 or Addamp SAOamp SBO MMAMB s0 Sub amp SAOamp SBO or Addamp SAOamp SB1 MMA MB s0 Sub amp SA1amp SB 1 or Addamp SA1amp SBO 3 AddSub M 2 MA 39 MB7 S 1 Mantissas Sub amp SA1amp SBO or Addamp SA1amp SB1 MMAMB S1 END CASE If MSIGN 1 then If negative mantissa then M lt M Make positive abs value S lt S Change sign End If RLH Spring 2004 ECE 4120 FloPt 23 Version 2 6 If MOthenElt O Emil Else If M24 1 then llXXX Shift Right M by l Ol lXXX E E l Else Bit 24 23 0 4N01ma1ize lt While M23 0 do 0001xx Shift left M by 1 E E l 01 XX End While End If RLH Spring 2004 ECE 4120 FloPt 24 IEEE Floating Point Multiplication Examples simpler than addition EX 1 60 102 gt Mult Mantissas Add Exponents X 40 103 240 105 EX 2 101 23 gt No Alignment needed X 110 24 0 0 0 1 0 1 1 0 1 Ol l 1 0 27 gt No Normalization 111 27 Rounding RLH Spring 2004 ECE 4120 FloPt 25 IEEE Floating Point Multiplication Examples EX 3 111 21 gt No Alignment X 111 25 11 1 1 1 1 11 1 IEIO 0 1 26 gt Normalize SR1 011000127 110 27 RLH Spring 2004 ECE 4120 FloPt 26 IEEE Floating Point Multiplication Hardware IEAIIEBIISAIISBI IMAI IMBI T8 T8 l l T24 T24 Add Sign Logic Integer HOW gt Excess 127 XOR Multiplier P 8 24 Increment I Normalize ISRU T 24 M SY Y RLH Spring 2004 ECE 4120 FloPt 27 IEEE Floating Point Division Examples similar to Multiplication EX 1 6 102 15 10391 gt Divide Mantissas Subtract Expo 4 103 10 0 22 EX2 110 1 24 1010110 00 Q 101 22 0 101 4 r4 1 0 0 22 R ignored 524 gt No alignment N0 normalization RLH Spring 2004 ECE 4120 FloPt 28 IEEE Floating Point Division Examples 010 22 EX3 100 1 24 111 010000 22 Q 111 1 22 0111 2 r2 1 101 failed 7 1000 M 0 010 22 R ignored gt Normalize SL1 100 21 RLH Spring 2004 ECE 4120 FloPt 29 IEEE Floating Point Division Hardware IEA EBI ISAHSBI IMAI llll ll subtraCt Sign Logic Integer HOW gt Excess 127 XOR DlVldeT Q R i separate norm and exp if R needed I Normalize l 8141 M RLH Spring 2004 ECE 4120 FloPt 30 Decrement Y Floating Point Extra Bit Errors 0 Bit Shifting for Align and Normalize can create Wider words 0 Must be reduced to standard Width result 0 Reduction creates error and bias depending on method Truncation Rounding Others RLH Spring 2004 ECE 4120 FloPt 31 Extra Bit Errors Examples 4bit Addition Example 110120 AlignSR3 gt 0001i1010 23 100123 1001 1 0 1 05 1 0 1 0 H4 1f 4b1t Reducing width Add causes a small error RLH Spring 2004 ECE 4120 FloPt 32 Extra Bit Errors Examples 4bit Subtraction Example Subtract and Normalize exact sub gt 0 0 0 l l l 0 0 if 8bit subtracter Norm SL3 l l l 0 if 4bit subtracter Norm SL3 IMO Bad Error Need double Width ALU to prevent loss of signi cance We must usually consider 0 Increased ALU Reg Width 0 Rounding method RLH Spring 2004 ECE 4120 FloPt 33

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