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# SP TP SENSORNETS CPSC 689

Texas A&M

GPA 3.75

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This 13 page Class Notes was uploaded by Ms. Jerad Bernhard on Wednesday October 21, 2015. The Class Notes belongs to CPSC 689 at Texas A&M University taught by Staff in Fall. Since its upload, it has received 12 views. For similar materials see /class/226088/cpsc-689-texas-a-m-university in ComputerScienence at Texas A&M University.

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Date Created: 10/21/15

Power Issues with Embedded Systems Rabi Mahapatra Computer Science MahapatraTexas AampMSpn39ngDZ 1 Plan for today Some Power Models Familiar with technique to reduce power consumption Reading assignment paper by Bill Moyer on LowPower Design for Embedded Processors Proceedings of IEEE Nov 2001 MahapatraTexas AampMSpn39ngDZ Next Generation Computing Watts metrics Networks l pwpsPDAs g Cellphones ops 1 Serv Data Processing Mega Wam MahapatraTexas AampMSpn39ngDZ 3 Power Aware Increase in prominence of portable devices SoC complexity heat generation Traditionally speed performance amp area cost Now add power as the new axix MahapatraTexas AampMSpn39ng 02 Physics Revisited Energy is in Joules Power Rate of energy consumption joulessec in Watt Vddld instantaneous power MahapatraTexas AampMSpn39ngDZ 5 Impact on embedded system Energy consumed per activity reduces battery life 7 Decreases battery capacity fast IR drops in a battery due to ow of current 7 Requires more Vdd amp GND pins to reduce R also thickampwide wiring is necessary Inductive Power supply voltage bounce due to current switching 7 Requires more amp shorter pins to reduce inductance 7 Require on chip decoupling capacitance to help bypass pins Power dissipation produces heat and high temperature reduces speed and reliability MahapatraTexas AampMSpn39ngDZ 5 Opportunities for LowPower Algorithms Source Code C ompiler Operating System ISA Microarchitecture Circuit Design Manufacturing Minimize Operation Optimized code Energy rniser Scheduling Energy Exposed Clocked Gating Low voltage swing Lowk dielectric MahapatraTexas AampMSpn39ng02 Some Power Models Macro level 7 Arithmetic 7 Software 7 Memory Activity Based 7 Empirical 7 Informationtheoretic 7 Signal modelingbased MahapatraTexas AampMSpn39ng02 Empirical Based on chip estimation system Glaser ICCAD91 P OLGEr CLlVdd2f G number of equivalent gates Er energy consumed by an equivalent gate CL average loading per gate including fanout 0L activity factor Demerit lacks consideration on different logic styles MahapatraTexas AampMSpringDZ 9 Information Theoretic Reference Najm95 Based on activity estimation P k Can kAh A area h entropy factor a function of entropy H Limited accuracy does not include possibility of encoding MahapatraTexas AampMSpringDZ 10 Signal Model Based Reference Landman TCAD96 7 Properties of 2 s complement encoded data stream 7 Arithmetic blocks are regular Analytical Method Ramprasad TCAD97 7 Wordlevel statistics 7 Autoregressive Moving Average signal generation model 7 2 s complement amp sign magnitude signal encoding MahapatraTexas AampMSpringDZ Software Power Power consumed by a processor P Ref TiwariTVLSI94 P Vdd 1 Energy E E P Tp program execution time Program Execution TimeTp Tp Nquot Tclk E 7 P Tp vdd 1NTclk If Vdd and Tclk are assumed to be constant Energy is measured by measuring current 1 Lowpower software small value of N or fast execution time When Vdd and Tclk are varying Current measurements MahapatraTexas AampMSpringDZ Instruction Level Power Modeling Reference Tiwari TVLSI97 Current consumption of a program with no loops but M instruction 1 240 Bk Nk O ii1modM 240 Nk Bk Base current of kth instruction in the program Nk Number of clocks required to complete kth instruction 0 i j overhead of executing successive instruction MahapatraTexas AampMSpringDZ 13 Power Dissipation in CMOS Three sources Pswitching Switching power capacitive dominant today Pleakage Leakage Power will dominant in 013 micron and below Pshmcircuit Schort c1rcu1t component MahapatraTexas AampMSpringDZ 14 Switching Power Dissipation Occurs when device changes state or switching of charge in and out of CL capacitance Flow of current across the transistor s impedence P tCLV2ddf 7 t average number of transition per cycle 7 f clock frequency switching 7 CL effective capacitance Increases with clock frequency Decreases quadratically with supply voltage 8590 of active power consumption MahapatraTexas AampMSpringDZ LowPower Techniques Lowpower techniques reduces one or more of t CL Vdd and f 7 t encoding 7 CL fast algorithm design layout 7 Vdd voltage scaling variable voltage processor 7 f lowfrequency and clock gating All of these are useful for embedded system MahapatraTexas AampMSpringDZ Short Circuit Power Dissipation Occurs due to the overlapped conductance of both PMOS and NMOS transistors forming a CMOS logic gate as the input signal transitions Pshortcircuit Imean Vdd 1020 contribution to dynamic power Not important if all signals are guaranted to have steep slopes MahapatraTexas AampMSpn39ngDZ 17 Leakage Power Dissipation Occurs regardless of state change Due to leakage currents from reversed biased PN junction OFF switches are not really off Proportional to device area and temperature Increases exponentially with reduction in Vt voltage scaling Signi cant when system is idle Embedded Systems MahapatraTexas AampMSpn39ngDZ 18 Total Power P Static Power Not a factor in pure CMOS designs Sense ampli er voltage references and constant current sources contribute to the static power Regardless of device state change P PstaticPleakage switching shortcircuit MahapatraTexas AampMSpringDZ 19 Power Delay Leverage Power amp Delay trade off Speed is proportional to CL Vdd Vdd 7 V015 Trends Reduce Vdd amp V1 to improve speed Energydelay product is minimized when Vdd 2 Vt Reducing Vdd from 3 VI to 2 Vt results in an approximately 50 decrease in performance while using only 44 of the power MahapatraTexas AampMSpringDZ 20 Algorithmic Technique PR Focus on minimizing number of operation weighted by their cost First order goal 7 Underlying implementation arithmatic or logical Recomputation of intermediate results may be cheaper than memory use Loop unrolling reduces loop overhead Number representation 7 fixed point or oating point 7 Signmagnitude versus 2 s complement is preferred in certain DSP when input samples are uncorrelated and dynamic range minimum 7 Bit length of course trade off accuracy 7 Adaptive bit truncation in portable video encoder reduces 70 of the power over full bit width MahapatraTexas AampMSpringDZ 21 Architectural Technique PR Instruction set design and exploiting parallelism amp pipelining are important Architecture driven voltage scaling method Chandrakasan IEEE J Solid state Circuits 92 7 Lower voltage for power but apply parallelismpipeline to speedup 7 Possible if application has parallelism tradeoff with latency due to pipeline amp data dependencies and area 7 Speculative logic allowed if low overhead else determental Meeting required performance without overdesigning a solution is fundamental optimization 7 Extra logic power is not controllable and they still present even if parallelism is absent MahapatraTexas AampMSpringDZ 22 Logic and Circuit Level PR Focus on reducing switched capacitance or and signal swing Signal probabilities may favor either static or dynamic CMOS logic 7 ample Twoinput NAND gate with uniform distribution at inputs probability of output being 0 p0 is 025 pl 075 7 For static gate probability of a power consuming transition from 0 gt 1 is p0p1 7 01875 7 For dynamic gate with the output precharged to logic 1 power is consumed whenever the output was previously 0 Thus it has higher by 025 transition at output than static 7 However dynamic circuit has lower input capacitance by a factor of 2 to 3 MahapatraTexas AampMSpringDZ 23 Logic circuit PR For wider input static gate say four input NAND p0 00625 and p0 gt 1 is 00586 For dynamic version as above p0 p0 gt 1 00625 Static logic suffers from glitches needs restructuring and that adds up power more than 20 X T f Restructured Logic MahapatraTexas AampMSpringDZ 24 Logic circuit PR Mapping logic function to gates is tricky too P 0 25 P 0 5 P 0 0625 Metal 05625 P 0 25 P0 5 P 0 125 P d0 0625 P060104 4375 MahapatraTexas AampMSpn39ng 02 25

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