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by: Ms. Jerad Bernhard


Ms. Jerad Bernhard
Texas A&M
GPA 3.75


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Class Notes
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This 9 page Class Notes was uploaded by Ms. Jerad Bernhard on Wednesday October 21, 2015. The Class Notes belongs to CPSC 489 at Texas A&M University taught by Staff in Fall. Since its upload, it has received 15 views. For similar materials see /class/226084/cpsc-489-texas-a-m-university in ComputerScienence at Texas A&M University.

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Date Created: 10/21/15
Design Interface and VerificationI Introduction to a model of interfacing components in a design and its verification MahapatraAXLMFEIIDO Interfacing components Process is an independent part of a computation done concurrently with other parts VHDL UNIX Thread is used in Java Component in Codesign COMPONENT name declaration local quantities of components used in computation computation MahapatraAXLMFEIIDO Telephone switch components 0 COMPONENT unit physical phone that detects the o ehook sends id and disconnects pmhoneicannector computation END unit COMPONENT connect check receiver not busy rree capacity arbiter COMPONENT transfer transmits digitized sound from common memory data transmission constantly in both directions Mahapah aAXLMFEIIDO Interfacing components Interface determines the coordination of the components including their data trans fer and synchronization Codesign demands heterogeneous interface modeling 7 Can not favor any one existing technology or signaling discipline alone A c ofnpbne39n t 39 component B Interface Mahapah aAXLMFEIIDO Interfacing components contd Interface model allows components to share one or more state variable ie simple Boolean integer buffer and other data type 7 Sharing value of state variable in interface may be changed by several different components 7 Undisciplined used of shared variable can lead to time dependent design errors which can be difficult to locate MahapatraAXLMFEIIDO 5 Telephone switch COMPONENT MnnhnnkBOOLEAN ltlt anyhooka 052p dialing sequ2n52gtgt Shared Van39 able onhook MahapatraAXLMFEIIDO 6 More Components of telephone switch After receiving dialing sequence the dialing component has the number until to be called this number is exchanged with the transfer component and therefore part of the interface COMPONENT dial0nh00k39BOOLEAN recinumber Together the arthook and recnumber makes up the interface between the dial and connect components of one unit they are grouped as record TYPE InterfaceDialCann Interface dialconnect campanentquot RECORD arthook BOOLEAN z39ndicale receiver on haakquot recinumber number Dialledphane END MahapatraAXLMFEIIDO 7 Physical Realization of State Variable Software as program variable in memory hardware wire connecting subcircuits 0 wires contain current value of state variable provision of refresh to remain current A state variable x is interpreted as a function from Time to its range of values eg x is boolean we have Mb x Time gt B Example Analog signal coming from microphone of a telephone Signal can be represented by state variable interface Mv v0ice39Time gt Freq The interface of an AD converter transforming analog input to discret 8 bit sample can be described as follows COMPONENT adcanvert n analog frequency out 0 255 MahapatraAXLMFEIIDO 8 Verification Veri cation is important for nontrivial design projects Ideally all exhaustive check is required but seldomely possible in practice Formal methods are more recent 7 Formality is a possibility but should not be mandatory Three kinds of formal methods are used at different stages of design process 7 Interface verification 7 design verification 7 Implementation verification MahapatraAXLMFEIIDO Interface verification What is interface verification Separate design to distinct components is common components interact through interface using coordination mechanism following the protocols 7 Designers might treat details on signaling differently across various components Leads to inconsistency gt Interface veri cation checks this inconsistencies MahapatraAXLMFall DO Design verification What is design verification Consists of verifying selected key requirements of incomplete models Example Arbiter 7 At most one device has access to common resources mutual exclusion Once the interface to bus has been designed it is possible to verify that it does not violate the mutual exclusion property even ifother components of the design are still missing MahapatraAXLMFEIIDO 11 Implementation verification To construct ef cient product it is necessary to re ne initial design into concrete realization typically includes a number of restrictions e g restrict integer values to a certain range so that you use xed number of bits Clearly it requires that the concrete realization has been done and hence implementation veri cation is relevant rather late in design process Now available in commercial design system MahapatraAXLMFEIIDO 12 Simplified Arbiter as an example COMPONENT arbiterreql grl reqr grr BOOLEAN INITIALLY grl FALSE grr FALSE ltlt reql A grr agrl TRUEgtgt H ltlt reql A grl agrl FALSEgtgt H ltlt reqr A grl agrr TRUEgtgt H ltlt reqr A grr agrr FALSEgtgt END arbiter Would check grr and grl are never both true This is mutual exclusion to beasserted grl A grr Reading assignment Section 651 of Text MahapatraAXLMFallDO 13 Interface Verification How is it possible to verify that different components have a consistent View of their interface 7 Allow them to have different views as long as these are not in con ict EX packet in communication protocol 7 An uninterrupted collection of bits to be transmitted vs structured packet with different fields indicating addresses control and checksum In codesign computational model interface of component consists of set of state variable and a protocol MahapatraAXLMFallDO 14 Interface verification contd Simple arbiter protocol fourphase 7 client requests the privilege by setting req to true 7 when gr becomes true the client enter its critical section 7 when leaving it req is set false 7 gr becomes false following req is set false This can be expressed formaly as follows reqposr reqpre grantpost reqpost grantpost grantpre grantpostreqpost Both the arbiter and the client may assume that the other components follow this protocol To verify that the changes made to gr by arbiter follow the protocol it must be shown that all its transitions obey grpost grpre reqpostgrpost39 Similarly for client reqpost reqpre reqpost grpost Mahapah aAXLMFEIIDO Design verification Requirements of a design are formalized as predicates constraining the computation Eg two grant signals never given simultaneous access Example Let us verify invariant in a design Invariant Sub Setofstate space containinginitjal state Further there must not be any transition from estate within the subset to a state T Tn 1 1 it ls on a state S is invariant lpre tprepost lpost To show that 7 grl A grr is an invariant for arbiter four implications must be shown le reql A grr A grl 7 grl A grr MahapatraAXLMFall DO Implementation verification Refine initial abstract design into concrete realization 7 This includes number of restrictions Both abstraction and realization are described form ally abstract design concrete design Abstract design consists of many possible scheduling algorithms vrs concrete des1gn is one of the possible realization 7 Thus concrete design wont exhibit all the behavior of abstract design Refer pp226227 for examples of concrete design of arbiter and the abstract arbiter 7 To show that the concrete design is a refinem ent one must show that any behavior exhibited by concrete design is also a possible behavior of abstract design MahapatraAXLMFEIIDO


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