DIG INTEGRATEDCKT DES
DIG INTEGRATEDCKT DES ECEN 454
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This 47 page Class Notes was uploaded by Dr. Amani Grimes on Wednesday October 21, 2015. The Class Notes belongs to ECEN 454 at Texas A&M University taught by Jiang Hu in Fall. Since its upload, it has received 28 views. For similar materials see /class/226247/ecen-454-texas-a-m-university in ELECTRICAL AND COMPUTER ENGINEERING at Texas A&M University.
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Date Created: 10/21/15
J ECEN 454 Digital Integrated Circuit Design Lecture 2 CM05 Circuit 2 ECEN 454 Lecture 2 Complementary CMOS E Complementary CMOS logic gates nMOS pulldown network pMOS pMOS pullup network gm aka static CMOS inputs output nMOS pulldown Pullup OFF Pullup ON quote m39k Pulldown OFF Z float 1 Pulldown ON 0 X crowbar ECEN 454 Lecture 2 2 CMOS Inverter A Y V DD 1 A Y A gt9Y GND ECEN 454 Lecture 2 CMOS Inverter A Y V DD 1 0 OFF A1 YO ON GND ECEN 454 Lecture 2 CMOS Inverter Y V DD 0 ON A0 Y1 OFF A gt9 Y GND ECEN 454 Lecture 2 Negative Function When input 0gt 1 output 1gtO or unchanged NMOS is turned on pulldown When input 1gt0 output Ogt1 or unchanged PMOS is turned on pullup Static CMOS implements negative functions ECEN 454 Lecture 2 CMOS NAND Gate A A B D 13 ECEN 454 Lecture 2 CMOS NAND Gate 7 A B Y o W ON W ON 0 1 Y1 1 0 A390 OFF 1 1 3 0 OFF D 13 ECEN 454 Lecture 2 8 CMOS NAND Gate 7 A B Y 0 W OFF ON 1 Y1 0 A 0 OFF 1 B 1 ON D 13 ECEN 454 Lecture 2 9 CMOS NAND Gate A ON A OFF BO D 13 ECEN 454 Lecture 2 10 CMOS NAND Gate 7 A 1 OFF OFF YO ON 1 ON D 13 ECEN 454 Lecture 2 11 CMOS NOR Gate 457 O 1 O 1 g f ECEN 454 Lecture 2 12 Series and Parallel nMOS 1 ON pMOS O ON Series both must be ON a Paralet either can be ON 2le ECEN 454 Lecture 2 o o g U ao cKo m n o A 91 U OO N O m 39n gU oAAm DEA x o o 91 U oN o m 91 D39 I n 39n o O A g U od o ao n O 35 0 O g am 0 Z Z 039 D 0 g 039 D O U m z O O O O z Um O 3 vii Conduction Complement x Complementary CMOS gates always produce 0 or 1 Ex NAND gate Series nMOS YO when both inputs are 1 Thus Y1 when either input is 0 All Gl Requires parallel pMOS Y A e Rule of Conducton Complements B l Pullup network is complement of pulldown Parallel gt series series gt parallel ECEN 454 Lecture 2 14 Pulldown Construction To implement logic function f NMOS for implementing 7 Implement AND by series connection Implement OR by parallel connection ECEN 454 Lecture 2 15 Pullup Construction PMOS for implementing f Using inversed input signal DeMorgan s Law I m Z I 14 45 Z E ECEN 454 Lecture 2 16 Compound Gate C4 A4 fABCD H Z z 5 V ECEN 454 Lecture 2 17 Logic Optimization For a complex logic function implement by a big compound gate or a set of small gates Depending on objectives area delay or else Solved by logic optimization ECEN 454 Lecture 2 18 Tristates Trl39state buffer produces Z when not enabled ECEN 454 Lecture 2 19 Tristates Trl39state buffer produces Z when not enabled EN EN va ECEN 454 Lecture 2 20 Nonrestoring Tristate 5 Transmission gate acts as tristate buffer Only two transistors But nonrestorng 0 Noise on A is passed on to Y EN L ADY I EN ECEN 454 Lecture 2 21 Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output ECEN 454 Lecture 2 22 Tristate Inverter recr Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output M Z M o m ECEN 454 Lecture 2 23 Multiplexers 21 mutpexer chooses between two inputs 8 D00 D1 1 ECEN 454 Lecture 2 24 Multiplexers 21 multiplexer chooses between two inputs 8 D00 D1 1 ECEN 454 Lecture 2 25 GateLevel Mux Design 1 EDO too many transistors How many transistors are needed ECEN 454 Lecture 2 26 GateLevel Mux Design 133 Y SD1 D0 too many transistors How many transistors are needed 20 31 DO Y ECEN 454 Lecture 2 27 Transmission Gate Mux Nonrestoring mux uses two transmission gates ECEN 454 Lecture 2 28 Transmission Gate Mux 5 Nonrestoring mux uses two transmission gates Only 4 transistors s L DO D1 ioii S ECEN 454 Lecture 2 29 Inverting Mux Inverting multiplexer Use compound A0122 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter DO lv s D0 D1 3 8 D1 8 s Y Y DO 0 s s s s Y D1 1 ECEN 454 Lecture 2 30 D Latch When CLK 1 latch is transparent D flows through to Q like a buffer When CLK 0 the latch is opaque Q holds its old value independent of D aka transparent latch or levelsen5tIe latch CLK CLK C D o D E Q I Q ECEN 454 Lecture 2 31 D Latch Design 231 Multiplexer chooses D or old Q ECEN 454 Lecture 2 32 D Latch Operation Q Q CLK1 CLK0 CLK OI D Q ECEN 454 Lecture 2 33 D Flipflop When CLK rises D is copied to Q At all other times Q holds its value aka positive edgetriggered p op mastersa Ie p op Flop g O 34 ECEN 454 Lecture 2 D Flipflop Design 22 Built from master and slave D latches I r 7 O r 7 J Q M J D lj E Q JK DO I J CLK J l CLK CLK ECEN 454 Lecture 2 35 f D Flipflop Operation 7 D gtOQM u CLK0 L jg v 21 if LET CLK D Q R ECEN 454 Lecture 2 ECEN 454 Digital Integrated Circuit Design Lecture 4 Transistor I l CharacterStics 2 ECEN 454 Lecture 4 Transistor Model So far we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive currentvoltage IV relationships Transistor gate source drain all have capacitance I c AVAt gt At CI AV Capacitance and current determine speed Also explore what a degraded levelquot really means 4E 4 4E a ECEN 454 Lecture 4 2 MOS Capacitor 7 Gate and body form MOS capacitor 36 Operating modes Accumulation Depletion Inversion polysilicon gate Vg lt 0 silicon dioxide insulator 639 6969 ptype body a 0 lt Vg lt Vt depletion region b Vg gt Vt inversion region depletion region 6 a a 1 gr 1 eeeeeeee u v 3 u u v Iy C ECEN 454 Lecture 4 Terminal Voltages E v Mode of operation depends on V9 Vd VS 9 vgs vg vs vg l vgd v v v gd 9 d l l I Vds Vs Vgs VS Vd ds Source and drain are symmetric diffusion terminals By convention source is terminal at lower voltage Hence Vols 2 0 nMOS body is grounded First assume source is 0 too Three regions of operation Cutoff Linear Saturation ECEN 454 Lecture 4 nMOS Cutoff 5235 No channel Ids O V Jud eyeg eeemwa a 9 B B ptype body b ECEN 454 Lecture 4 nMOS Linear Channel forms Current flows from CI to s V efmmsmd a Ids Increases With Vds Vds0 Similar to linear resistor g g e b VgsgtnggtVt LZT 39 W a 3 JEIdS 9 ECEN 454 Lecture 4 6 nMOS Saturation Channel pinches off 2 Ids independent of Vals We say current saturates Similar to current source G7 AI 11 II I l r eeeee D V gtV V eeeeee can 5 ptype body b ECEN 454 Lecture 4 IV Characteristics 7 In Linear region Ids depends on How much charge is in the channel How fast is the charge moving ECEN 454 Lecture 4 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel 391 5 Qchannel W source gs 9 ad drain I t Vt n 39 n SiO2 gate oxide Vds good Insulator 90X 39 ptype body ptype body ECEN 454 Lecture 4 9 Channel Charge 233 MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel 139quot 55 Qchannel CV ii E C L SiO2 gate oxide ds M m good insulator 90X 39 ptype body ptype body ECEN 454 Lecture 4 10