DIG INTEGRATEDCKT DES
DIG INTEGRATEDCKT DES ECEN 454
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This 41 page Class Notes was uploaded by Dr. Amani Grimes on Wednesday October 21, 2015. The Class Notes belongs to ECEN 454 at Texas A&M University taught by Jiang Hu in Fall. Since its upload, it has received 27 views. For similar materials see /class/226247/ecen-454-texas-a-m-university in ELECTRICAL AND COMPUTER ENGINEERING at Texas A&M University.
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Date Created: 10/21/15
ECEN 454 Digital Integrated Circuit Design Lecture 19 Design for TestabYity 2 ECEN 454 Lecture 19 Test Cost Test pattern generation Fault simulation Generation of fault sites information Test equipment Test process Test cost may overweight design cost ECEN 454 Lecture 19 Why Design for Testability Testability is a design characteristic that influences various costs associated with testing It allows for Device status to be determined Isolation of faults Reduce test time and cost ECEN 454 Lecture 19 3 Controllability Ability to establish a specific signal value at each node by setting circuit s inputs Circuits typically difficult to control decoders circuits with feedback oscillators clock generators ECEN 454 Lecture 19 Observability Ability to determine the signal value at any node in a circuit by controlling the circuit s inputs and observing its output ECEN 454 Lecture 19 Predictability Ability to obtain known output values in response to given input stimuli Factors affecting predictability Initial state of circuit Races Hazards ECEN 454 Lecture 19 Difficult Test Cases Sequential logic is more difficult to test than combinational logic Control logic is more difficult to test than data path logic Random logic is more difficult to test than structured busoriented designs Asynchronous design is more difficult to test than synchronous design ECEN 454 Lecture 19 7 Quantify Testability Need approximate measure of Difficulty of setting internal circuit lines to O or 1 by setting primary circuit inputs Difficulty of observing internal circuit lines by observing primary outputs Uses Analysis of difficulty of testing internal circuit parts redesign or add special test hardware Guidance for algorithms computing test patterns avoid using hardtocontrol lines Estimation of fault coverage Estimation of test vector length ECEN 454 Lecture 19 8 Types of Measures SCOAP Sandia Controllability ancl Observability Analysis Program Combinational measures CCU Difficulty of setting circuit line to logic 0 CC Difficulty of setting circuit line to logic 1 C0 Difficulty of observing a circuit line Sequential measures analogous 5C0 5C 50 ECEN 454 Lecture 19 Range of SCOAP Measures 39 Controllabilities 1 easiest to infinity hardest 39 Observabilities O easiest to infinity hardest 39 Combinational measures Roughly proportional to circuit lines that must be set to control or observe given line 39 Sequential measures Roughly proportional to times a flipflop must be clocked to control or observe given line ECEN 454 Lecture 19 10 4Controllability Examples 080 a 001 a a 2 000 z m139n 000 a 000 12 1 b 001 z 001 a 001 b 1 000 b 001 b a z 000 z 000 a 000 b 1 b 001 z min 001 a 001 2 1 a z 000 z m1nCCOa 000 b 001 a 001 11 1 b 001 z m1n001 511 000 b 000 a 001 11 1 a z 000 z 001 a 001 b 1 b 001 z 1111111000 a 000 11 1 ECEN 454 Lecture 19 11 4 Observability Examples 00 a 001 a 00 a 00 2 001 b 1 3 000 3 0022 00 b 00 z 001 a 1 13W 001 b 00 a 00 z 000 b 1 13 00 b 00 z 000 a 1 b 00 a 00 z min 0001 001 0 1 a z 00 b 00 z min 000 a 001 51 1 ij 00 a00z001 b1 a Dig 00 bCO z001 a1 b ECEN 454 Lecture 19 12 Goal of Design for Testability DFF Improve Controllability Observability Predictability If each register could be observed and controlled test problem reduces to testing combinational logic between registers Better yet logic blocks could enter test mode where they generate test patterns and report the results automatically ECEN 454 Lecture 19 13 Design and Test Tradeoff Most DI I39 Design for Testability techniques need extra hardware or modification to circuits that may affect performances to DI I39 need to consider the cost tradeoff between design and test ECEN 454 Lecture 19 14 DFl39 Methods DI I39 methods for digital circuits Adhoc methods Structured methods 0 Scan 0 Builtin selftest BIST ECEN 454 Lecture 19 15 AdHoc DFI39 Methods 7 Good design practices learnt through experience are used as guidelines Avoid asynchronous unclocked feedback Make flip flops initializable Avoid redundant gates Avoid large fanin gates Provide test control for difficulttocontrol signals Avoid gated clocks Design reviews conducted by experts or design auditing tools Disadvantages of adhoc DFI39 methods Experts and tools not always available Test generation is often manual with no guarantee of high fault coverage Design iterations may be necessary ECEN 454 Lecture 19 16 Scan Design Circuit is designed using prespecified design rules Test structure hardware is added to the verified design Add a test control TC primary input Replace flipflops by scan lly ops SFF and connect to form one or more shift registers in the test mode Make inputoutput of each scan shift register controllableobservable from PIPO ECEN 454 Lecture 19 17 Scan Design Rules Use only clocked Dtype of flipflops for all state variables At least one PI pin must be available for test more pins if available can be used All clocks must be controlled from PIs ECEN 454 Lecture 19 18 Correcting a Rule Violation All clocks must be controlled from PIs ECEN 454 Lecture 19 19 Scan Storage Cell Q So Si NT Clk ECEN 454 Lecture 19 20 fScan FlipFlop SFF 1E m ECEN 454 Lecture 19 21 Scan Methods ECEN 454 Lecture 19 22 Integrated Serial Scan Pl PO Combinational SCANOUT logic Control SCANIN ECEN 454 Lecture 19 23 Scan Chain Convert each flipflop to a scan register Contents of flops can be scanned out and new values scanned in scanin inputs outputs soanout ECEN 454 Lecture 19 24 BIST Builtin Self Test PRPG Pseudo Random Pattern Generator ORA Output Response Analyzer CUT Circuit Under Test Start PIE PO Passfail ECEN 454 Lecture 19 25 BIST Motivation Useful for field test and diagnosis less expensive than a local automatic test equipment ECEN 454 Lecture 19 26 Benefits and Costs of BIST Level Design Fabri ManufMaintenance Diagnosis Service and test cation Test test and repair interruption Chips 1 Boards 1 System l Costincrease Cost saving l Cost increase may balance cost reduction ECEN 454 Lecture 19 27 Economics BIST Costs I Chip area overhead for Test controller Hardware pattern generator Hardware response compacter Testing of BIST hardware I Pin overhead at least 1 pin needed to activate BIST operation I Performance overhead extra path delays I Reliability reduction due to increased area and complexity ECEN 454 Lecture 19 28 BIST Benefits 7 Reduced testing and maintenance cost Lower test generation cost Reduced storage maintenance of test patterns Simpler and less expensive ATE Can test many units in parallel Shorter test application times Can test at functional system speed ECEN 454 Lecture 19 29 BIST Types OnIine BIST Concurrent Nonconcurrent Offline BIST Functional Structural ECEN 454 Lecture 19 30 nk BIST Architecture 7 Test fIZI E I I Controiier l ROM I I l I v I I Reference v v v Signature Hardware mp CircuitUnder Test 0 Output Pa ttem h MUX h with optionai Response h Comparator Generator modifications Compacter A Primary Primary Inputs Outputs Signature GWFEUIW ECEN 454 Lecture 19 31 PseudoRandom Pattern Generation through LFSR Xn I XnB X1 X0 Linear Feedback Shift Register LFSR Produces patterns algorithmically repeatable Has most of desirable random properties Long sequences needed for good fault coverage ECEN 454 Lecture 19 32 Response Compaction Severe amounts of data in CUT response to LFSR patterns example Generate 5 million random patterns CUT has 200 outputs 5 million x 200 1 billion bits response Uneconomical to store and check all of these responses on chip lgt Responses must be compacted ECEN 454 Lecture 19 33 LFSR for Response Compacter asy Characrerfsrfc Polynomia X5 x 3 x 1 D90 D90 DO D105 00 H f WE rquot ECEN 454 Lecture 19 34 Signature Analysis Signature any statistical circuit property distinguishing between bad and good circuits Aliasing due to information loss signatures of good and some bad machines match Signature analysis compare good machine response into good machine signature Actual signature generated during testing and compared with good machine signature ECEN 454 Lecture 19 35 BILBO Builtin Logic Block Observer BILBOI 811802 LFSR CUT h LFSR CUTE Linear Feedback Linear Feedback Shift Register Shift Register Pattern Response Generator I Compacter Response Pattern Compacter Generator Four modes Flipflop AwNI h LFSR pattern generator LFSR response compacter Scan chain for flipflops ECEN 454 Lecture 19 36 Example of BILBO Combined functionality of D flipflop pattern generator response compacterand scan Chain 51 lD1 3902 52 I i 2 s W5 Do Do Clock r1 C C ECEN 454 Lecture 19 BILBO Serial Scan Mode 52 00 Dark lines show enabled data paths B1 0 D1 32 82 I T I T EI V V L9 ea ClOCk 0 Q1 02 ECEN 454 Lecture 19 38 BILBO LFSR Pattern Generator Mode 52 01quot B1 0 D1 3902 52 1 IT IT I V v SI 5 DO DO Clock IN C C 01 02 ECEN 454 Lecture 19 39 BILBO in DFF Normal Mode 52 10 0 Clock r7 C 0 ECEN 454 Lecture 19 40 BILBO in Response Compactor Mode 52 11quot B1 1 F1 3902 52 1 I T I T EI V V 8 KW 00 00 Clock r7 C C 01 02 ECEN 454 Lecture 19 41