DIG INTEGRATEDCKT DES
DIG INTEGRATEDCKT DES ECEN 454
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Date Created: 10/21/15
ECEN 454 Digital Integrated Circuit Design Lecture 6 SPICE Slinulaton 2 ECEN 454 Lecture 6 Introduction to SPICE Simulation Program with Integrated Circuit Emphasis Developed in 1970 s at Berkeley Many commercial versions are available HSPICE is a robust industry standard 0 Has many enhancements that we will use Written in FORTRAN for punchcard machines Circuits elements are called cards Complete description is called a SPICE deck ECEN 454 Lecture 6 2 Writing Spice Decks Writing a SPICE deck is like writing a good program Plan sketch schematic on paper or in editor o Modify existing decks whenever possible Code strive for clarity 0 Start with name email date purpose 0 Generously comment Test o Predict what results should be 0 Compare with actual o Garbage In Garbage Out ECEN 454 Lecture 6 Example RC Circuit rcsp David Harrishmcedu 2203 Find the response of RC circuit to rising input R1 ZKQ Parameters and models Vin C1 VOUt 100fF option post Simulation netlist Vin in gnd pwl Ops 0 100ps 0 150ps 18 800ps 18 R1 in out 2k C1 out gnd 100f tran 20ps 800ps plot vin vout end ECEN 454 Lecture 6 4 9 343911331 17917 NEIDEI dunnn39nna m E r f n n 4 n n m n n n n 4 n n m n q q a a a a a a a H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H HH 9 q nnnn39z DUDE39I nnnn39I mnnnn39nns 39n qE a IEmXBJ llnSBH Result Graphical vout 15 10 05 0390 39I I I I I I I I I I 00 100p 200p 300p 400p 500p 600p 700p 800p 900p tS ECEN 454 Lecture 6 Sources DC Source Vdd vdd gnd 25 Piecewise Linear Source Vin in gnd pwl Ops 0 loops 0 150ps 18 800ps 18 Pulsed Source Vck clk gnd PULSE 0 18 Ops 100ps 100ps 300ps 800ps PULSE v1 v2 td tr tf pw per td tr pw tf LIA LIA LI 7quot l v2 4 m ECEN 454 Lecture 6 7 SPICE Elements ECEN 454 Lecture 6 Units Letter Unit Magnitude a atto 103918 f fempto 103915 p pico 103912 n nano 10399 u micro 10396 m mili 10393 k kilo 103 x mega 106 g giga 109 Ex 100 femptofarad capacitor 100fF 100f 100e 15 ECEN 454 Lecture 6 DC Analysis mosivsp Parameters and models include 39modelstsmc180modelssp39 temp 70 option post Vgs Simulation netlist nmos Vgs g gnd 0 Vds d gnd 0 M1 d g gnd gnd NMOS W036u L018u Stimulus dc Vds 0 18 005 SWEEP Vgs 0 18 03 end ECEN 454 Lecture 6 10 IV Characteristics Ax 7 33 nMOS IV Vgs dependence 25039 Saturation 200 150 Ids HA 100 50 0 00 03 06 09 12 15 ECEN 454 Lecture 6 11 MOSFET Elements 7 M element for MOSFEI39 Mname drain gate source body type wltwidthgt Lltlengthgt ASltarea sourcegt AD ltarea draingt PSltperimeter sourcegt PDltperimeter draingt ECEN 454 Lecture 6 12 Transient Analysis invsp Parameters and models 82 param SUPPLY18 a option scale90n y include 39modelstsmc180modelssp39 temp 70 42 option post Simulation netlist Vdd Vdd gnd 39SUPPLY39 Vin a gnd PULSE 0 39SUPPLY39 50ps Ops Ops 100ps 200ps M1 y a gnd gnd NMOS W4 L2 AS20 PS18 AD20 PD18 M2 y a vdd vdd PMOS W8 L2 AS40 PS26 AD40 PD26 tran lps 200ps end ECEN 454 Lecture 6 13 Transient Results 46 33 Unloaded inverter Overshoot We Very fast WV edges 1398 144 tf 10ps i V 1 0 i tpdf 12ps tpdr 15ps 5 tr16ps 036 39 00 V 00 50p 100p 150p 200p ECEN 454 Lecture 6 14 Subcircuits Declare common elements as subcircuits subckt inv a y N4 P8 M1 y a gnd gnd NMOS W39N39 L2 AS39N539 PS392N1039 AD39N539 PD392N1039 M2 y a vdd vdd PMOS W39P39 L2 AS39P539 PS392P1039 AD39P539 PD392P1039 ends EX Fanoutof 4 Inverter Delay D evnce I Reuse inv Under Load on Shapeinput Test Load Load Shaping l I l I I l Loading ECEN 454 Lecture 6 15 F04 Inverter Delay fo4sp Parameters and models param SUPPLY18 param H4 option scale90n include 39modelstsmo180modelssp39 temp 70 option post Subcircuits global vdd gnd include 39libinvsp39 Simulation netlist Vdd vdd gnd 39 SUPPLY 39 Vin a gnd PULSE 0 39SUPPLY39 Ops 100ps 100ps 500ps 1000ps X1 a b inv shape input waveform X2 b c inv M39H39 reshape input waveform ECEN 454 Lecture 6 16 F04 Inverter Delay Cont X3 c d X4 d e x5 e f tran 1ps 1000ps measure tpdr inv M39H239 device under test inv M39H339 load inv M39H439 load on load a ris ing prop delay TRIG v c VAL 39 SUPPLY239 FALL1 TARG v d VAL 39 SUPPLY2 39 RI SE1 measure tpdf falling prop delay TRIG v c VAL 39 SUPPLY2 39 RI SE1 TARG v d VAL 39 SUPPLY2 39 FALL1 measure tpd param39 tpdrtpdf 2 39 average prop delay measure trise rise time TRIG v d VAL 39 0 2 SUPPLY39 RISE1 TARG v d VAL 39 0 8SUPPLY39 RISE1 measure tfall fall time TRIG v d VAL 39 0 8SUPPLY39 FALL1 TARG v d VAL 39 0 2 SUPPLY39 FALL1 end ECEN 454 Lecture 6 17 F04 Results 20 E 1n 00 18 ECEN 454 Lecture 6 Optimization HSPICE can automatically adjust parameters Seek value that optimizes some measurement Example Best PN ratio We ve assumed 21 gives equal risefall delays But we see rise is actually slower than fall What PN ratio gives equal delays Strategies 1 run a bunch of sims with different P size 2 let HSPICE optimizer do it for us ECEN 454 Lecture 6 19 PN Optimization 7 fo4optsp Parameters and models param SUPPLY18 option scale90n include 39modelstsmc180modelssp39 temp 70 option post Subcircuits global vdd gnd include 39libinvsp39 Simulation netlist Vdd vdd gnd 39 SUPPLY 39 Vin a gnd PULSE 0 39SUPPLY39 Ops 100ps 100ps 500ps 1000ps X1 a b inv P39P139 shape input waveform X2 b c inv 39P139 M4 reshape input X3 c d inv P39P139 M16 device under test ECEN 454 Lecture 6 20 PN Optimization 7 X4 d e inv 39P139 M64 load X5 e f inv P39P139 M256 load on load Optimization setup param P1optrange8416 search from 4 to 16 guess 8 model optmod opt itropt30 maximum of 30 iterations measure bestratio param39P1439 compute best PN ratio tran 1ps 1000ps SWEEP OPTIMIZEoptrange RESULTSdiff MDDELoptmod measure tpdr rising propagation delay TRIG v c VAL 39 SUPPLY2 39 FALL1 TARG v d VAL 39 SUPPLY2 39 RI SE1 measure tpdf falling propagation delay TRIG v c VAL 39 SUPPLY2 39 RI SE1 TARG v d VAL 39 SUPPLY2 39 FALL1 measure tpd param39tpdrtpdf239 goal0 average prop delay measure diff param39tpdr tpdf39 goal 0 diff between delays end ECEN 454 Lecture 6 21 P N Results PN ratio for equal delay is 361 tpd tIDGIr tIDGIf 84 ps slower than 21 ratio Big pMOS transistors waste power too Seldom design for exactly equal delays What ratio gives lowest average delay tran lps 1000p s SWEEP OPTIMIZEoptrange RESULTStpd MODELoptmod PN ratio of 141 tIDGIr 87 ps tIDGIf 59 ps tpd 73 ps ECEN 454 Lecture 6 22 Power Measurement HSPICE can measure power Instantaneous Pt Or average P over some interval print Pvdd measure pwr AVG Pvdd FROMOns TO10ns Power in single gate Connect to separate VDD supply Be careful about input power ECEN 454 Lecture 6 23 Device Models include file containing transistor models Level 1 2 3 historically important inadequate now BSIM model Berkeley ShortChannel IGFET Model Version 1 2 3v3 and 4 gt level 13 39 49 and 54 ECEN 454 Lecture 6 24 Monte Carlo Simulation param dxlaunif 0 12 5nm dvthnagauss 0 16 8m 1 dvthpagauss 0 14 6m 1 tran 1ps 1000ps SWEEP MONTE100 The measure cards report average minimum and standard deviation ECEN 454 Lecture 6 25 ECEN 454 Digital Integrated Circuit Design Lecture 8 Logical E ort and Gate Sizing 2 ECEN 454 Lecture 8 Introduction Chip designers face a bewildering array of choices What is the best circuit topology for a function How many stages of logic give least delay How wide should the transistors be Logical effort is a method to make these decisions Uses a simple model of delay 9 9 Allows backof theenvelope calculations quot Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries ll ECEN 454 Lecture 8 2 Delay in a Logic Gate Express delays in processindependent unit d dabs r 3RC 2 z 12 ps in 180 nm process 40 ps in 06 pm process ECEN 454 Lecture 8 3 Delay in a Logic Gate Express delays in processindependent unit T Delay has two components dfp ECEN 454 Lecture 8 Delay in a Logic Gate Express delays in processindependent unit T Delay has two components dfp Effort delay f gh aka stage effort Again has two components ECEN 454 Lecture 8 Delay In a Logic Gate Express delays in processindependent unit d 2 239 Delay has two components dfp Effort delay f gh aka stage effort Again has two components g logcal effort Measures relative ability of gate to deliver current gs 1 for inverter ECEN 454 Lecture 8 Delay In a Logic Gate Express delays in processindependent unit d dubs T Delay has two components dfp Effort delay f gh aka stage effort Again has two components h eectn39ca effort Cout Cin Ratio of output to input capacitance Sometimes called fanout ECEN 454 Lecture 8 Delay In a Logic Gate Express delays in processindependent unit d dubs T Delay has two components dfp Parasitic delay 0 Represents delay of gate driving no load Set by internal parasitic capacitance ECEN 454 Lecture 8 Delay Plots 0 2 input NAND fp ghp Q39CCQ NormalizedDelayd Inverter Q39CCQ I I I I 2 3 4 ElectricalEffort h Cout Cin ECEN 454 Lecture 8 I 5 4 Delay Plots 0 f 2 input h D 6 NAND Inverter g p U 9 43 a g 243h 2 i E r What about NOR2 E g 2 EffortDelayf 1 1 Parasitic Delay p 0 I I I I I 0 1 2 3 4 5 ElectricalEffort h Cout Cin ECEN 454 Lecture 8 10 Computing Logical Effort ECEN 454 Lecture 8 DEF Logical effort is the ratio of the Input capaCtance of a gate to the input capaCtance of an inverter deliver77g the same output current 5 Measure from delay vs fanout plots i2 Or estimate by counting transistor widths 44 11 Catalog of Gates Logical effort of common gates Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 43 53 63 n23 NOR 53 73 93 2n13 Tristate mux 2 2 2 2 2 XOR XNOR 4 4 6 12 6 8 16 16 8 ECEN 454 Lecture 8 Catalog of Gates Parasitic delay of common gates In multiples of pmv1 Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 2 3 4 n NOR 2 3 4 n Tristate mux 2 4 6 8 2n XOR XNOR 4 6 8 ECEN 454 Lecture 8 Example Ring Oscillator Estimate the frequency of an Nstage ring oscillator W o o o W Logical Effort 9 Electrical Effort h Parasitic Delay p Stage Delay cl Frequency fosc ECEN 454 Lecture 8 14 Example Ring Oscillator Estimate the frequency of an Nstage ring oscillator 31 stage ring oscillator in Logical Effort 9 1 06 um process has Electrical Effort h 1 frequency of 200 MHz Parasitic Delay p 1 Stage Delay cl 2 Frequency fosc 12Nd 14N ECEN 454 Lecture 8 15 Example F04 Inverter Estimate the delay of a fanoutof 4 F04 inverter d H H Logical Effort 9 Electrical Effort h Parasitic Delay p Stage Delay cl ECEN 454 Lecture 8 16 Example F04 Inverter Estimate the delay of a fanoutof 4 F04 inverter Hi Logical Effort Electrical Effort Parasitic Delay Stage Delay U1I Lgt I The F04 delay is about 200 ps in 06 pm process 60 ps in a 180 nm process Q39U IO N f3 ns in an f pm process ECEN 454 Lecture 8 17 Multistage Logic Networks 1 Logical effort generalizes to multistage networks Pat7 Logta Effort G H g 39 39 Cout ath Pat7 Eectnca Effort H p inpath 33v Pat7 EffO l F H H gihi e R p D y z 20 911 9253 g343 g41 I h1 x10 h2 yx h3 zy h4 20z ECEN 454 Lecture 8 18 Multistage Logic Networks Logical effort generalizes to multistage networks Pat7 Logta Effort G H g 39 39 Coul alh Pat7 Eectnca Effort H P in palh Pat7 E rort F Hgihi Can we write F GH ECEN 454 Lecture 8 19 Paths that Branch tea2 No Consider paths that branch DIG l L 39I39IZTZT N ECEN 454 Lecture 8 Paths that Branch No Consider paths that branch G 1 H 90518 GH 18 h1 151556 l h2 90 15 6 F glgzhlh2 36 2GH ECEN 454 Lecture 8 21 Branching Effort Introduce branch77g effort Accounts for branching between stages in path C Coff path b on path C on path Note 3 b I H z Hh BH Now we compute the path effort F GBH ECEN 454 Lecture 8 22 Multistage Delays 3 Path Effort Delay DF Path Parasitic Delay P 219 4 gt Path Delay D Zdi DF P ECEN 454 Lecture 8 23 Designing Fast Circuits 026413 P Delay is smallest when each stage bears same effort lt3 J I gihi F Thus minimum delay of N stage path is D NFf P This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes ECEN 454 Lecture 8 24 Gate Sizes How wide should the gates be for least delay A Cour f gh gC m C gt g1 Aoutl f ml Working backward apply capacitance transformation to find input capacitance of each gate given load it drives Check work by verifying input cap spec is met ECEN 454 Lecture 8 25 Example 3stage path Al 23v Select gate sizes X and y for least delay from A to B 3 Y 45 1E x Y B ECEN 454 Lecture 8 26 Example 3stage path Logical Effort Electrical Effort G H Branching Effort B Path Effort If Best Stage Effort f Parasitic Delay P Delay ECEN 454 Lecture 8 27 Example 3stage path jD45 A v 3 39 1 Logical Effort G 435353 10027 Electrical Effort H 458 Branching Effort B 3 2 6 Path Effort If GBH 125 Best Stage Effort f F 5 Parasitic Delay P 2 3 2 7 Delay D 35 7 22 44 F04 ECEN 454 Lecture 8 28 Example 3stage path at Work backward for sizes y X y E45 AjS X y B 1v U ECEN 454 Lecture 8 29 Example 3stage path 322 Work backward for sizes y4553515 x 152 53 5 10 ECEN 454 Lecture 8 30 Best Number of Stages sf How many stages should a path use Minimizing number of stages is not always fastest Example drive 64bit datapath with unit inverter lnitialDriver DatapathLoad 64 64 64 64 25 1 1739 1 4 N 1 2 3 f D ECEN 454 Lecture 8 31 Best Number of Stages How many stages should a path use Minimizing number of stages is not always fastest Example drive 64bit datapath with unit inverter lnitialDriver v v D NFlN P N641N N gm E64 3764 a a 8 is Fastest ECEN 454 Lecture 8 32 Derivation Ax 2933 Consider adding inverters to end of path How many give least delay L BI K Nn1Extralnverters o n1 nggicag gt o o 0 Path EffortF DNF piN nlp 1 i1 8 D Ff1an Ff pmv 0 W Define best stage effort 0 F pmvp11np0 ECEN 454 Lecture 8 33 Best Stage Effort PM 101 1n0 0 has no closedform solution Neglecting parasitics pinV O we find p 2718 e For pinV 1 solve numerically for p 359 ECEN 454 Lecture 8 34 Sensitivity Analysis E How sensitive is delay to using exactly the best number of stages g lt5 10 24 lt p lt 6 gives delay within 15 of optimal We can be sloppy I I p 4 ECEN 454 Lecture 8 35 Example Ben Bitdiddle is the memory designer for the Motoroil 68W86 an embedded automotive processor Help Ben design the decoder for a register file Decoder specifications 16 word register file Each word is 32 bits wide Each bit presents load of 3 unitsized transistors True and complementary address inputs A30 Each input may drive 10 unitsized transistors Ben needs to decide m m How many stages to use i i How large should each gate be How fast can decoder operate 32 bits Register File Jepooeo 9L l7 ECEN 454 Lecture 8 36 Number of Stages Decoder effort is mainly electrical and branching Electrical Effort H Branching Effort B If we neglect logical effort assume G 1 Path Effort F Number of Stages N ECEN 454 Lecture 8 37 Number of Stages e Decoder effort is mainly electrical and branching Electrical Effort H 323 10 96 Branching Effort B 8 If we neglect logical effort assume G 1 Path Effort F GBH 768 Number of Stages N log4F 31 Try a 3stage design ECEN 454 Lecture 8 38 Gate Sizes amp Delay E Logical Effort G Path Effort FA Stage Effort f 2 Path Delay D Gate sizesz y A3 W A2 m A1 W A0 W ECEN 454 Lecture 8 39 Gate Sizes amp Delay Logical Effort G 1 63 1 2 Path Effort FA GBH 154 Stage Effort f F113 536 PathDeIay D3f141221 Gate sizesz 961536 18 y 182536 67 A3 W A2 m A1 W A0 W W0 rd 0 96 units of wordline capacitance word15 ECEN 454 Lecture 8 40 Comparison Compare many alternatives with a spreadsheet Design N G P D NAND4INV 2 2 5 298 NANDZNORZ 2 209 4 301 INVNAND4INV 3 2 6 221 NAND4INVINVINV 4 2 7 211 NANDZ NORZ INV INV 4 209 6 205 NANDZINVNANDZINV 4 169 6 197 INV NANDZ INV NANDZ INV 5 169 7 204 NANDZINVNAND2INVINVINV 6 169 8 216 ECEN 454 Lecture 8 41 Review of Definitions Term Stage Path number of stages 1 N logical effort g G ng electrical effort h 2 H 2 branching effort b C 39pg fpam B 2 H bi effort f gh F GBH effort delay f DF Zfi parasitic delay p P Zpi delay dfp DZdizDFP ECEN 454 Lecture 8 42 Method of Logical Effort 1 Compute path effort F GBH 2 Estimate best number of stages N 10g4 F 3 Sketch path with N stages 1 4 Estimate least delay D NF P 5 Determine best stage effort Ff giCom 6 Find gate sizes Cmi ECEN 454 Lecture 8 43 Logical Effort from SPICE Logical effort can be measured from simulation As with FO4 inverter shape input load output Dech Under Load on Shape input Test Load Load I I ECEN 454 Lecture 8 44 Logical Effort Plots PIOt tpd VS h Normalize by r yintercept is parasitic delay Slope is logical effort 115ps 160 140 120 d 100 Delay fits straight line abs very well in any process as long as input slope is 40 20 conSIstent ECEN 454 Lecture 8 45 Logical Effort Data For NAND gates in TSMC 180 nm process 2 A 145 082 114 237 142 B 136 097 117 160 122 3 I 182 080 131 490 211 B 173 095 134 394 136 C 163 110 136 260 151 4 A 196 089 142 654 308 B 186 102 144 571 284 C 180 114 147 469 2 l2 D 171 128 149 326 197 Notes Parasitic delay is greater for outer input Average logical effort is better than estimated ECEN 454 Lecture 8 46 Limits of Logical Effort Chicken and egg problem Need path to compute G But don t know number of stages without G Simplistic delay model Neglects input rise time effects Interconnect Iteration required in designs with wire Maximum speed only Not minimum areapower for constrained delay ECEN 454 Lecture 8 47 Summary of Logical Effort Logical effort is useful for thinking of delay in circuits Numeric logical effort characterizes gates NANDs are faster than NORs in CMOS Paths are fastest when effort delays are 4 Path delay is weakly sensitive to stages sizes But using fewer stages doesn t mean faster paths Delay of path is about log4F FO4 inverter delays Inverters and NANDZ best for driving large caps Provides language for discussing fast circuits But requires practice to master ECEN 454 Lecture 8 48 Cascaded Inverters v w p stage ratio sizei1 p o sizei a K1IF3 EICH1ID ECEN 454 Lecture 8 49 Delay of Cascaded Drivers Delay between stage i and i1 Ri39Ci1339Ri39Ci Total delay from stage 1 to stage k pR1C1 pRZC2 ka1Ck1 chL pRlC1 pR1C1 pR1C1 RlCL PM k1PR1C1 RICL Pkquot1 ECEN 454 Lecture 8 50 Minimum Delay Stage Ratio A k10R10C1 B RlcCL t Acp Bp1k Let derivative t O A 1koBop39k 0 pk k 1oBA CL CL I3 CL 311k 1 m ECEN 454 Lecture 8 51 Optimal Number of Stages CL C1 Pk k nCLC1 In p t kopoRlocl In CLC1 In D 1pR1C1 Delayt reaches minimum when p 272 ECEN 454 Lecture 8 52