Introduction to Digital Integrated Circuits
Introduction to Digital Integrated Circuits EL ENG 141
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This 5 page Class Notes was uploaded by Kris Heathcote on Thursday October 22, 2015. The Class Notes belongs to EL ENG 141 at University of California - Berkeley taught by E. Alon in Fall. Since its upload, it has received 60 views. For similar materials see /class/226757/el-eng-141-university-of-california-berkeley in Electrical Engineering at University of California - Berkeley.
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Date Created: 10/22/15
EE14 fFal 2008 Digitd Integrated O39muils MOS Capacitance Lecture 10 M08 Capacitance EE 1 i H mm 4 E M i m wt 6 Announcements Mos Capacitances G u Homework 5 due Thursday Humewurk E uutnext WEE u Midterm 1 Tues Oct 7 630800pm in 105 North ate Midterm review sessiun Munday Mamiipm Krueberi i n This Thursda 39s lecture moved to Fri 3 430pm 521 o Eiad s Th affine huurs muvedtu Fri 4 EELS B pm E5 151 Lamina EEc m gamma 67555 Material Gale Capacitance in Last lecture MOS Transistor Model in Today s lecture MOS capacitance in Reading 332 mm i Capacitance per area from gate across the oxide is WL39Cm Where in emtnX FF m m m FF m Gate Capacitance ii Distribution between terminals is complex Capacitance is really distributed Useful models lump it to the terminals Several operating regions Way off off transistor linear transistor saturated EEcsm Lemum t 7 Dansstar in Linear Region Ts w L Tn Channel is formed and acts as the otherterminal Ct30E drops to zero shielded by channel Model by splitting oxide cap equally between source and drain Changing either voltage changes the channel charge EECSTM Le utE MU 70 Transistor In Cutoff Isiri 1 When the transistor is off no carriers in channel to form the other side of the capacitor Substrate acts as the other capacitor terminal Capacitance becomes series combination ofgate oxide and depletion capacitance 7 Email Lammem x Transistor in Saturation Region 15 W i 1 Co CE CDL C ClSE Q C u j Changing source voltage doesn t change VGC uniform y Eg VGO at pinch off point still VTH Bottom line CGCS 23WLC0X V EECSlAl Lecture l ll Transistor In Cutoffmnm s n l l on CW out I 955T l qua When VGS lt VT total CGCB much smallerthan WLCOX Usuallyjust approximate with CGCE 0 in this region If VGS is very negative for NMOS depletion region shrinks and CGCB goes back to WLCOX EECSMi Lecture 10 9 Transistor in Saturation Region mm l s w n Icu T C39SE r LLT CD u Drain voltage no longer affects channel charge Set by source and VDSsat If change in charge is 0 CGCD 0 EEcSMi Lecture 10 12 Gate Capacitance NUS l 1115711 In gate VS VGs Cg e vs operating region with vDS 0 512625141 Lgctunetttoi 13 Diffusion Capacitance Bottom Area cap Cbottom Cj39Ls39W Sidewalls Perimeter cap L Csw stw2L8W S Submjf GateEdge Cge ngate39W Usually automatically included in the SPICE model EEQSLl 41 Lectung io 16 Gate Overlap Capacitance Polysilicon gate Gate oxide tax I L Cross section Topview C0Cxxd 0 OffLinSat a cGSO CGDO cow 51295441 Lactate 19 14 Junction Capacitance 2 Junction caps are nonlinear CJ isa function of junction bias Canaclznm izhnmy un vs SPICE model equations Area CJ area gtlt 0J0 1 VDBI BW Perimeter CJ perim gtlt CJSWi VDB BW5W Gate edge CJ W x CMe 1 VDBlt1gtBWSW9 nn n2 no ns us in MndevnllngM How do we deal with nonlinear capacitance EEQSJ 41 Lactlimi il 17 Gate Fringe Capacitance Fringing fields Cross section COV notjust from metallurgic overlap get fringing fields too Typical value O2fFWin umedge EE051 41 Linearizing the Junction Capacitance Replace nonlinear capacitance by largesignal equivalent linear capacitance which displaces equal charge over voltage swing of interest g QJltVmgigteojltViawgt C K C0 24 AVD Vmgh Vtaw 24 J m Keg WK to lmg l m i o ViaWY39ml EECSl 41 Capacitance Model Summary El GateChannel Capacitance CGC 0 I CGC Cox39W39Ieff 50GtoS 50GtoD 39 CGC 2339Cox39W39Ieff 100 G to s IVGSI lt IVTI Linear Saturation El Gate Overlap Capacitance 39 CGSO CGDO Co39W Always El JunctionDiffusion Capacitance cdiff cjLSw stwZLS W cjgw Always EEC3141 Lecture10 19 Model Calibration Capacitance Can calculate Cg Cd based on tech parameters But these models are simpli ed too Another approach Tune eg in spice the linear capacitance until it makes the simpli ed circuit match the real circuit Matching could be for delay power etc Cload Dela 1 Delay2 ygt Match EEQS141 Lecture 10 22 Capacitances in 025pm CMOS Process Co 2 Co 9 2 my 15 CW mm m fFllm fFllm fFllm V fFllm V NMOS 5 031 2 05 09 028 044 09 PMOS 5 027 19 048 09 022 0 32 09 EECSJ 41 Lecture 10 20 Model Calibration for Delay V39 b39 Iquot V Dela 1 Delay2 ltygt Match Forgate capacitance Make inverter fanout 4 Adjust Cload until Delay1 Delay2 For diffusion capacitance Cload Simpli ed Model Capacitance models important for analysis and intuition But often need something simpler to work with Simpler model Lump together as effective linear capacitance to ac ground In most processes CG CD 15 2fFWum EECS I 41 Lecture 10 21 Replace inverter A with a diffusion capacitance load EEQSl41 Lecture10 23 Delay Calibration 1 4 16 64 lt gt T T T quotEdge Shaperquot Load 7 Why did we need that last inverter stage EEQSl41 Lecture10 24 The Milw Effect As Vm increases VElm drops 7 Once get H ito the transition region 98m from tho m gt1 0 Can experiences voltage swing S largerthan Vm 7 Which means you need to provide more har e c g 7 Makes cEm iook iargerthan it reaiiy i5 Knovm as the Miller Effect in the analog world EECSW Le ure w Next l ecture VTCs and Delay revisited Ladmem 0 7 EEcsm