Introduction to Digital Integrated Circuits
Introduction to Digital Integrated Circuits EL ENG 141
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This 15 page Class Notes was uploaded by Kris Heathcote on Thursday October 22, 2015. The Class Notes belongs to EL ENG 141 at University of California - Berkeley taught by Staff in Fall. Since its upload, it has received 26 views. For similar materials see /class/226759/el-eng-141-university-of-california-berkeley in Electrical Engineering at University of California - Berkeley.
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Date Created: 10/22/15
EE141 Spring 2005 Lecture 2 Design Metrics EEMi Last Lecture o Moore s law 0 Challenges in digital IC design in the next decade Today 0 Design metrics EEMH Administrivia EEMl 0 Everyone should have a UNIX account on Cory This will allow you to run HSPICE gtgt If not check httpAvwwinsteecsberkeleyeduusrpubjpgHowtoGet NamedAcctij PC accounts for 353 Cory will be created early next week when the cassist is completed Discussions start in Week 2 Labs start in Week 3 lfyou have not signedin on the class roster please do so afterthe lecture Design Metrics o How to evaluate EElM performance of a digital circuit gate block Cost Reliability Scalability Speed delay operating frequency Power dissipation Energy to perform a function Cost of Integrated Circuits o NRE nonrecurrent engineering costs design time and effort mask generation onetime cost factor 0 Recurrent costs silicon processing packaging test proportional to volume proportional to chip area EEMl NRE Cost is Increasing Mm Cam we p 8 ex 02 mi in Process Geomhleemnl 7011111 ASICs will have 4M wwwmwmmzmiunnmm 1 mm mm mewr EElM Die Cost Single die cost of Wafer cost of die dles per Waferdle yleld Wafer Going up to 12 30cm mm http www amd Com 7 EE1A1 Cost per Transistor cost pertransistor 1 Fabrication capital cost per transistor Moore s law 01 001 0001 00001 000001 0000001 00000001 L 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012 EE1A1 Total Cost 0 Variable cost cost of die cost of die test cost of packaging variable cost I I final test yield 0 Cost per IC COSt per 1C variable cost per 1C M volume EEMW 9 Yield N0 of good chms per wafer X 100 Total number of ch1ps per wafer Wafer cost D1e cost D1es per waferX D1e y1eld 11 X wafer diameter22 11 X wafer diameter D1es per wafer d1e area x2 X d1e area quot EEMW Defects EE141 die yield 1 defects per unit area x die area or jam or m 3 complexity of mfg process defects per unit area 05 to 1 cm2 die cost fdie area4 Some Examples 1 994 Chip Metal Line Wafer Def Area Dies Yield Die layers width cost cm2 mm2 wafer cost 386DX 2 090 900 10 43 360 71 4 486 DX2 3 080 1200 10 81 181 54 12 galler PC 4 080 1700 13 121 115 28 53 HP PA 7100 3 080 1300 10 196 66 27 73 DEC Alpha 3 070 1500 12 234 53 19 149 Super Spare 3 070 1700 16 256 48 13 272 Pentium 3 080 1500 15 296 40 9 417 EE141 Reliability Noise in Digital Integrated Circuits VU A Von T 1V W 1 E Inductive coupling Capacitive coupling Power and ground noise P EEMW DC Operation Voltage Transfer Characteristic Vout VOH fVOL VOL fVOH VM fVM quot39VoutVin VOH Vin Nominal Voltage Levels EEMH Mapping between analog and digital signals H 1 H V Vout OH V Slope 1 V OH lH Undefined Region VL V 0 VOL OL EEMW Definition of Noise Margins v OH NOIse margln hlgh H Undefined Region 39 v VOL IL NOIse margln low quot0 GateOutput gt Gatelnput EElM Noise Budget o Allocates gross noise margin to expected sources of noise 0 Sources supply noise cross talk interference offset 0 Differentiate between fixed and proportional noise sources EEMl 17 Key Reliability Properties 0 Absolute noise margin values are deceptive a oating node is more easily disturbed than a node driven by a low impedance in terms of voltage 0 Noise immunity is the more important metric the capability to suppress noise sources 0 Key metrics Noise transfer functions Output impedance of the driver and input impedance ofthe receiver EElAl 18 Regenerative Property v7 v m Regenerative mm 19 Regenerative Property Simulated response 1 4 u x n mm mm 20 Fanin and Fanout N M Fanout N Fanin M The Ideal Gate Vout Ri 00 RC 0 Fanout 00 9 00 NMHNMLVDD2 EEMH An Oldtime Inverter EEm Performance Delay Definitions EEiM 24 Technology Characterization Ring Oscillator for tp EEW 25 A FirstOrder RC Network v e v MU 1 6 V tp In 2 r 069 RC Important model matches delay of inverter EEW 26 Power Dissipation Instantaneous power Vruppl t Peak power Ppeak Vsupplylpeak Average power 1 tT Vsupply tT Pave J ptdt lsupply tdt EEW Z7 Energy and EnergyDelay Power Delay Product PDP E Energy per operation PM X If Energy Delay Product EDP quality metric of gate E X If EEW 28 A FirstOrder RC Network Vout LCL Vdd T T 2 E0H 1P0 VddIlsupplytdt Vdd I CLdVout CL Vdd o o o T T Vdd 1 2 Ecap Pcaptdt Voutlcaptdt I CLlethout 7C 0V 0 0 0 2L dd EEMH Next Lecture 0 Manufacturing Technology EEMH
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