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ProjectComputer Architecture

by: Jacey Olson

ProjectComputer Architecture CSE 141L

Jacey Olson

GPA 3.69

Steven Swanson

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Steven Swanson
Class Notes
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This 9 page Class Notes was uploaded by Jacey Olson on Thursday October 22, 2015. The Class Notes belongs to CSE 141L at University of California - San Diego taught by Steven Swanson in Fall. Since its upload, it has received 19 views. For similar materials see /class/226787/cse-141l-university-of-california-san-diego in Computer Science and Engineering at University of California - San Diego.

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Date Created: 10/22/15
A Brief Intro to Verilog Brought to you by Sat Garcia 11 Meet your 141 L TA I Sat Garcia Esatcsucsdedu D2 Year PhD Student 60ffice Hours Tentative Place EBU3b 8225 basement Monday 34pm Wednesday 11amNoon Please come to my office hours get lonely there by myself What is Verilog I Verilog is A hardware design language HDL Tool for specifying hardware circuits Syntactically a lot like C or Java An alternative to VHDL and more widely used What you39ll be using in 141L HELLA COOL If you are totally into hardware design languag39 s Verilog in the Design Process Behavioral Test II gt Manual R t 1 Simulate Test egls er 39 Transfer Level Logic Synthesis Simulate Test Gate Level I Auto Place Route 1 Adapted from Arvind amp Asanovic s MIT 6375 lecture 4 39 Ways To Use Verilog I Structural Level Lower level I Has all the details in it which gates to use etc ls always synthesizable I Functional Level Higher Level I Easierto write 39 Gate level RTL level highlevel behavioral Not always synthesizable I We ll be sticking with functional mostly 1 Data Types in Verilog I Basic type bit vector Values 0 1 X don39t care Z high impedence I Bit vectors expressed in multiple ways binary 439b1110 is just for readability hex 1639h034f decimal 3239d270 other formats but these are the most useful 39 Data types continued I Connect things together with wire Single wire I Wire myWIre Array of wires I wire70 mywire I Why not wire07 I For procedural assignments we39ll use reg Again can either have a single reg or an array I reg30 accum 4 bit reg reg is not necessarily a hardware register 39 Iquot A simple example comb circuit I Let39s design a 1 bit full adder a b i i module FAnputa b cin cin outputs cout assignsaquotbquotc Gout FA assign cout a amp b a amp cin b amp cin lt7 endmodule iS Note red means new concept blue and green are just pretty colors p Ok but what if we want more than 1 bit FA Adapted from Arvind amp Asanovic s MIT 6375 lecture 8 i A 4bit Full Adder I We can use 1 bit FA to build a 4 bit full adder module 4bitFA Input 30 A B input cin output 30 8 output cout wire c0 c1 c2 FA fa0A0B0cinS0c0 implicit binding FA fa l aA l bB l cinc0 sS l coutc l explicit binding FA fa2A2B2c1S2c2 FA fa3A3B3c2S3cout endmodule Adapted from Arvind amp Asanovic39s MIT 6375 lecture a Testing the adder timescale 1ns1ns Add this to the top of your file to set time scale module testbench reg 30 A B reg CO wire 30 8 wire C4 4bitFA uut BB AA cinCO 68 coutC4 instantiate adder initial initial blocks run only at the beginning of simulation only use in testbenches begin monitortimequotA obBb cinb coutb sum obnquotABCOC4S end initial begin A 439d0 B 439d0 CO 139b0 50 A 439d3 B 439d4 wait 50 ns before next assignment 50 A 439b0001 B 439b0010 don t use n outside of testbenches end endmodule Verilog RTL Operators Arithmetic 95 Reduction 1 39 39 A Logical ampamp Shift gtgt ltlt gtgtgt ltltlt Relational gt lt gt lt Concatenation Equality 7 Conditional Bitwise amp I A A I Avoid using and because you39ll run into problems when trying to synthesis Adapted from Arvind amp Asanovic39s MIT 6375 lecture 11 A simple D flip flop seq circuit I For sequential circuits use always blocks I Always blocks and assign are executed in parallel module DFF input clk d output q qbar reg q qbar always posedge clk triggered on the rising edge of the clock begin q lt d nonblocking assignment LHS not updated until later qbar lt d qbar lt q will not function correctly I end endmodule Adapted from Arvind amp Asanovic s MIT 6375 lecture 12 39 Always blocks in comb circuits I Can use continual assignment AND always blocks for combinational circuits I Our 1bit adder using always block module FA Input a b cin outputscou0 reg s cout when using always block LllS must be reg type always a or b or cin for comb circuits sensitive to ALL inputs bwm s a quot b quot cin use blocking assignment here LHS immediately cout aamp b a amp cin b amp cin em endmodule 39 Iquot Quick Note on blocking vs non blocking I Order of blocking statements matter 39 These are not the same cab39 dCe dce Ca b I Order of nonblocking statements doesn t These are the same cltab dltce dltce cltab I Use nonblocking with sequential blocking with combintational Tips for maintaining synthesizability I Only leaf modules should have functionality All other modules are strictly structural ie they only wire together submodules I Use only positiveedge triggered flipflops for state I Do not assign to the same variable from more than one always block I Separate combinational logic from sequential logic I Avoid loops like the plague Use for and while loops only for test benches Adapted from Arvind amp Asanovic39s MIT 6375 lecture Another Example 4 input MUX I we can use case module mux4 input a b c d statements within 354215 an always block regout always begin case sel 2 d0 out a default out 1 bx endcase end endmodule Adapted from Arvind amp Asanovic s MIT 6375 lecture Finite State Machines FSMs I Useful for designing many different types of circuits I 3 basic components Combinational logic next state Sequential logic store state Output logic I Different encodings for state Binary min FF s Gray One hot good for FPGA One cold etc A simple FSM in Verilog module simplefsm input clk start stanu output restart reg 10 state nextstate parameter 80 2 b00 81 2 b0 l 82 2 b10 always begin nextstatelogic case state 80 begin if start nextstate 81 else nextstate 80 continued from left 81 begin nextstate 82 end 82 begin if restart nextstate 80 else nextstate 82 always posedge clk begin stateassignment state lt nextstate end end default nextstate 80 endmOdule endcase end continued to the right


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