ProjectComputer Architecture CSE 141L
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This 9 page Class Notes was uploaded by Jacey Olson on Thursday October 22, 2015. The Class Notes belongs to CSE 141L at University of California - San Diego taught by Staff in Fall. Since its upload, it has received 56 views. For similar materials see /class/226797/cse-141l-university-of-california-san-diego in Computer Science and Engineering at University of California - San Diego.
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Date Created: 10/22/15
Week 6 Update CSE 141L November 7 2008 Announcements Lab 2 Part B was due today Go over answers today Lab 3 PartA due in 1 week Create datapath of exec unit Based on your ISA anyone not have one Work with your partner on this Tracking progress How to track time in CPU Q How can tell when X cycles have passed since signal Y was asserted A Xflipflops in a row Ioadstorevalid Test testbench E vestevLaddv mstvucttoerahd mstvucttorLdata d data stovejata deque een oadjtovegahd Is a fetch unit affected by load or store operations How do we tell Ioadstorevalidr Ioaddataready Branch Testbench tnstruc oeraHd tnstruc orLdata tnstructtonjddr Sigma e V t Note how instructionvaid changes VS branch addr instruction 0 nonbranchiopo 1 nonbranchiopt 2 conditional branch to 7 predicted taken 3 nonbranchiopa 4 nonbranchiop4 5 nonbranchiop5 6 nonbranchiops 7 branch to 0 Custom Test bench tnstmcttomvand tnstruc orLdata tnstruc orLaddr deque restart restarLaddr storaen roadjtoreJaHd smegma roadjtorejddr Simultaneously assert restart from 0x10 store OXDEAD at 0x10 Implementation Result 0 My results from Xilinx 91 5517ns Cycle Time 181 26MHz Quick Poll Who got a better result The Critical Path Before we move on to Lab 3 Any questions Back to the Future 141 L Edition Creating a Core Core ties together fetchunit and execunit lnstantiate one of each of these in the core module module coreparameter DWDTH 34 PAWDTH 4 input ck input reset ll IIO interface output inreq outputoutre output PAWDTH1 0 inaddr output PAWDTH1 0 outaddr input DWDTH1 0 indata output DWDTH1 0 outdata input inack input outack Backend Components Register File Data Memory Separate from instruction memory Misc logic components ALU Sign extender MUX VWI be leaf modules to be instantiated in backend Register File Read combinational logic Write sequential logic flipflops Sample interface we writeisel Easily implemented by using din 4 readisel regfile 4 dout Data Memory Use CORE Generator Optimized implementation Initialize with your c oe file 8K addresses 34bit words Tutorial is available on class website Wrapper Provides general interface Read XOR Write refused signal Must try req again readiwriteireq writ addr eien din V clout 4 Wrapper refused The Backend Datapath we writeisel din regfile d readisel 0 readiwriteireq 1 wn eien dout Generated i addr Ram Modue din 39 refusec Wrapper inireq oqueq iniaddr 30 ouLaddr 30 inidata 330 Backend ouLdata 330 iniack ouLack clock cycle mack O mack 1 in Imeq lt 1 reght lt din Iniaddrlt channe Wn39 competes outiack 0 outiack 1 ut 1 OUt outjddr lt channe out39 competes Single Multi or Pipelined It s up to you to decide Tradeoffs a 141 review Single Multi Pipelined Part A Deliverables Leaf Modules Reg File Data Mem etc Implemented with RTL Verilog Execution Unit Datapath Implemented with structural Verilog Datapath Schematic Do NOT use Xilinx schematic generator Explain how instructions go through the datapath
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