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Crime And Society

by: Ernestine Rowe

Crime And Society SOCC 141

Ernestine Rowe

GPA 3.83


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Class Notes
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This 9 page Class Notes was uploaded by Ernestine Rowe on Thursday October 22, 2015. The Class Notes belongs to SOCC 141 at University of California - San Diego taught by Staff in Fall. Since its upload, it has received 28 views. For similar materials see /class/226812/socc-141-university-of-california-san-diego in social psychology at University of California - San Diego.

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Date Created: 10/22/15
Week 3 Status Update CSE 141L Oct 17 2008 Announcements No office hours today go to Y Hack Week stuff Lab 2 Part B is now available Due in 2 weeks Oct 31 scaaary Fetch unit control and testing Need to pick partners Email me members and team name by next Friday or Lab 1 grades are coming soon Most people did very well Why pcprevr Ioa d avgslid with IT Question 5 Cycle 0 Control 39mEW iniq n39qub f load r smug mm mm m M Question 5 Cycle 1 Question 5 Cycle 2 Control 13331 Luna momma 39 fQiGLieaVquot Question 5 Cycle 3 Question 5 Cycle 4 Control 13331 Luna momma 39 fQiGLieaVquot Question 5 Cycle 5 Question 5 Cycle 6 Control 13331 Luna momma 39 fQiGLieaVquot Question 5 Cycle 7 Control s efnu39x3 DI Verilog Refactoring adderv module addeer parameter WIDTH32 input WIDTH 10 dino input wm 0 din1 output WIDTH 10 dout reg WIDTH 10 outReg wire doutw outReg assign dout doutw always a e i g n outReg dinO dinl en endmodule module adder parameter WIDTH32 input WIDTH 10 dino input WIDTH 10 din1 output WIDTH 10 dout assign dout dinO dini endmodule Simplify if possible Ports are already wires Verilog Refactoring muxv module mymux parameter WIDTH1 0 input se1 input WIDTH10 dinO module mymuxparameter mun110 input WIDTH10 din1 output WIDTH10 dout input input WIDTH10 dino input WIDTH 01 din1 reg WIDTH10 reginoregin1 output WIDTH1O dent reg WIDTH10 regout gt assign dout regout assign dout sel din1 dino a1ways begin endmodule casese1 1de regout ltregino 139d1 regout ltregin1 endcase Avoid lt in combinational logic and always begin regin1ltdin1 reginoltdino end endmodule Before we move on Any other questions about part A stuff Lab 2 Part 2 Overview 4 Steps Implement Control for Fetch Unit Use given test benches Create your own test bench Performance evaluation Keep your Verilog code as clean as possible Step 1 Control Unit Webpage fully specifies behavior of control unit Three types of signals Input eg restart loadstorevalid Internal eg selmux fifoclear Output instrvalid loaddatavalid Subtle point Restart should clear FIFO on the next cycle regardless of preemption Why Testing your Fetch Unit We give you two testbenches Simple restartdequeueload example Branchinglooping program You will need to create one testbench on your own Test simultaneous restart and loadstore Can use the GUI TB editor or do it manually Manual Testbenoh Setup timescale 1ns1ns Add this tothe top ofyour le to set time scale module testbench reg 30 A B reg CO wire 30 S wire C4 4bitFA uut BB AA cinCO SS coutC4 instantiate adder initial initial blocks run only at the beginning of simulation only use in testbenches egin monitortimequotAbBb cinb coutb sum bnquotABCOC4S initial begin A 439d0 B 439d0 CO 139b0 50 A 439d3 B 439d4 wait 50 ns before next assignment 50 A 439b0001 B 439b0010 don t use n outside of testbenches end endmodule 18


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