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by: Mattie Schmidt


Mattie Schmidt
GPA 3.83


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This 109 page Class Notes was uploaded by Mattie Schmidt on Thursday October 22, 2015. The Class Notes belongs to GLOBL 124 at University of California Santa Barbara taught by Staff in Fall. Since its upload, it has received 82 views. For similar materials see /class/226844/globl-124-university-of-california-santa-barbara in Global Studies at University of California Santa Barbara.




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Date Created: 10/22/15
ECE 145C218 C notes set 10 ICs for Optical Transmission Mark Rodwell University of California Santa Barbara rodwelleceucsbedu 8058933244 8058933262 fax I98 l l quotMilliquot TI IlSIIliSSiIIII lollies Systems block diagrams eye diagrams waveforms Transmitters Laser diodes diode drivers Optical modulators modulator drivers Receivers Photodiodes Receiver block diagrams AGC and limitng AGC amplifier and detector SNR constraints on limiting amplifier design Limiting amplifiers TIA SNR analysis topologies DC restoration loops SNR analysis Personik Integrals Timing recovem PLLs phase detectors for data steams frequency locking Mux and Demux basic structures timing thereof ECEMSCZlBC mules M Rudw ell cupynghled 2008 highrate high ate serial bina data r gmTramquot electrical ry serialbmary data highrate serial 39bmary data optical data electrical 44 lowrate data 39 k W 3 optical pt ca g a transmitter receiver g g Jln I L o 5 E o E Typical form of optical link muX transmitter receiver demuX Motivation Copper wires have high losses at high frequencies see notes skin effect Optical bers have low losses 03 dBkm 1310 nm 017 dBkm 1550 nm Prevalent Mode of operation 2008 Digital transmission Binary Intensity Modulation On Off Incoherent power detection mucmcm M m momma Timioal Signal Formal nnz Modulation b b E 17gt To 7 a nu nr E 311 E 8E time time In each bit period Intensity is modulated high low to communicate 1 vs 0 sent Modulated intensity for quot0 is not quite zero P Extinction ratio P opumvo opncall Eye pattern represenm waveform vs time modulo one bit period Represenm data trajectories for all possible sequences segue215C notes M Rodwel coprrgmeaznoa li al Transmitter Ilirectlv Modulated laser IIiIIIIe G D 44 53 g gt I a E 3 B 5 z s t 3 2 lt1 3 c 2 E o g a 0 E 9 5 signal bias T3 voltage current Diode is driven by suA er osition of bias and AC drive current Diode shows a sharp increase in light output when drive current exceeds laser threshold P m E 7702 Vq 1 0P 77 quantum efficiency V 2 optical frequency in Hz Laser diode I V characteristics resemble those of a PN diode except that forward voltage increases only slowly once threshold current is exceeded ECE1A C215Jnotes M Rodwel coprrgnzeaznoa laser IliIIlIe characteristics relaxation tesonance modulation response gt frequency Laser small signal modulation reponse depends upon bias current Bandwidth increases as bias current increases then saturates collapses Response is 2nd order damping increases at high currents Few diode lasers exceed 25 GHZ bandwidth 2008 Undesired wavelength modulation chirp makes lasers less attractive for long range high speed links Though laser rate equations suggest a more compleX model laser electrical parameters are well approximated by an ideal diode in series with a small 5 10 Q series resistance ECE145C 218C notes M Rodwell copyrighted 2008 laser Transmitters monitor laser diode diode laser diode data modulation current DC bias from loop modulation current Basic Form sometimes uses DC feedback loop to maintain laser bias Monitor diode generally on laser backside DC loops not needed with modern low threshold lasers Laser amp driver are not on same die Interconnect is likely long and likely needs series padding RIM Rdiode ZO to control line ringing E CE 1450 218C notes M Rodwell copyrighted 2008 Z i dPabsorbed hv dV control DC bias voltage Electro Absorbion modulators A reverse biased PIN junction containing an optical waveguide in the I region Varying the reverse bias varies the optical attenuation Electrical model is that of a reverse biased diode but with a parallel resistance representing the absorbed light Device is loaded with a 50 Ohm parallel load and driven With combined DC bias and pulse train ECE7450Q7BC Holes M ROdWeH CopyIgmed 2008 I gt ZO ZU ZO 44 44 M l 44 m 70 gt 20 20 20 Interferometer split optical waveguide give paths a relative phase shift recombine Output optical E field intensity EM 2 E0 cosA Output optical power Pom oc E 02m PM 2 PM cos2A 2 PM 2l cos2A Electro optic Modulator Optical waveguide refractive index varies weakly with applied E eld Voltage induces optical phase shift changes output intensity P 2gt1 cosw Vgt V is 4 6 V for 40 Gbs modulators need high power driver ignal Ecgwscmac notes M Romet copyIgmed 2008 llrivers If lentoantic Modulators Combination of high bandwidth and high drive V I Nearly always a distributed amplifier InP HBT 0r InGaAsInP HEMT Single ended or differential ECE745027BC notes M Rodwel copyrighted 2008 ontical BEGEWEIS PIN Pll l lli lles f P 44 gt gt 174 N 1 N RS 4 7761 Iph h V Popl Reverse biased diode with illumination of I region 7761 I hV optical hVq20954Vatl13lOnm hVquBOOVatlZISSO nm ngAD 50514502130 notes M Romveil copyrighted 2003 variable gain ampli er 44 lowpass lter gt a TT 39 gtltgtlt x x Transimpedance amplifier low input noise current wideband Functions Linear amplifier chain with variable gain accomodate range of received power Low pass filter to bandlimit noise from flow to 075 B bit rate Not shown AC coupling or DC restore loop remove DC from signal Comparator to quantize in voltage M S latch PLL to set decision time points Filter bandwidth is the minimum sufficient for zero intersymbol interference so as to minimize noise within decision system bandwidth ECEMSCZiBC notes M Rodweii copyrighted 2008 limiting li ai BBGBiVBI 44 limiting ampli ers Simpler form for highest speed operation No AGC instead ampli ers limit for stronger input signals Each ampli er has bandwidth 75 of B bandlimits noise As input power is increased more stages driven into limiting Effective voltage comparison point is rst limiting stage Bandwidth exceeding gt 075 B prior to limiting point degrades sensitivity Form does not accomodate dispersion compensation AC coupling or DC restore needed not shown ECE1ASC21BC notes M Podwel mpynghzed 2W8 Upper half is basic AGC cell Differential pair with V 391 variable current shunt Lower half is DC compensation Adds DC as gain is reduced compensates current reduction from upper block Vago bar Vagcbar Vbias O Mil quotBEGINquot BI olar lt53 t DC currents in the 2 BJT s are forced by current sources all to be I 0 Analysis work in lecture shows that for a inputs much larger than kTq Vow VinypeakipeakZ kT61 10T C bit ECE145C218C notes M Rodwell copyrighted 2008 input from TA O l signal from DC restore loop 3 W Note input level shift Interconnect drivers receivers might be current steering 0r TASTIS Anticipate multiple TASTIS stages more than shown so notes M RodweH copyng ed 2008 limiting Amnlilier chain M S 8 NMIIS DC levels at Vdd 2 Differential forms are also feasible ask me ECE14SC27BC mazes M Rudw all cupyngmw 2008 very high frequency R bypass sech on for RF C control Forward Gain AOL 2 AV Reverse Gain 2 lsRC Loop Transmission T AVSRC Closed Loop Gain i T SRC AVsRC sRCAV 1T 1AVsRC 1sRCAV CL 2 AV Where flow AV 27ZRC 1 Jf flow segue215C notes M Rodwel coprrgmeaznoa WIIV TIA illlllll stage E Sininf4kITgm4kTRSRgR FET SEquot f ZkTgm 4kTRM RX2qube BJT DetailedTIA noise analysis left to reader see noisenotes 44 f C 127thigh CmR l Av Miller effect Szmzmlf 4kTRf 27Z m2SEnEnfSEnEnfR L l 27thigh C MR I need smaller R for same bandwidth S1m1mf 4kTRz Z JCMYSEnEK f 55quot fR more noise because R is smaller 5057450 mac notes M Rodwel copyrighted 2008 Willellaml THIS GIVIIIS amp IIIVIIIS V DD VDD V01 VDD2 RF C C C VV R Left 2 designs are low gain Wideband designs for very high bit rates Right Lower rate design larger open loop voltage gain permits larger R f 50514502180 Hales M Rudweu cupynghled 2008 WilleIIaml 39I39Ills Binolar V V CC CC Left low gain Wideband design for very high bit rates Right higher gain lower bandwidth design for moderate rates higher AV gt larger Rf feasible gt less noise ECE745027BC no es M Romet copyIgmed 2008 Widehaml 39I39I s Illlllllll I10 level V CC V 38 This sequence has DC output levels of 415 0 V 5 Consider what input DC levels TASTIS chain can accept Similar level shifters can be are used with all TIAs shown Designs with many diodes slow Designs with cascaded EF level shifters badly damped E CE 1450 2 180 notes M Rodwell copyrighted 2008 BGGGWBI SGIISilWiW This will be derived in a subsequent notes set Assume input noise of the form Slinlm f a bf 2 Then hV Pmin Q77 Where Q 2 SNR 6 for 10399 uncoded bit error rate I zaBI2 bB3I3 I2 E 068 I3 2 012 This assumes channel lters having bandwidth 75 of the bit rate B E CE 1450 2 180 notes M Rodwell copyrighted 2008 Timing BEGINva decision ckt 00 System synchronizes a VCO to the average pulse period of the 1ncom1ng data Phase detector must be tolerant of phase reversals inherent to modulated data ECE74SC27BC notes M Rodwel mpyngmed 2008 nemultinlexer and interlace Will timing recoverv decision ckt Incoming data 161 tree demux 16 data at 116 the rate Tree lemultinlexer Ecgwscmac notes M Romet copyngmed 2008 decision ckt fdatal2 fdata fdatal4 Note that MS S latches are requlrecl to prevent timing skew ECE 145C 218 C notes set 2 Transmission Lines Mark Rodwell University of California Santa Barbara rodwelleceucsbedu 8058933244 8058933262 fax E 1450 2180 notes M Rodwell copyrighted TI IlSIIliSSi II lines Geometries Characteristic Impedances Group Velocity Dispersion Skin Effect Losses substrate radiation losses Excitation of unwanted modes suppression Packaging and package resonances types of transmission lines E CE 1450 2180 notes M Rodwell copyrighted TI EIIISIIIiSSiIIII lines for I39llWille Wiring geometry voltages currents V l 12 I 12 E CE 1450 2180 notes M Rodwell copyrighted TI EIIISIIIiSSiIIII lines for I39llWille Wiring geometry voltages currents W2 4 w E CE 1450 2180 notes M Rodwell copyrighted gtW Dominant Transmission medium in IllV microwave amp mmwave le Key advantage IC interconnects have very low ground lead inductance Ground lead inductance leads to groundbounce is Millermultiplied by IC gain Key problems throughwafer grounding holes vias coupling to TM modes in substrate Via inductance forces progressively thinner wafers at higher frequencies basic theory L C 20 velocity Gamma E CE 1450 2180 notes M Rodwell copyrighted TI IlSIIliSSi II lines A pair of wires with regular spacing dielectric loading along the length These have inductance per unit length and capacitance per unit length Forward and reverse waves propagate Reflections will occur if lines are not correctly terminated l 1 1 I l I TI EIIISIIIiSSiIIII lines Basic IBM Z Ldz S H H H V gen From basic nodal analysis of line dV dz LdI dr and d1 dz C d V 611 from which we nd Vzt Vt zv V tzv Vt zv Vtzv Z 0 0 21 where Z xLC and vzlxLC Forward and HBVBI SB Waves l I l l l l V t z v voltage in forward wave V t z v voltage in reverse wave V t Z v Z 0 VIZV Z 0 current in forward wave current in reverse wave 03900quot and characteristic Imnetlance l I l l l l ZO LC and vzlxLC L and C are here quantities per unit length v c 8m7 Where c is the speed of light and am is the effective dielectric constant of the line Zsc f V 1 l l l l 1 ZL gen At end of line V F1V Where Fl 2 Z Zquot 1 Z Zo 1 At beginning of line V FSV 7ng Where rs z ZS Zo1 ZS20 Zo Zo ZS Need good terminations to prevent line reflections and ringing andT ECE1450 2180 notes M Rodwell copyrighted l l l l l I If total line length is Z englh Then total capacitance in that length is C Clenglh 2 0 and total inductance in that length is Llenglh TZO Where T length v 2quot speed of light delayquot on the line E 1450 2180 notes M Rodwell copyrighted llllllllell models Ill GIT SIIIII I transmission IiEICIGS Tmodel Pimedel L2 L2 0 l E If total line length length is much less than a wavelength or total line delay I l v is much less than 1 fs length ignal or total line delay I is much less than pulse risetime then the line can be approximated as a T 0r 7 section T length Zo Llenglh zZo E 1450 2180 notes M Rodwell copyrighted ladder models of moderately snoruransmission nines Pi model synthesis L L L L L J U J J U J L U L L U J J U J TCZ TCZ TCZ TCZ TCZ TCZ TCZ TCZ TCZ TCZ Tmodel synthesis m m m m m To To To To To Clearly we can break a line of any length into sections of length I such that Tune 2 1 line line v is much less than a signal period In this fashion a transmission line can be modelled by an LC lter This is a frequent substitution in circuit simulations Skin Loss E CE 1450 2180 notes M Rodwell copyrighted Assume a plane wave perpendicularly incident in direction 2 onto a plane of metal E H 6E jauH and ai jws0E 62 62 Hence Ez Eoe where 7 1jammg a If we ltlt 0 then 7 E Jjwua Jana2 ijua2 De ning the skin depth as 5 42 ago we nd that EZ Eoeiz eijz the eld dies down exponentially with distance into the metal Perhaps more importantly the wave impedance in the metal is E jaw jaw g nmelal Z J H jam a a 20 20 substituting in the expression for the skin depth 1 l 77mm j lt note the res1st1Ve and 1nduct1Ve terms 05 05 This is the SURFACE IMPEDANCE E CE 1450 2180 notes M Rodwell copyrighted In a transmission line the wave travels parallel not perpendicular to the metal surface but the same surface impedance is seen provided that the transmission line wavelength is much larger than the skin depth The transmission line then has an added series impedance per unit distance of series 1 where P is the effective current carrying periphery a For this microstrip line there is surface impedance both in the signal and ground lines Zseriesz W W2H 50 E CE 1450 2180 notes M Rodwell copyrighted I 02 I 02 I 02 I C2 39 39 39 This then introduces both loss and dispersion i serum series and P 50 62 62 series Vz jamzm ij1P ajP a 0 1z V ij ij some secondary change in characteristic impedance gtZ gt Vz Voe Wz where yline ZseriesjaC V 1Zseries janLC1 j2mL jawLC CL2 1 j wxLCZ 2Z mLC yhne J W 0 J 2201350 2201350 Skin Loss dispersion E CE 1450 2180 notes M Rodwell copyrighted Skin eet losses Iii Thus impulse isspunse 3 quot of we transmission Mr E C Uz1 JrT ex 17 found iine cam Main be min 392 I Wiginmn and J I W I Nauman Pmc IHE We 395 W 420 February 1957 quot Skin effect causes pulse bmacisning pmporiional t0 distance2 Skim efi ect impulse weaponse I I I I I I I I I I I I l I I I I 003 0025 002 5 g 0015 001 0005 CI 39 39 39 39 I 39 39 39 39 39 39 39 39 39 39 39 0 2 ID 0391 normalnzed time The step response is the integral of the mmpwlss rsspmss Nuts the innitial fast rise and Ms subsequent quotdribble up smar a s sristis at skim s sst losses mespio nss to 1 V input step Iumcth o m Skin Effect Step Response Illllllllllllllllllllllllllll st l hasn39t reached 19 Volts P Illllllllllllllllllllllllllll 5 TIE 115 2039 25 EU m normallized time E CE 1450 2180 notes M Rodwell copyrighted Radiation Loss ECEM5C218C noies M RodWel copyrighted conlanar Waveguide No ground vias Hard to ground C No need to to package thin substrate 39 V Parasitic microstrip mode 0 ground plane breaks a loss of ground integrity IIIV substrate mode coupling se39suatg or substrate losses kz substrate substrate mode coupling Silicon conducting substrate gt su strate conductivity losses Parasitic slot mode Repairing ground plane with ground straps is effective only in simple le In more complex CPWICs ground plane rapidly vanishes a commonlead inductance a strong circuitcircuit coupling 40 Gbs differential TWA modulator driver 35 GHz masterslave latch in CPW 175 GHz tuned amplifier in CPW note CPWIines fragmented ground plane note fragmented ground plane note fragmented ground plane E CE 1450 2180 notes M Rodwell copyrighted IIIV MIMIG Interconnects classic Substrate Microstrin W Brass carrier and IC with backside a sem ly roun ground plane ampvias interconnect substrate IC vias eliminate onwafer round loops 12 pH for mom substrate 75 a 100 GHz Line spacings must be 3substrate thickness 3 factors reqUire very SUbStrateS for GHZ CS gt lapping to 50 um substrate thickness typical for 100 GHz Kansansmu M w mum Substrate Radiation losses I Transmission line velocity is v c 1 8 2 Velocity of a plane wave in the substate is v which is slower Power radiates at angle 1 determined by matching KZ With substrate of finite thickness radiation 5 ows requency structure due to substrate modes W calmmu M w mum Substrate Radiation losses II n nmahan run I man a MSW M ulwmiummmm quotum i a quotmwmm Experimental confirmation scale model measurements am an m u Ln 3s 1mmnma m 11 Loss in dB per wavelength is proportional to frequency2 and to 319 5 49 Offtlshe tiansverse From Rutledge et al see Imensronso e Ine reference list E CE 1450 2180 notes M Rodwell copyrighted ERD I I I I I I I I I I I I I I I I I I I I I I I I I D I 245 39 l 1 39 E E Substrate M203 E g 20 E a w n Dam1m F j I I a I 39 HT 39 C a H153 3 I D n 39 quot E 1 5 3 quot quot 39 SID2 t r 7 DEBU m D100 gum DIED I I I I l I I I I I I I I I I I I I I I I I I I 390 100 20E BUDI 400 500 Frequency GHZ mucmscmsmmw Wm TransmissionLine Losses Radiation Losses Coplanar waveguide as example ammws mm cc 3 2w2 f3 Line impedance constrains SW Narrower lines are better Skin Losses amd8 mm x wquot fquot2 Wider lines are better Microstrip substrate radiation losses are reduced by substrate thinning CPW substrate radiation losses are reduced by reducing S and W but good design practice is to thin substrate until it cannot support dielectric waveguide modes E CE 1450 2180 notes M Rodwell copyrighted I I I I I I I I I I I I I 10 quotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquot 1 mm cable L E quotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquotquot I 14 dBm at E g 3 100 GHz cutoff g 3 mm cable llllllll I 31 dBm at B 1 39 33 GHz cutoff c lg J 10 mm cable m 07 dBm at g 10 GHz cutoff 2 E 01 4 Z 8r21 tan5310 I I I I I I I I I I I I I I 1 10 100 1000 Frequency GHz Single mode propagation requires f S c 2 ilk 2 D Dom 1 r inner Skin loss ash oc f 2 D gt Loss ash 00 f32 Inner quotcircuittypequot parasitic modes Transmissionnu Paras39 0 MINES F a hymn nip gvound slgnal gvmmd ml 59quot substvzle subslvale backslde gmund plane lmlemlonal bankslde gmund plane mlenllonall alwatev chuck lacmdenlal m walelchuck lancldemzll mlcvosmp mode av av l l v av v 7v w on lanar gm 0 Elm modep D V a V m l we av v av mplanar mvegmae mode nv Total number of quasiTEM modes is one less than of conductors Care must be taken to avoid excitation of parasitic modes unexpected results will otherwise arise To Avoid quotcircuitTimequot Parasitic Modes 1 Where do the currents flow 2 Which conductors have what voltages for which modes Be aware that currents must flow in the ground planes of unbalanced transmission lines The currents flow close to the edge of the ground plane nearest the signal conductor there are equal and opposite voltages on the 2 conductors of balanced transmission lines This seriously restricts the types of junctions allowable E CE 1450 2180 notes M Rodwell copyrighted 12 2 lt 4 lt lt 1 gt gt gt 1 lt 4 lt lt 12 2 i i 2 T i 2 12 2 lt 4 lt lt 1 gt gt gt 1 lt 4 lt lt 12 12 A slotline mode is excited at a CPWjunction The fix this is one of many possible examples E CE 1450 2180 notes M Rodwell copyrighted 1180 GHz HEMT amplifier UCSB HRL Note the ground bridges UH HHBHES 13 50532 3mm 39 nznmmunnznnn a 1 m I r x rl 14 39r 11 7 339 N J Lr 1 f l V INEEf l lgq 71 U I gt 39 B Agarvval UCSB M Matloubian HRL package resonance and grounding E CE 1450 2180 notes M Rodwell copyn39ghted di ital ADC r segctions input 39 buffer I I Lground f ground return m jmeo A V currents a m Ground simply means a reference potential shared between many circuit paths To the extent that it has nonzero impedance circuits Will couple in unexpected ways RF resonance oscillation frequently result from poor ground systems ECEM5C218C noies M RodWei copyrighted line 1 ground T ground line 2 ground plane I l commonlead inductance coupling EMI due to poor ground system integrity is common in highfrequency systems whether on PC boards or on ICs E CE 1450 2180 notes M Rodwell copyrighted l llllllll BIIIIIIBB I0 Packaging Will TonSuriaceonlv f llllll IC parallelplane transmission line peripheral peripheral bond inductances bond inductances E CE 1450 2180 notes M Rodwell copyrighted Brass carrier and IC with backside assembly ground ground plane amp vias interconnect substrate IC vias eliminate onwafer ground groundground IOOPS inductance powersupply resonance E CE 1450 2180 notes M Rodwell copyrighted I DWBI SIIIIIIW Resonance Lb nd Resonates at f 1 27r1Lb0ndCa ftpquot Von gain peak suckout oscillation etc co I Icon Active AC supply regulation Passive filter synthesis R L1 C1 supply impedance is R at all frequencies e E CE 1450 2180 notes M Rodwell copyrighted I DWBI Slllllllll Resonances PDWBI SIIIIIIIII namning 8O I I I I I I I I I I I I I I I I I I I I I a E E g 70 2m JE ZvJ E ZE III O j bypass capac ors 1 1 1 I g E seriets l shunt E reSIs Ive g damplng IIIII I39mquot E Q 40 In I NIHNIIIIIII quotIIIle 2 Wall quotIn g 3 O E III I I IIIWIIIIII III39VIIIIE 5 I II I I39m ullquotquotlumll quotMIMI a 39 I lquot III III III III IIIquot IIIIII IIII39IIIIIIIIII39I I39II III g E IIIIII IIIIII39I39IIIII IIIII39IIIIIII IIIIIIIII IIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII quotE o Q O I I I I I I I I I I I I I I I I I I I I I O 20 4O 60 8O 1 00 Frequency GHz 90 GHzlocal resonance between power supply capacitance and supply lead inductance N 5GHZ resonancesglobal standing wa Ie on power supply bus power supply usally will resonate we must model simulate and add damping during design illi E CE 1450 2180 notes M Rodwell copyrighted Interconnects Summary Design Strategy ECEM5C218C noies M RodWel copyrighted conlanar Waveguide Summary No ground vias Hard to ground C No need to to package thin substrate 39 V Parasitic microstrip mode o IIIV39 substrate mode coupling se39suatg or substrate losses kz substrate substrate mode coupling Silicon conducting substrate gt su strate conductivity losses Parasitic slot mode Repairing ground plane with ground straps is effective only in simple le In more complex CPWICs ground plane rapidly vanishes a commonlead inductance a strong circuitcircuit coupling 40 Gbs differential TWA modulator driver 35 GHz masterslave latch in CPW 175 GHz tuned amplifier in CPW note CPWIines fragmented ground plane note fragmented ground plane note fragmented ground plane E CE 1450 2180 notes M Rodwell copyrighted classic Substrate Microstrin Summarv W Brass carrier and IC with backside a em ly roun ground plane ampvias interconnect substrate IC vias eliminate onwafer round groundground IOOPS indurianm 12 pH for mom substrate 75 a 100 GHz Line spacings must be 3substrate thickness 3 factors reqUire very SUbStrateS for GHZ CS gt lapping to 50 um substrate thickness typical for 100 GHz ECE1450 218C notes M Rodwell copyrighted IIIll IVIIIVIIG Interconnects ThinFilm Microstrin thinfilm microstip line narrow line spacing gt 0 density Ground Plane 1 no substrate radiation no substrate losses g fewer breaks in ground plane than CPW but ground breaks at device placements InP mmwave PA still have problem with package grounding Rockwell need to flipchip bond thin dielectrics gt narrow lines gt high line losses gt low current capability gt no high2 lines ECEld5C218C holes M RodWel copyrighted IIIIt MIMIG Intel eenneets Inverted ThinFilm Microstrin narrow line spacing a C density inverted micrOStip quothe Some substrate radiation substrate losses No breaks in ground plane no ground breaks at device placements still have problem with package grounding need to flipchip bond thin dielectrics a narrow lines a high line loses a low current capability a no highZo lines InP 8 GHz clock rate deltasigma ADC ECEM5C218C noies M RodWel copyrighted 0 clean l llllll I llll ll gt interconnects can39t I10 modeled 35 GHz static divider interconnects have no clear local ground return interconnect inductance is nonlocal interconnect inductance has no compact model 8 GHz clockrate deltasigma ADC thinfilm microstrip wiring every interconnect can be modeled as microstrip some interconnects are terminated in their Zo some interconnects are not terminated but ALL are precisely modeled InP 8 GHz clock rate deltasigma ADC E CE 724A lL SI PrInCIples Lecture 8 CMOS In verters Dela y Power and Sizing Prof Kaustav Banerjee Electrical and Computer Engineering Email ka usta vece ucsb edu is Kau av a f Pmpagatim Belay C 205 Inverters CMOS inverter capacitances Cap on Node f 0 Junction cap Cdbp and Cdbn 0 Gate overlap capacitance I C gdyp and gdm beware of l l I Mlller effect ngn Cdbn ICint ICg Interconnect cap C ngap Cdbp f Vin 0 0 mt Receiver gate cap Cg C x Verter capacitances Cload Cdb Cdbp ngn ngp Cint C gate Y J Y j C Cdb Cdbm ngn ngP gate AKeqCJO PKeqsijsw 2WXDC0x WLdmwnCox I Miller Effect For each gate CMOS Inverter PropagatiOn Delay Approach tPHL CL szing2 n a 4K iu 4I quot 5 x 5 CMOS In verter Propagation Dela y Approach 2 tpHL RonCL Effquot 069 RonCL IL4J L u H 7777777777777 1r iiiii J V In L i r Transient Response Due output before the transistors can even start to re 7 changes at the inputcan affect gate performance I to ng of transistors directly couples voltage at input to act to 2 5 Vm Symmetric inverter has VOU tpHLtpLH 2 A 1 5 Z gtU 1 tpHL PLH o 5 Vol V DD 1 7 Z x V00 IDSAT 9 R2 1 I V wa VDDZV IDSATU 9 4 002 Vim W wnh rm rim 7 WWW 2 Delay as a function of 00 Same as the ON resistance of a transistor Trade off energy dissipation vs performance 55 1 1 5 J 4 5 z 0 692 a 0 52 CLVDD 7 HL y F 41135217quot WLj nanDSATJVDD VTn VDSATnZ 4 6 5 35 7 Tu E 6 3 39 u 5 Note for VDD gtgt VT Q 25 Iggsmio Vamp2 tp is almost 5 ll 5 39 2 avoided Independent of V00 7 Some improvement due to 7 1 5 D D channel length modulation D u Reliability concerns 1 03 1 12 14 16 13 2 22 24 at high V00 De vice Sizing x 10 3R i i l 36 for xed load 34 7 S sizing factor 7 3 2 for NMOSPMOS 39 C V C V 3 3 rpm 0692 L W 052 3 4135131 WLlink quotVDSATKVDD VTn VDSATnZ HQ 28 7 7 25 Selfloading effect Intrinsic diffusion 24 capacitances 22 7 7 dominate 2 NMOSPMOS ratio 11 CMOS inverter loaded by identical gate i L x10quot 5 youl improves with increasing Wp tpHL degrades with increasing Wp larger parasitic cap 45 t sec p A 35 16 24 39elds symmetrical transient response 3 35 4 45 5 B If symmetry and noise margins are not of prime concern inverter delay can be reduced by reducing the width of PMOS 1 15 2 25 Impact of Rise Time on Dela y 035 03 g 0 25 E 02 015 M As the input signal changes gradually MOS conduct simultaneously a pHL V 03 Design for Performance CI Keep load capacitances CL small Recall that three major components contribute to the load cap internal diffusion overlap caps interconnect cap fanout gate cap El Increase transistor sizes watch out for selfloading El Increase VDD watch out for reliability issues quot Pawer Dissip Where Does Power 60 in CMOS Dynamic Power Due to chargingdischarging of capacitors Leakage Power Subthreshold Gate Junction ShortCircuit Power When NMOS and PMOS are both turned ON Dynamic Power Dissipation Energytransition CL Vdd2 Power Energytransition f CL Vdd2 f 0 Not a function of transistor sizes 0 Need to reduce CL Vdd and f to reduce power Energy taken from supply during transition EVDD 2 ivDD tVDD dtszDICL o o Von d2 dt CLVDD J dvout 2 CL V020 o Dynamic Power Dissipation Note during the discharge phase charge is removed from CL and its energy is dissipated in the NMOS Energy taken from supply during transition dvo Von E Von 2 Ivan tVDD dt VDDI CL dtm dt CLVDD I dVout CL V020 0 0 0 Energy stored in the capacitor E w39 d wc det d c VDD d CLV 2 C 2quot Von tvout tJ L Vout t L Vow Vout T Where is the other half of the energy Dissipated by the PMOS Modification for Circuits with Reduced Swing E0 gt1 CL Vdd VddVt ii Can exploit reduced swing to lowerpower eg reduced bitline swing in memory Primary Leakage Mechanisms v i Vout j i i i Drain Junction 7 7 7 i CS Leakage Liar SubThreshold Current Subthreshold current one of most compelling issues in lowenergy circuit design Subthreshold Leakage Component Subthreshod Slope S 60 mvdecade for ideal transistor with n1 1 0392 10393 1oquot ID Ves Snn1o 1012 01 02 03 04 05 05 07 08 09 10 VGS V o Leakage control is critical for lowvoltage operation Kaustav Bane 39eie Re verseBiased Diede Leakage v v v Reverse Leakage Current Jr Vdd fix L 1 I 39 IDLJSXA JS 10100 pAumZ at 25 deg C for 025pm CMOS JS doubles for every 9 deg C Short Cimuit Currents IO Vn th K Banerjee andA Mehrotra IEEE Transactions on 0 who and tune mwmi Electron Devices Vol 49 No 11 2002 a 5 Why mdmnmkwlwfnrm hf Cues mm Static Power Consumption In the absence of 1ng switching steadystate rJ Sources operation I M5 L i Istat Due to all previously i i Vout mentioned leakage Hun T currents Vln5V quotquotl l E C l Pstat Pn1Vdd stat Wasted energy Should be avoided in almost all cases but could help reducing energy in others eg sense amps Leakage El Effect of leakage current Wasted power power consumed even when circuit is inactive Leakage power raises temperature of chip Can cause functionality problem in some circuits memory dynamic logic etc El Reducing transistor leakage Longchannel devices Small drain voltage Large threshold voltage VT w quot v 391 Kau iavs a mg Principles for Power Reduction El Prime choice Reduce voltage Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question 06 09 V by 2010 El Reduce switching activity CI Reduce physical capacitance Device Sizing Leakage Power Reduction El Process scaling VT reduces with each new process historically Leakage increases 1OX El Leakage vs performance tradeoff For highspeed need small VT and L For low leakage need high VT and large L El One solution dualVT process LowVT transistors use in critical paths for high speed HighVT transistors use to reduce power quot Scaling Theory Constant Vdd Constant E Parameters scaling scaling Width w 07 Length L 07 Dlmentlons Oxide thickness t0x 07 Junction depth X 07 Die Area 072 Gate capacitance per unit area C gm 8 01 7 Gate capacitance C 3 wLCgm 07 Total Capacitance C 07 Supply Voltage VDD l 07 Current per device IDS 0c m V35 Vm VDD 1 07 C g AV Intr1n51c Gate Delay r 07 07 AV Fre uenc focl L q y r 0 7 Active Power Dissipation Pam CVng 1 072 EnergyDelay Product CVgDr 072 049 074 02401 1 07 2 Power Dissipation density PMWAma W 2 E0 732 w Inverter ling Load capacitance Vcc Driver Receiver Vcc Cg4 II M2 M4 CL Cint Cexz I Cdb2 Vout Voutz Vin c j quot ng12 Cdb1 T Cw L Internal Cags of Driver Cint r Junctlon caps Cdb12 M1 M3 Gate caps ng12 including Miller Caps External Caps Cext Interconnect cap CW Gnd Recelver gate caps Cg43 Intrinsic delay of CMOS inverter Let Req be the equivalent resistance of the gate inverter then delay to is defined as rp 2069 Reg Cm Cext 2069 Req Cm 1 if int tpo 1 if int tl00 is the intrinsic delay Impact of sizing on gate delay Let S be the sizing factor Rref be the resistance of a reference gate usually a minimum size gate CW be the internal capacitance of the reference gate Rref Cint SCiref 7 Reg Hence R76 C t tp 069 S Ciref 1 ex 1 Intrinsic delay is S SCiref independent of gate sizing and is determined C ext only by technology and Z 069 Rref Ciref 1 SC inverter layout iref 2 If 8 IS made very large C gate delay approaches p0 1 I the intrinsic value but iref increases the area signi canty In verter Chain If CL is given 7 How many stages are needed to minimize the delay How to size the inverters May need some additional constraints In verter Delay Minimum length devices LO25um Assume that for WP 2WV 2W same pullup and pulldown currents approx equal resistances RN RP approx equal rise rpm and fall tpHL delays W Analyze as an RC network 2W Delay D rpm 1n 2 RNCL rpm 1n 2 RPCL Load for the next stage Cgm 3LC A I V 15 Kaumquot gamer53 In verter With Load RW Delay E q RW V 1 T tp kRWCL Load CL k is a constant equal to 069 W unit Assumptions no load gtzero delay


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