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by: Kobe Dare


Kobe Dare
GPA 3.6


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Class Notes
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This 75 page Class Notes was uploaded by Kobe Dare on Thursday October 22, 2015. The Class Notes belongs to THTR 124 at University of California Santa Barbara taught by Staff in Fall. Since its upload, it has received 54 views. For similar materials see /class/226860/thtr-124-university-of-california-santa-barbara in Theatre at University of California Santa Barbara.




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Date Created: 10/22/15
Lecture Prof Kaustav Banerjee Electrical and Computer Engineering Email ka usta vece ucsb edu In verter Operation El Inverter is simplest digital logic gate 0 D 1 In Out 1gtO 0 El Many different circuit styles possible Resistiveload PseudoNMOS CMOS El Important characteristics Speed delay through the gate Power consumption Robustness tolerance to noise Area and process cost l O Ol t FIG 223 A CMOS inverter In verter model lTC Voltage transfer curve VTC plot of output voltage Vout vs input voltage Vin Vin Inverter V0ut Ideal diqital inverter Vcc ideal When Vin0 VoutVcc When VinVcc Vout0 Sharp transition region Vout Actual inverter lOH and lOL El VOH and VOL represent the high and low output voltages of the invener El VOH output voltage Vout when Vin 0 El VOL output voltage VOL when Vin 1 V1 1 Ideally VOH Vcc 39 VOL 0 VOL and lOH El In transfer function terms 39 VOL fVOH VOH 39 VOH fVOL f invertertransfer V01quot function El Difference VOHVOL is VOL 5 the voltage swing of o V Vcc Vln 0H the gate Fullswing logic swings from ground to Vcc In verter Threshold Inverter switching threshold Point where voltage transfer curve intersects VoutVin line VoutVin V01quot Represents the point at which the inverter VOL switches state Vin VCC 39 Normally VM z Vcc2 0L m r U nity Gain Points Slape 1 ESPl3 1quot 1 Nwse Margins El VIL and VIH measure effect of input voltage on inverter output El VIL largest input voltage recognized as logic 0 El VIH smallest input voltage recognized as logic 1 El Defined as point on VTC where slope 1 V1L V1H VICC Vin Noise Margin cont El Noise margin is a measure Interconnect of the robustness of an gto gto inverter 39 NML VIL 39 VOL V0 1 39 NMH VOH 39 VIH NMH VIH El Models a chain of inverters Example NML VIL First inverter output is VOH V35 I Second inverter recognizes input gt VIH as logic 1 I Difference VOHVIH is safety Ideally no1se margm should be zone for noise as large as possible Noise Margin cont El Why are VIL VIH defined as unitygain point on VTC curve Assume there is noise on input voltage Vin Iout Inoise Firstorder approximation Taylor Series Note dVoutldVin 0 occurs only d V Vow 0W Vnoise at the beginning and at the end of the VTC curve elsewhere It m is negative de gt 1 noise will be ampli ed out If gain dV If gain lt 1 noise is ltered Therefore VIL VIH ensure that gain lt 1 Output Characteristics V input Characteristics Logicai High V w Ouiput Range VUH NiMH VIH mdeterminaie V Region NML Lngi39ca Law I VOL Output Range GNU Logicai High Input Range Logical Low Input Range FIG 227 Noise margin de nitions In verter Time Response VCC Vcc2 Vin Vss Vcc gt Vout Vcc2 t0 t1 t2 t3 El Propagation delay measured from 50 point of Vin to 50 point of Vout D tphl t1 39 to tplh t3 39 t2 tp 12tl0hltplh Rise and Fall Time tF tR V90 V10 El Fall time measured from 90 point to 10 point tF t1t0 El Rise time measured from 10 point to 90 point 39 tR t3 39 t2 El Alternately can define 2080 risefall time Ring Oscillator El Ring oscillator circuit standard method of comparing delay from one process to another El Oddnumber n of inverters connected in chain oscillates with period T usually n gtgt 5 M tPHL2 tPLHE tPHLl tPLH2 tPHLE tPLHl T thplhl tphll tplh2 tph12 tplh3 tphl3 1 T2t np f T 2m p 2nf Resistiveload Inverter El Requires only NMOS transistor and resistor VCC El When Vin 0 I NMOS is OFF VGS 0 R No current through NMOS 0r Vout re5stor Vin o l Voutchc El When Vin Vcc NMOS is ON VGS Vcc NMOS ON resistance ltlt R I Vout z 0 Remember if body terminal not shown it is connected to Not suitable for VLSI large area of R DC grid for NMOS Vcc for power dissipation PMOS Drain current ID Load currenth Kirchoff s Law Rm 01 mA Von Vm 162 162 Vin v39m a uA 1000 v 18 800 15 600 R 15K a 12 V quot 400 V CR f 09 ds 0 load 200 0 u 39 As Rmadincreases VTC becomes sharper 12 H 9 RmxsK 06 RW10K lt R 15K 03 W K x a Vquot M Generic nMOS inverters with resistive or constant cgnen 19an PseudoNMOS In verter El Replace resistor with always on PMOS transistor Vcc 2 VGSP VCC El Easrer to Implement In 8 G standard process than large o resistance value D Vout El PMOS load transistor ViHO I Ratbed I ON when VGS lt VT gt ying VGS VCC transistor always on 05 the relative size of the Gnd transistors Linear when VDS gt VGSVT gt V Vcc gt VccVT Vout gt VT Remember VTPMOS lt 0 out Saturated when VDS lt VGSVT gt V lt VccVT Vout lt VT Vcc out Compare 800 18 with resistive 5 load inven er 18 Note Smaller 15 400 I W of PMOS 12 means larger V U 9 30 f 4 resistance 39 200 06 03 100 P 4 0 r r 0 y r r r C 0 03 06 39 12 15 18 d 0 0 3 06 09 12 1 5 18 FIG 230 PseudonMOS inverter and DC transfer characteristics CMOS In verter CI CI CI CI CI CI Complementary NMOS and PMOS devices In steadystate only one device is on no static power consumption Vin1 NMOS on PMOS off Vout VOL O Vin0 PMOS on NMOS off Vout VOH Vcc Ideal VOL and VOH High input resistance insulated gate and low output impedance finite resistance path between output and Vcc or Gnd Ratioless logic Vin Gnd Vout PMOS ll Out NMOS NWdl PMOS Polysilicon GM Contacts Share power and ground Abut cells DD Connect in Metal F stOrder Analysis VDD VDD T 7 CMOS In Verter Transient Response VDD RP tpHL fRonCL 069 RonCL Vout r E I CL Vm 5 0 V1715 VDD a Lowto high b Hightolow E CE 124A lL 5 I Principles Sequential 073m Designl Prof Kaustav Banerjee Electrical and Computer Engineering Email ka usta vece ucsb edu x at19f eag g ning Sequentia ILQEC Sequential Logic All useful systems require storage of state information Inputs gt gt Outputs COMBINATIONAL L39OGIC Current State I Next State Registers Q D lt A synchronous system A all registers are controlled TCLK by a single global CLK A generic Finite State Machine FSM consisting of combinational logic and registers Output of the FSM F current inputs current state Next State is determined based on current state and current inputs fed to the input D of the registers At the rising edge of the CLK D copied to Q with some delay Note There are 2 storage mechanisms 1 positive feedback and 2 charge storkage auatav aner39ee Classi cation of Memory Elements El Background Memory large centralized memory core high density array structuresSRAMs and DRAMs El Foreground Memory embedded in a logic individual registers or register banks focus of this section Classi cation of Memory Elements Static Memory El preserves state as long as power is ON El built by using positive feedback or regeneration where the circuit consists of intentional connections between the output and input of a combinational circuit El most useful when register will not be updated for extended periods of time eg configuration data loaded at powerup time El Condition also holds for most processors that use conditional clocking gated CLK where the CLK is turned off for unused modulesno guarantee on how frequently the registers will be clocked and static memories are needed to state information El bistable element is the most popular form Banterlree Classi cation of Memory Elements Dynamic Memory El store data for short ms period of time El based on the principle of temporary charge storage on parasitic capacitors in M08 devices El similar to dynamic logic capacitors need to be refreshed periodically to compensate for charge leakage El significantly simplerhence provide higher performance and lower power dissipation El most useful in datapath circuits that require higher performance levels and are periodically clocked KathieBantam Naming Conventions El Definitions a latch is a level sensitive device a register is an edgetriggered storage element El There are many different naming conventions For instance many books call edgetriggered elements flipflops This may lead to confusion however Any bistable component formed by the cross coupling of gates is a flipflop FF Latches Multiplexer based CLK1 D to Q D 2 D JP 2 CLK1 CLK0 state of Q As long as CLK remains high D will be CLK written on Q LatchBased Design N negative latch is transparent when 1 O o P positive latch is transparent when 1 1 Timing of PN Latches Positive Latch Negative Latch In gtD Q gtOut In gtD Q gtOut G G TCLK CLK clk I l l l I clk I I I In NMNMINNONN In NNNNINNONN Out I I I I I I Out Out I Out Out stable follows In stable follows In When clk When clk is high is low Latch versus Register CI Latch El Register stores data when Stores data when ClOCk is low 0r high clock rises or falls D Q D Q Characterizing Timing Latch Register 2 02 Q D Q D Q Datamay arrive after Clk edge gt Clk Ck 1 02 Q 1 02 Q Requires an extra timing parameter Data is ready when Ck arrives Registers or FlipFlops Combines two latches One ve sensitive slave and one ve sensitive latch master Edge Triggered FF or MasterSlave FF CLK039 D to QM 2745 Slave holds previous value D M QM Q Of Q CLK1 d CLK 1 master can t sample CLK input and holds value ofD quot H Slave opens and QMD Q e FIG 131 CMOS positive edge tn39ggered D ip op Timing De nitions CLK Register gt D Q gt D 1CLK ts setup time time for which the data inputs D must be valid before the CLK edge the hold time time for which data input must remain valid after the CLK edge tc2q worst case propagation time through the Register wrt the CLK edge Maximum Clock Frequency To ensure that the input data of the sequential elements is held long enough after the CLK edge and is not modified LOGIC too soon by the new wave of data coming in tpc0ml0 2 tcdreg tcdlogic gt thold tcd contamination delay 1 Tmm telkQ t11c0mb tsetup minimum deay CIk period must accommodate the longest delay of any stage in the network Static Latches and Registers Static Memories use Positive Feedback BiStability Vi1 Dcvm Vi2 DCVOZ 0f Obtained by ipping the wrt origin and then I 01 Va VTC of the second inverter rotating anticlkwise by 90quot I Vi2 Vo1 A B and C are the only three possible operating points If gaingt1 in the transient region A and B are the only stabe operating points C is a Vn V02 metastable point ECE145C 218C Notes set 7 Mathematics of Electrical Noise Mark Rodwell University of California Santa Barbara rodwelleceucsbedu 8058933244 8058933262 fax Strategy There is not time in 145c218c to develop this subject in detail Strategy give backround suf cient for correct calculation of SNR spectral densities correlation functions signal correlations error rates More detail can be found in my noise class notes on the web or in the literature Van der Zeil39 s book is comprehensive E CE 1 450 2180 notes M Rodwell copyrighted 2007 TIIIIiBS m distributions random variables expectations pairs of RV joint distributions covariance and correlations Random processes stationarity ergodicity correlation functions autocorrelation function power spectral density Noise models of devices thermal and shot noise Models of resistors diodes transitors antennas Circuit noise analysis network representation Solution Total output noise Total input noise 2 generator model EnIn model Noise gure noise temperature Signal noise ratio random variables E CE 1 450 2180 notes M Rodwell copyrighted 2007 The l Sl SIBII random Variables During an experiment a random variable X takes on a particular value x The probability that x lies between x1 and x2 is Px1lt x lt x2 TfXxdx x1 f X x is the probability distribution function 1396 I E CE 1 450 2180 notes M Rodwell copyrighted 2007 EXEIIIIIIIB l0 Gaussian IliSII illllli ll The Gaussian distribution fXltxgtJ1 ma a 2 2 2 750x 20x We will define shortly the mean 7 and the standard deviation 0393 Because of the central limit theorem physical random processes arising from the sum of many small effects have probability distributions close to that of the Gaussian f x M gt 4 N2Gx V gtlt g Expectation of a function gX of the random variable X Elgltxgtl JgltxgtfXltxgtdx Mean Value of X X 2 EX foxdx Expected value of X 2 ltX2gt EX2 szfXxdx 2 The variance 0x of X is its root mean square dev1at10n from its average value a ltX f2gtEX X2 Tx f2fXxdx The standard deviation 0x of X is simply the square root of the variance The notation describing the Gaussian distribution fXxeXp x x gt2 2 2 275036 20x should now be clear f M x V gtlt g The variance is the expectation of the square minus the square of the expectation E CE 1 450 2180 notes M Rodwell copyrighted 2007 To understand random processes we must rst understand pairs of random variables In an experiment a pair of random variables X and Y takes on specific particular values X and y Their joint behavior is described by the joint distribution f XY x y DB PAltxltBandCltyltDHfXYxydxdy CA E CE 1 450 2180 notes M Rodwell copyrighted 2007 Marginal distributions must also be defined ooB PAlt x lt B IIfXYxydxdy ooA lif dx and similarly for Y Doo PClt yltDHfXYxydxdy C oo lff ykl y In the case Where fXYx9y fXxfYy9 the variables are said to be statistically independent This is not generally expected E CE 1 450 2180 notes M Rodwell copyrighted 2007 The expectation of a function gX Y of the random variables Y and Y is OOOO Elgltxygt I jgltxygtf ltxygtdxdy OO OO Expectation of X EX a Txfmmwxdy foltxgtdxdy OO Expectation of X 2 EX2 ltX2gt foXYu ydxdy foXxdxdy OO OO and similarly for Y and Y 2 The correlation of X and Y is OOOO RXY ElXYl I jxy f ltxygtdxdy OO OO The covariance of X and Y is CXY EX XY rEXY fY Xr l RXY Xy Note that correlation and covariance are the same if either X or Y have zero mean values E CE 1 450 2180 notes M Rodwell copyrighted 2007 When we are working with voltages and currents we usually separate the mean value DC bias from the time varying component The random variables then have zero mean Correlation is then equal to covariance It is therefore common in circuit noise analysis to use the two terms interchangably But nonzero mean values can return when we e g calculate conditional distributions Be careful E CE 1 450 2180 notes M Rodwell copyrighted 2007 The correlation coef cient of X and Y is pXY CXY O XO Y Note the standard confusion in terminology between correlation and covariance Slllll Ill TWO Balllllllll Variables Sum of two random variables Z X Y liZ1EkXYYEh42XYY Eh hr hzaw If X and Y both have zero means Ek Eh Ek mgy This emphasizes the role of correlation E CE 1 450 2180 notes M Rodwell copyrighted 2007 Pairs III l illllll Gaussian liamlom Variables If X and Y are Jointly Gaussian 1 may 2 270X039Y l pXY xexp 1 cc arrltx arlty rlty r2 21p2Y 0 OXOY 013 This definition can be extended to a larger of variables In general we can have a Jointly Gaussian random vector leijan which is specified by a set of means 371 variances E xixi and covariances E xile linear quotIIBI EIIiIIIIS llll IEIW39S If X and Y are Jointly Gaussian and if we de ne VaXbY andWcXdY Then V and W are also Jointly Gaussian This is stated without proof the result arises because convolution of 2 Gaussian functions produces a Gaussian function The result holds for J GRVs of any number ECE1450 2180 note 0 well copyrighted 2007 Probability distribution alter a linear oberation orii nii39s 7EVEaXbYabY and chfwzf a EV2 72 aZEX2192EY22abEXY abf2 a EW2 W2 02EX2d2EY2 2ch EXY c 612 CVW EVW 7W EaX bYcX dY 7W 2 EacX2 ad bcXY de2 7W 2 acEX2adbcEXYbdEY2 abfcdf SBJQp gnome We can now calculate the joint distribution of V and W 1 f vaw VW 272390V0W11 p3 xexp 1 v VY v t7w Ww W2 21 HEW 0 13 UVUW o Vi E CE 1 450 2180 notes M Rodwell copyrighted 2007 Why are IEIW39S Imnortant The math on the last slide was tedious but there is a clear conclusion With J GRV39 s subjected to linear operations it is sufficient to keep track of means correlations and variances With this information distribution functions can always be simply found This vastly simplifies calculations of noise propagation in linear systems linear circuits Uncorrelated C XY O Statistically independent fXYOC y fXxfY y Independence implies zero correlation Zero correlation does not imply independence For J GRV39 s uncorrelated does imply independence E CE 1 450 2180 notes M Rodwell copyrighted 2007 Two voltages are applied to The power dissipated in the the resistor R resistor is a random variable P EP1ltPgtltltVlm2gtw2mnzgt ltVfgt2ltrigt W R l 1 1 ltV12gt2 7V1V2 ltV22gt R R R 1 2 1 2 1 V2 EltV1 gtE2leV20V10V2 aw ltV1V2gtltVigt The noise powers of the two random generators do not add a correllation term must be included The instantaneous time values of the random noise voltages do add E CE 1 450 2180 notes M Rodwell copyrighted 2007 l a 44 1 The fiber has transmission probability p Send one photon and call the of received photons N1 EN1 E p and ENf p so 031 ENf f 19 192 If we now send many photons M of them transmission of each is statistically independent so calling the of received photons N EN MEN1 Mp and a Mofvl Mp p2 Now suppose M gtgt 1 p ltlt 1 and Mp gtgt 1 2 The variance of the count approaches the mean value of the count E CE 1 450 2180 notes M Rodwell copyrighted 2007 Thermal Noise as a Ballll lll Variable A capacitor C is connected to a resistor R The resistor is in equilibrium with a quotreservoirquot a warm room at temperature T R can exchange energy with the room in the form of heat C can dissipate no power it establishes thermal equilibrium with the room via the resistor From thermodynamics any independent degree of freedom of a system at temperature T has mean energy kT2 hence ltEgtkT2 CW 2kT2 I I 0 Q gtkTC The noise voltage has variance kTC random processes scammo nukes M udwel m y ghtedzm Random Processes Draw a set of graphs on separate sheets of paper of functions of voltage vs time Put them into a garbage can This garbage can is called the probability sample space Pick out one sheet at random This is our random function of time The random process is Vt The particular outcome is Vt I III scammo nukes M Rudy917 mW gMedsz Time Averages VS Samnle Space Averages Recall the definion of the expectation of a function gX of a random variable X Egltxgt JgltxgtfXltxgtdx g is the average value of g where the average is over the sample space g With our random process definition we can define an average over the sample space at some particular time t1 Egltvltt1 Jgltvltt1gtgtfVltvltr1gtgtdltvltr1gtgt We can also define an average of the function over time Agltvlttgtgt Jgltvlttgtgtdr Ex scammo nukes M Rudy917 mW gMedz W An Ergodic random process has averages over time equal to averages over the statistical sample space Egltvltr1gtgt Agltvlttgtgt In some sense we have made quot random variation with timequot equivalent to E HE quot random variation over the sample spacequot Time Samnles Ill Balllllllll quot0008303 With time samples at times t1 and t2 the random process Vt has values V01 and V02 V01 and V02 have some joint probability distribution They might or might not be jointly Gaussian Va V02 V01 E CE 1 450 2180 notes M Rodwell copyrighted 2007 Using Nyquist39s sampling theorem if a random signal is bandlimited and if we pick regularly spaced time samples t1tn we convert our random process into a random vector We can thus analyze random signals using vector analysis and geometry This is mostly beyond the scope of this class V0 ECE14502180 notes M Rodwell copyrighted 2007 The statistics of a stationary process do not vary with time Nth order stationarity EfVltr1Vltr2gtVltrn EfVt1 are rVltrn r and lower orders 2nd order stationarity EfVt1 Vltr2gt EfVt1 are r lower orders gt EfVt1 EfVz 1 r W v02 v01 E CE 1 450 2180 notes M Rodwell copyrighted 2007 We will make following restrictions to make analysis tractable The process will be Ergodic The process will be stationary to any order all statistical properties are independent of time Many common processes are not stationary including integrated White noise and lf noise The process will be Jointly Gaussian This means that if the values of a random process Xt are sampled at times t1 t2 etc to form random variables X1Xt1 etc then X1X2 etc are a jointly Gaussian random variable In nature many random processes result from the sum of a vast number of small underlying random processses From the central limit theorem such processes can frequently be expected to be Jointly Gaussian


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