NEUROBIOLOGY II MCDB 152
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This 2 page Class Notes was uploaded by Erika Kuvalis on Thursday October 22, 2015. The Class Notes belongs to MCDB 152 at University of California Santa Barbara taught by Staff in Fall. Since its upload, it has received 77 views. For similar materials see /class/226904/mcdb-152-university-of-california-santa-barbara in Molecular, Cellular And Developmental Biology at University of California Santa Barbara.
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Date Created: 10/22/15
Synchronous Down Counter Make a synchronous down counter that counts down from 3 to 0 and takes in synchronous reset enable load and data Reset takes precedence over all other inputs and upon reset the counter should go to 0 Upon load the FSM goes to whatever state is on the input data If neither load or reset is high the FSM goes to the next state on positive clock edge if enable is high Otherwise it stays in its current state QQQ Q E YESSR 39 ma 2 V m cg 9 Keenan quot1 quot we rm 6 s we 5 Kim 2 675 0 when xqw imtymtmwwni 1 J grM aw u H thm QWV iQ module DownCounterReset Load Enable Data Count elk input Reset Load Enable clk input 1 0Data output 10Count reg 1 0 Count always posedge clk begin ifReset Count lt 0 else ifLoad Count lt Data else ifEnable ampamp Count0 Count lt 3 else ifEnable Count lt Count 1 end endmodule who Qm U u Adder Mealy FSM Implement the adder 39om lab 5 in mealy form Inputs are 2 bits A and B The outputs should be the sum and carry bits 323 Q Q Q k 0 b Input um Cami l iD b Ih loooogt i w ooHr oow b lOOD OD lh iom B x x 0 0 x x x x v tb au Or tooo gtlt x module DownCounterA B Sum Cout elk input A B clk output Sum output Cout reg Cout wire Sum assign Sum A A B A Cout wire CoutNext assign CountNext Cout ampamp A II B ampamp Cout ampamp A ampamp B always posedge clk Cout lt CoutNext endmodule