INTRO COMPUTER ARCH
INTRO COMPUTER ARCH ECE 154
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Date Created: 10/22/15
ECEi 54 Computer Architecture Lecture 10 Multiple Cycle Processor October 31 2006 tner Elean39cal and Computer Engineering Universin of California Santa larbara Review Partitioning the CPI1 Datapath New Store 1 Place so that balances length of clock cycle Logic delays about the same between registers 2 Place to save information needed later in instruction Q execution Q Review Multicycle Datapath v E s tnstmctton Fetch Critical Path 7 pestt Store Recall Step by step Processor Design Step 1 ISA gt Logical Register Transfers Step 2 Components of the Datapath Step 3 RTL Components gt Datapath Step 4 Datapath Logical RTs gt Physical RTs Step 5 Physical RTs gt Control Step 4 Store met Lynn 151 Inquot L g l R g 5 T Mf sw wwmmmmm um lt pc 0 Physical Register Transfers Pc e MEM e ups lt km A SExlmls Step 4 Branch Logical Register Transfer nulls Rl l met Pclt pc Mszmamsltl39h m re Physical Register Transfers Pclt pc else Pclt p obSEmllm5lv239h Our Control Model State specifies control points for Register Transfer Transfer occurs upon exiting state same clock edge mputs eeputtteps uutputs Output Legte 52529 X Regtstetrtapstet Cumvul Palms 39 Depends up lnpul cumvul pemte Step 4 gt Control Spec for multicycle proc instruction etch decode upevand latch Execute Writehack Mammy Traditional FSM Controller Step 5 2 datapath state diagram 2 control 00 Translate RTs into control points sum up mm EDMiulpuims 39z39ASSign states WW2 00 Then go build the controller S a cumml leMS Equal Q delapam 2 7 Q 7 w lt Mzwvci instructiun Mm imam rd IRen Mapping Register Transfers to Control Points Willahack mm 5mm Assigning States instru inn latchquot IR MEMP lt nnnllq erlllt s Pclt we n111 er llt s Pclt we n1n1 Execute Writehack Mammy Detailed Control Specs Instruction Set and Control Options 7instruction subset MIPS easy to implement FSM by hand Full MIPS instruction set gt 100 instructions inclucing Floating Point ozoNeed to use Verilog CAD tools Full lA32 instruction set 03gt 500 instructions including copy and edit save restore state setup for keylike memory protection Announcements 1Homework 4 due Thursday Quiz l ozoNovember 7Lh in class ozoOld quizzes at httphlltneceucsbeduexamsphp Quiz 2 ozoMovedto November 30 in class ozoSchedule rearranged see webpage Controller Design The state diagrams that arise de ne the controller firan instruction set processor are highly structured Use this structure to construct a simple microsequencer Control reduces to programming this very simple device microprogrammlng taken data ath Euntml z i L p uprcude Adding the Dispatch ROM Sequencerbased control waned microPC or pro Vs state register Microprogramming 00 Microprogramming is a convenient method for implementing structured control state diagrams Random logic replaced by microPC sequencer and ROM Each line of ROM called a microimtruction contains sequencer control values for control points To reduce con ision normal instruction eg MIPS addu called macroinstruction limited state transitions to zero next sequential branch to pinstruction address from dispatch ROM Control design reduces to Microprogramming Part of the design process is to develop a language that describes control and is easy for humans to understand Control Value E ect Wm 00 Next paddless 0 decode ROM 01 Next haddnssdispatchROM 10 Next haddtess paddress1 uuuuuu Emu Decade Decade umtm thumt tmmt 0mm To DataPath tt u M Icroprogramml ng MaCI39OI nstructlon Inte rpretatlon User Ingram phs ata this can change nhe nltheseis mz pad inln nhe all use micrnsequence eg Fetch Calc 08mm Addr Fetch perzndtsj Calculate Save Answertsj Q Designing a Microinstruction Setquot 1 Start with list of control signals 2 Group signals together that make sense vs random elds 3 Place elds in some logical order eg ALU operation amp ALU operands rst and microinstruction sequencing last 4 To minimize the width encode operations that will never be used the same time Horizontal yCode one control bit in ylnstruction for every control line in datapath Vertical yCode groups of controllines coded together in ylnstruction eg possible ALU dest 5 Create a symbolic legend for the microinstruction format showing name of eld values and how they set the control signals m m m n I l Q oUse computersto design computers Q rnon MemiaReg ALUSeiB Alternative datapath Multiple Cycle Datapath PCSquot a v Minimizes Hardware 1 memory 1 adder M PCWVCand sen m Mew ism mi 3 W NUSE A 32 Start with list of control signals grouped into elds Signal name 512st when deasserted Ef ct when asserted ALUSelA 1st ALU o erand PC 1st ALU o erandRe rs Reante None Reg is Written MemtoReg Reg wnte datamput ALU Reg Write data input rnernory n 7 rd RegDst Reg dest no g dest no a Mem1ltead None Memory am ess 15 read MD lt Mernaddr MemWnte None Memory at address is written IorD Memory address PC Memory address s IRWnte None 13 lt rno nte None p lt P ouree PCWnteCondNone 12F ALUzero then PC lt PCSouree PCSource PCSouree ALU PCSouree ALUout xt p ro xten e 1gn xten e a WP adds 395 n1 ALLlsuhIrzcts m e ALU dnvs un inn Dude ernrszj 1 ALU dnvs In 0R g OALU em 3 L M Microinstruction Format unencoded vs encoded elds Field Name W 11 Comm Signals Set wide narrow ALU Control 4 2 ALUOp SRCl 2 1 ALUSelA SRC2 5 3 ALUSeIB ExtOp ALU Destination 3 2 RegWrite MemtoReg RegDst Memory 3 2 MemRead MemWrite IorD Memory Register 1 1 IRWn39te PCWrite Control 3 2 PCWrite PCWriteCond PCSource Sequencing 3 2 Adder Total width 24 15 bits Horizontal Vertical Q Legend of Fields and Symbolic Names Add ALU adds Subt ALU subaaets Fune code ALU does function code Or LU does logical OR SRCl PC st ALU lnpu c rs 5Rc2 4 pu Extend putsign ext muses ExtendU nd ALU input zero ext m 154 Extshft nd ALU input sign ex 5112R see dALU input Regm destination rd ALU ALUcut rt ALU LUcut rt Mem r em Memory ReadPC eadmemory using PC Read ALU ead memory using ALU out for addr write ALU Jnte memory using ALUcut for addr Memory register em PC write ALU ALUcuthn d Sequencing Se Feteh Dispateh ispateh using R Q Quick check what do these eldnames mean Desimaiiml Code Name RegWrite MemToReg RegDest 00 0 X X 01 rd ALU 1 0 1 10 rt ALU 1 0 0 11 rt MEM 1 1 0 SRCZ Code Name ALUSelB ExtOg 000 X X 001 4 00 X 010 rt 01 X 011 ExtSh 10 1 100 Extend 11 1 111 ExtendO 11 0 Q Specific Sequencer from before Sequencerb control unit from last lecture cCalled microPC or tire Vs state register Code Name L39th o f Next uaddress 0 dispatch ROM uaddress 1 e dispatch seq unnnnn DDDiUD nmim iUEIEIM immi Microprogramming Pros and Cons o E ase or design 0 Flexibility 0 Easy tn arlapt tn ehaneesin organieation timing technnlngy 0 Can malee ehaneeslatein design eyele or even in therielrl 0 Can implement very powerrul instruction sets just more control memory 0 Gmerahty 0 Can implement multiple instruetion sets an samemaehine 0 Can tailor instructinn set tn zpplicztinn o Compatibility 0 Many organieations same instructinn set 7 Control unit in same chip as data path so can t replace ROM ROM not raster than RAM so not much raster than 1st level instruction cache PLA smaller d thereroreraster than ROM 7 Simpler instruction sets popular now 7 CAD tools rast computers allows simulatio correct control Legacy Software and Microprogramming IBM bet company on 360 Instruction Set Architecture ISA single instruction set for many classes of machines 8bit to 64bit Stewart Tucker stuck withjob ofwhat to do about software compatibility If microprograrnming could easily do same instruction set on many different microarchitectures then why couldn t multiple microprograrns do multiple instruction sets on the same microarchitecture Coined term emulation instruction set interpreter in microcode for nonnative instruction set Very successful in early years of IBM 360 it was hard to know whether old instruction set or new instruction set was more frequently used Thought Microprogramming one inspiration for RISC If simple 39nstruction could execute at very high clock rate If you could even write compilers to produce microinstructions If most programs use simple instructions and addressing modes If microcode is kept in RAM instead of ROM so as to fix bugs If same memory used for control memory could be used instead as cache for macroinstructions Then why not skip instruction interpretation by a microprogram and simply compile directly into lowest language of machine microprogramrning is overkill when ISA matches datapath 11 Conclusion Disadvantages of the Single Cycle Processor 0 Long cycle time 0 Cycle time is too long for all instructions exceptthe Load Multiple Cycle Processor 0 Divide the instructions into smaller steps 0 Execute each step instead ofthe entire instruction in one eye1e Partition datapath into equal size chunks to minimize cycle time s lUlevels oflogicbetweenlatches Follow same 5step method for designing real processor Conclusion Control is specified by nite state diagram A Laptuieu u simple increment amp branch elds datapath control elds Control design reduces to Microprograrnming Control is more complicated with complex instruction sets restricted datapaths see the book Simple Instruction set and powerful datapath 2 simple contro l could try to reduce hardware see the book rather go for speed gt many instructions at once