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# SPECIAL TOPICS PHYS 594

UCSB

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This 98 page Class Notes was uploaded by Hailey Halvorson on Thursday October 22, 2015. The Class Notes belongs to PHYS 594 at University of California Santa Barbara taught by Staff in Fall. Since its upload, it has received 61 views. For similar materials see /class/227124/phys-594-university-of-california-santa-barbara in Physics 2 at University of California Santa Barbara.

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Date Created: 10/22/15

Symbolic Scheduling Aravind Vijayakumar ECE 594 Winter 2004 February 9 2004 Overview Data structures BDDs Symbolic Scheduling Automata based scheduling Image computation Control dominated scheduling Truth tables Logic Representation S o P P o S factored forms Boolean networks BDDS Binary Decision Diagrams First suggested in 1959 binary decision programs of CY Lee7 Current form trace to Akers1 Popularised by Bryant 3 2 Nice introduction by Minato 8 What is a BBB Binary Decision Diagrams BDD for a function f is a rooted DAG With vertex set V Two types of vertices internal value Value vertex has value 0 or 1 Internal vertex v ltgt variable varv denoted v For every v lov hiv E V Function at a vertex v is fv TJ flov v fhi V 16 10v fvlvo hiVfvlv1 f930U1VU3 Figure 1 Example BDD Reduced BDDS 0 Not very useful so far 0 Apply 2 reduction rules If 10v hiv eliminate v If 10v 10w and hiv hiw share them f 90 931 V 933 Eliminate Redundant Figure 2 Redundant nodes removed f 90 931 V 933 Share Subgraphs I 3 E Figure 3 Isomorphic subgraphs shared Reduced Ordered Binary Decision Diagrams 0 What s the big deal about ROBDDS 0 Pros Canonical Cheap implementation of some useful operations gtxlt Equivalence checking gtxlt TautologyFallacy gtxlt Complementation if package has complement edges Result of binary operation on 2 BDDs is bounded by the product of their sizes 10 ROBDDS The cons 0 Functions may be hard to represent Symmetric functions linear to quadratic Integer addition linear to exponential Integer multiplication always exponential o BDD size is extremely sensitive to variable order 11 f mogul V 93213 V 93411 Figure 4 Effect of Variable Ordering 12 Succeeding Material From 0 Intro to Algos 4 0 Logic Synthesis and Veri cation Algos 5 o Symbolic Sched Techniques 9 o Automata Based Symbolic Sched 6 o ECE 256B class notes 13 Symbolic Scheduling 9 Some similarity to ILP Use input target length derive ASAP ALAP bounds from that Bounds used for speeding up the algorithm Denote Sj ASAPQ Lj ALAPj Z is Boolean OR ing H is Boolean AND ing 14 Problem Formulation o Boolean formulation 0 Represent schedules by st st 1ltgt opjin steps 0 Constraints represented by Boolean functions Uniqueness Precedence Termination Resources 15 Example Uniqueness Constraint 0 Denote st Sj s OIij SltLj H 6st dimest 2 6st oIfSLj 0939 H kest k est iEst 16 What is Pj Control representation by guard variables Set of ops are control ops with associated binary guards Gi Operation j associated With guard function I j I j represents the control cases under which j must be scheduled 17 Example CDFG Figure 5 Example of a CDFG 18 Main Features Exact delivers all solutions under modeling assumptions Modeling assumptions subsume large variety of code motions Boolean constraints not linear BDD may explode 19 AutomateBased Symbolic Scheduling 6 Operations modeled as NFAs The NFAs are composed Via Cartesian product Compound NFA pruned for dependence resource constraints Reachable state analysis determines schedule Key point No need to maintain Whole trace 20 Example Models 0 11 0 0 0 o o IOzinbusy Statezdone r Signals inbusy Figure 6 Single cycle 2 cycle pipelined Operators 21 Example Models Very general 7 can describe any sequential behaviour Busy signal for resource constraints Models provide saturating done signal to indicate operand presence To create dependence 7 make done of one op the input of another Completion of some operations signi es termination 22 Example DFG Compound NFA a Data ow b Schedule states Figure 7 Simple DFG Compound NFA 23 Unconstrained Scheduling Forward States Reached Back Prune compH geaalags 2 Eaal a2 Eaal a2 850 a2 saalagsc Table 1 Resource constraint free scheduling a1 GEE a1 a2 SE a1a28C 24 Resource Constrained Scheduling Forward States Reached Back Prune lbwwp 1 2 Ea1 2 E a1 2 E 7 233a1 2Eaal agscnl 785 a1a2 5a1285 T QEE Jla gga jla2 5a1 85a1a285 a1 agsc 1EEaalmnlag nl saalags nlagsc a1 a2 8 c Table 2 Schedule With Constraint 0f 1 ALU 25 Some Observations Self loops present in each state 7 lots of choice All possible schedules maintained Can accomodate I O protocols easily Need to worry about ordering 26 Relations Binary relation R on sets A B is a subset of A X B If a b E R we write aRb If we say relation R is on A we mean R is a subset of A X A We ll be interested in relations of the form R g Bquot X 15 27 Image PreImage Consider a mapping 6 Z gt 9 Let 26 Q 1 Q 9 The image of X by 6 is 626 de ned as 596 y E Oiy WW 6 X The prez39mage 0f 3 by 6 is 6 10 de ned as 5 10 96 6 y I 512 E 3 The image of I is called the range k 28 Relation of 3 Mapping For the mapping 6 I I gt O we can construct a relation R R QZX O E z 00 6ii EZ Equivalently R may be de ned as R E z 0z 6 100 E mngeZ 29 BDD Representation of Relations Consider a relation R g Bquot X 15 LethBquotngBm Construct 90749137 1 ltgt a R 37 This is a BBB on n m variables with a path to 1 for every 9337 st 937637 Note that the BDD for the image of 26 Q Bquot is just 39626 907quot 30 k De nition of Automata Transition Relation NFA 5 tuple 13306fgt 6 I X S I gt 25 We do the following Encode input alphabet I using E bits Encode the states using m bits In particular suppose we associate with the machine the following variables 90 901 ml for the input variables 19 p1 pm for the present state variables 71 n1 nm for the next state 31 N Transition Relation We can now de ne the transition relation for 6 described earlier 6Rf 1 ltgt 7 E Mfg SR is a BDD on E l m l m variables Let 26 Q 15 over 90 and 73 Q 15 over 19 Then N 31906 73 SR is a BBB representing the set of states reachable in one cycle from 73 under inputs X k 32 MapBack Relation We can de ne the BDD function MB as MB H mew 193m Then given N Q 15 on n 73 SANA MB maps back the next state variables on to the present state variables k 33 Reachable State Computation Start with SO all Operations not done Compute St 3n3pSt SR MB Continue till in some time step t St f 73 9 Then prune back as St1 St1 3n3pSt MB SR 34 Composing NFAS NFAs encoded over different bits combine linearly Dependences enforced as mentioned earlier Resource constraints imposed on busy signals By themselves ne i may blow up When combined 35 Finis 36 References 1 S B Akers Binary decision diagrams IEEE Trans on Computers C 2765097516 June 1978 2 K S Brace R L Rudell and R E Bryant Ef cient implementation of a BDD package In Proc of the 27th Design Automation Conference pages 40745 1990 3 R E Bryant Graph based algorithms for boolean function manipulation IEEE Trans on Computers C 3586777691 August 1986 4 T H Cormen C E Leiserson and R L Rivest Introduction to Algo rithms Prentice Hall of India Pvt Ltd 7th Indian edition 1990 5 G D Hachtel and F Somenzi Logic Synthesis and Veri cation Algorithms Kluwer Academic Publishers 1996 36 1 ECE 594 Transaction Based Languages Sirisha Gadepalli Transaction I Exchange of a data or an event between two components of a modeled and simulated system I A data transaction can be a single word a series of words or a complex data structure that is transferred over a bus between system components I An event transaction models synchronization aspects that ensure correct operation of the system Transaction level modelling of 80C with SystemC 20 Transaction I A transaction is a single conceptual transfer of high level data or control between the test bench and the Design Under Veri cation DUV over an interface I It is de ned by its begin time end time and attributes I It can be as simple as a memory read or as complex as the transfer of an entire structured data packet through a communication channel The TransactionBased Veri cation Methodology Why we need TBLs I Increasing size and complexity of ICs I Emergence of SystemonChip SOC I Uni ed modeling environment for both hardware and software components of a big system I An intermediate abstraction level between functional description and cycleaccurate speci cation I Architecture evaluation I HardwareSoftware Partitioning I Coverif1cation of hardware and software I System Design Abstraction Levels neci ca nn Model Imnlemenm nn Model Transaction Level Modeling in System Level Design Transaction Level Models u mamx mlwlacv z slavemlena z 3 albu nnlEnace Bus Arbitration Model u maslarmlenaca 239 51M nlsvram 3 amnmmmram 4 mame music menace 2 slam menace 3 album menace TimeAccurate Communication Model CycleAccurate ComputationModel l Transaction Based Speci cation I Model of hardware system components at a high level of abstraction I Details of communication among computation components are separated from the details of the their implementations I Cyclespeci c and pinspeci c details not included unlike RTL I Contains processes ports and abstract channels Advantages I More intuitive I Modular I Faster to simulate I Easy to Change I Easy to reuse Languages I SystemC I SystemVerilog I TBS SystemC A set of classes that extends C libraries Can describe Untimed Level Transaction Level Register Transfer Level Interfaces declare access methods that channels provide Ports implement access methods declared Within one or more interfaces Channels enable a module access a channel s interface I Communica on in SystemC Synopsys Example FIFO write interface class class writeif39 virtual public sci12terface public39 virtual void write char 0 virtual void resetO 0 read interface class class readif 39 virtual public scin terface public39 virtual void rea d clzar amp 0 virtual int 11 uma vailableO 0 class fo 39 public sccha1111e1 public WIitei public readif publicf f oCscmodule11ame name scclza1111e111ame nume1ements0 rst0 1 139mpeme11tation of witeifmetlzod void wzite lzar c if 11ume1eme11 ts max wait 39eacLeven t data rst nume1eme11ts max c12ume1eme11ts WIiteeve11t120ti60 imp1eme11tati011 ofreaaL 39metbod void read char ampc if11ume1eme11ts 0 waitW139iteeve11t c data rst 39 11am e1eme11 ts L rst rst 1 max readeve11 t110t139670 private 39 char da tam ax int nume1eme11ts rst scevent WIiteevent readeve11t class producer 39 public scmodule public scportltwriteifgt out SC39 CTORODroducer SOL THREADQroduceZ39 void produceO const clzar str quothello worldquotj leile stroutgtWrite str call in terz ece method class consumer 39 public scmodule public scportltreadifgt in SC CTOR 0011s umer SQ THREADcousumef void consumeO 1 char 0 While true ingtreadci cout ltlt 0 ltlt fluslzf class top 39 public scm0du1e publjcf fe f anst producer 50r0d139nst consumer cons1nst top Cecm0duenan2e name 39 sc1n0du1ena1ne f0139nst neW fo ijoJ 91 pr0d139nst new producer 39ProducerI 9 pr0d139nstgt0ut fb1nst cons139nst neW consumer Consumerl 9 cons139nstgt1n fanstZ39 ll 139ntscn2a139n int argc char argv top t0p1quotT0p1 9f scstart391f return 0 SystemVerilog I C data types to provide better encapsulation and compactness of code I Interfaces to encapsulate communication and facilitate Communication Oriented design I Literal time values literal array values literal structures and enhancements to literal strings I New Basic Data Types String Dynamic arrays Mailbox and Semaphore Event Variable Class I More compact code fewer bugs AcceIera s Extensions to Veriog Interfaces in SystemVer og interface intt bit AB byte CD lcgic EF endinte r int w r modA mlqw modB m2w An interface can Bantam module media tint ilh anything that could be in a andmdule module except other module modB mt 11 mndue defml tnnns or endmodule Instances System Veriog for Design TBS Nondeterministic specification language Abstraction level between a pure functional unscheduled behavioral format and a cycle accurate fully scheduled rendition I TBSIR a CDFG abstracts functionality u SC NFA sequential constraints on data transfers 1 RC resource constraints Possible to synthesize different designs with same functionality but different schedules I Example ALU module ALU shared busy resource trans subtractt a b 39gt c I 5115711521112 bV8 a 1 signal out 9V 8 c dependence zhterfaceaampbu3 bampbusy campbusy Transaction Based Veri cation tranaactinm doRea add JEFF data ICEIF design pmcdoRead pmudo Tirite teat tramactim vc mtmn model TEN The TransactionBased Veri cation Methodology l A Case Study I SystemC specification I Hierarchical re nement from TL to RTL I Simulation carried out for bubblesort algorithm TL an order of magnitude higher than RTL rue I Similar number of LUTs Figure l RB processor implemented with 3 modules 39 lExeculion Unil Register Bank and Memory Unit and 3 and FFS When SyntheSIZed channels lFIagsChannel Regscnannel and Memory on FPGA Channen Boldlaee namesare inslances others are classesr lllrroryCimnE E From VHDL Register Transler Levelto SystemC Transaction LevelModeling Current Tools I Synopsys El Design Compiler VCS HDL Compiler LEDA El SystemVerilog Catalyst Program I Mentor Graphics El Scalable Veri cation platform VStationTBX I Cadence Future Work I Industry Standards I Automated codesign tools for El HWSW partitioning a TL gt RTL re nement El Veri cation between different abstraction levels Conclusion I Transaction Based Languages CI DUDE provide an intermediate abstraction level between untimed and cycleaccurate speci cations of the design Separate the computation models and the communication channels between them Increase simulation speed Help in design decisions at an early stage Provide reusable hierarchical modules Provide golden testbenches ECE594A notes set 4 More on High Frequency Ampli er Design Mark Rodwel University of California Santa Barbara rodwelleceucsbedu 8058933244 8058933262 fax class notes ECE594A rodwell University of California Santa Barbara copyrighted Commonbase stage by MOTC Cbe Cob CL E J J i i RL Rgen Rbb Rbb Cbe Cob CL VVVT J RL RgenT 394 lt Rbb gt j C R l Rgen a1 be bb R re rgen rbe genre RL ch Rbb 1 RL CLRL e gen 02 note that becuase al a2 are independent of location of input and output the form is identical to that of CE stage Note also the Miller multiplication effect with Rbchb class notes ECE594A rodwell University of California Santa Barbara copyrighted Definition of Sparameters El ii imi S parameters are rigorously de ned in terms of the voltage waves on transmission lines connected to the device under test b1511 S12a1 b2 521 522 a2 where the a39 s and b39 s are the wave amplitudes class notes ECE594A rodwell University of California Santa Barbara copyrighted Relating amplifier Gains to Sparameters821 These definitions allow us to develop a simpler way of finding the S parameters 52 gen denerator 2 load 20 Which is simply how much bigger the signal became upon insertion of the amplifier in the 50 Ohm system 321 is called the insertion gain class notes ECE594A rodwell University of California Santa Barbara copyrighted Relating amplifier Gains to S parametersS12 gen Z 22106161 220 generator class notes ECE594A rodwell University of California Santa Barbara copyrighted Relating amplifier Gains to S parametersS11 and 822 Vout Zin Zout 81 l and 822 can be directly related to input and output impedances Z Z 1 S11 2 WhereZm 2 Zn Zin ZO1 ZloadZZO Z 1 S22 2 Where Zom Zom ZoutZ01 Z rworzZO gene in practice we do not need to plug into the formulas knowing the Z in tells us the S11 becuase the formula is one to one and is neatly represented by the Smith chart class notes ECE594A rodwell University of California Santa Barbara copyrighted Relating amplifier Gains to S parametersS11 and 822 AA NJ r N F U U S11 2 ZmZO1 Where Zm Zm Zm Zo 2105101220 freq 1 000GHzto 1000GHz S M Where Z Z 22 Zom ZO 7 out out Z Z we do not need to plug into the formulas the Smith chart is a plot of this formula so the Smith chart plots S i and Z in at the same time class notes ECE594A rodwell University of California Santa Barbara copyrighted Example of working with S parameters mZO 21 2 1 jooCmZo S11 ZWWhGI G Zm 1jooCm 2m ZO1 S22 2 M where Zout in nity out S12 2 0 easy class notes ECE594A rodwell University of California Santa Barbara copyrighted Example of working with S parameters 0 21 1 12 1ijZO2 20 ZO 0C S ZmZO 1 ijZOZ WhereZ Z L ZMZO1 1wCZO2 OjCUC 522 ijwhere Zom ZO ZoutZO1 this illustrates the importance of quotZn ZLZ H o etc class notes ECE594A rodwell University of California Santa Barbara copyrighted Why do we care about impedances matched to 50 Ohms Port P1 Qf FBA TU Ez arlFBA P2 Num1 Z500 Ohm Num2 E 360 F10 GHz 32 3 T w 352 31 FWD ROW spa idcisw mA 5 Vdc5 v 30 n O a 29 4 2 s N 21 0 nF Num2 a 28 Port c E Kim 1 Eli OnF 390 27 n 2 R2 26 BJTWNPN Rite 33M 25 AreaAef AreaAsw Region I Region mp27 Temp27 24 Modenoniinear c Modenoniinear o 39H39o39mz39o39quot 39dquotLi39dquot 396quot liquot396quot 6quot36quotioo freq GHz Standing waves on transmission lines cause gain phase ripples of the form 1 Z SZ L eXp j 2 fr1 Either we must have short transmission lines or the lines must be C3 31 0 HF well terminated class notes ECE594A rodwell University of California Santa Barbara copyrighted Why do we care about impedances matched to 50 Ohms 30 ohm IC core 50 ohm interface with high interface Zm50 Z interfaces Zout50 If IC has small dimensions we can use high z internal interfaces and just interface to e g 5 0 Ohms at chip boundaries or in some cases between major circuit blocks on wafer class notes ECE594A rodwell University of California Santa Barbara copyrighted why do we care about transmission lines mat 39 L RI eizlcnsilim in E m uutput gain comm 39 i H V0 tantrai 39 39 a EurQuadrant A A multiplier input 3 ms quotarea There are times when we would like to ignore transmission lines and S parameters If the IC has interconnects which are short then we can treat all interconnects as lumped This means we can ignore standing waves on the lines But we must be aware that C Tim2011 line 2 TM ZO hence a short line can be modeled as lumped but its parasitics cannot be ignored line class notes ECE594A rodwell University of California Santa Barbara copyrighted Effect of lumped wiring parasitics on IC performance J J RL RL Q Here we can model these short lines as lumped Ignoring B T parasitics Cline Z1139ne Z 0 9 Lline Z1139ne Z 0 9 And we get an RC charging time of Zwiring ClineRL Since the gain is ngL kT qIRL designing for low power low 1 means designing for high RL and hence interconnect capacitance becomes more important class notes ECE594A rodwell University of California Santa Barbara copyrighted Effect of lumped wiring parasitics on IC performance CD RL RL Once we have studied EF frequency response in detail we will understand that Lline Tline Z can have substantial effect upon the EF stability and pulse response 0 class notes ECE594A rodwell University of California Santa Barbara copyrighted Getting more bandwidth At this point we have learned basics MOTC etc How can we get more bandwidth Resistive feedback transconductancetransimpedance emitterfollower buffers benefits and headaches emitter degenerationbasics emitter degeneration and area scaling ftdoubler stages distributed amplifers ftdoubler stagessimple RL power with Darlington broadbanding peaking with LC networks distributed amplifiers examples class notes ECE594A rodwell University of California Santa Barbara copyrighted Broadband gain blocks quotworlds simplest amplifierquot 94545 a Examine a cascade of simple differential pairs For the differential signal path this becomes a CE stage cascade If we model each BJT as a simple gm Cm combination the gain per stage is ngC the bandwidth is 1 ZERCCm and the gain bandwidth product is gm Z Cm 2 ft This is the origin of the quot f7 limitquot We can do much better class notes ECE594A rodwell University of California Santa Barbara copyrighted Broadband gain blocks quotworlds simplest amplifierquot 145 Te e e Let us think this through Transistors exist to give us transconductance gm An input voltage is converted into an output current Our simplest design strategy is to convert this output current back into a voltage using a resistor hence the gain relationship Transconductance always comes at the price of input capacitance by the ratio C m 2 gm 279 class notes ECE594A rodwell University of California Santa Barbara copyrighted Resistive feedback stages I gain and impedance Rf Rf gm gm This is a more sophisticated way of converting gm into voltage gainnodal analysis to be done in lecture Per stage gain of A negative with input and output resistances of R are obtained if we set nout gm 1A12in0ut and Rf 1A12in0ut39 class notes ECE594A rodwell University of California Santa Barbara copyrighted Resistive feedback stages I bandwidth and gainbandwidth RfRfRfRfRf w w w w w 9m 9m 9m gm gm Rf Rf Rf WE WI 9m 1 gm e 5 9m Since gm 2 1 14 in and C 2 gm 27zf f3dB 1275Rmouz 2C gm C1 A f3dB 2ft 1 A Note that for A gtgt 1 this is twice the bandwidth of a simple CE stage class notes ECE594A rodwell University of California Santa Barbara copyrighted Why have we nearly doubled the bandwidth The resistive feedback has provided output impedance of RmOW without losing signi cant output current in a physical loading resistance We need roughly 12 the gm to obtain the desired gain at a given impedanceso we get 12 the C and hence twice the bandwidth class notes ECE594A rodwell University of California Santa Barbara copyrighted Variations on resistive feedback 41 39 g resisitive loading ELIIE g 3958 gmblocks BEL resistive feedback We can use sets of transistors to build the gm block This block can then be used with either resistive loading or resistive feedback to build an ampli er class notes ECE594A rodwell University of California Santa Barbara copyrighted Feedback with buffer 0 0 Rf Av1 Rf 0 gm This is often used for DC bias reasons But also the required gm is now gm 2 A Rim0m not 1 A This improves bandwidth for low gain stages but then we pick up additional capacitances from the EF stage class notes ECE594A rodwell University of California Santa Barbara copyrighted Resistive feedback as 50 Ohm gain blocks R DC V DC SRC2 R3 s 1 dcsw mA R50 kOhm VdC5 V II AAA I I C Port 02 P2 C10 nF Num2 Port C P1 01 Num1 0 10 nF VAR R VAR Aef8 23R e61 comp105 BJTNPN Astage5 BJT T2 ASW56 Modelhbt J9f1 AreaAef AreaAsw JSW1 Region Region efAef Jef Temp27 Temp27 ISWASW sz Modenoninear c Modenoninear RbIaSef250ef C3 Rourrentsc1450Isw 010 nF Rbiascs250Isw Ree125Astagecomp 50Asw 26Isw Ree2501Astagecomp 50Asw 26Isw Rf501Astage Note the gain relationships class notes ECE594A rodwell University of California Santa Barbara copyrighted High Speed Amplifiers U93quot PK Sundavavajan 18 dB DC50 GHZ 15 821 m 5 El SM 75 4m 45 S22 m 2m 3m 4m 5 Gains dB N m 2 an AU 5 6D 7 2 Frequency GHZ dass notes ECE594A rodweH Unwersm of Cahforma Santa Barbara Cowrwgmed 2 stage differential amplifier First stage is resistively terminated second stage has resistive feedbackthis is because first stage is allowed to limit or can have AGC applied either of which would violate the feedback gainimpedance relationships class notes ECE594A rodwell University of California Santa Barbara copyrighted CherryHooper GmZt amplifier Very popular feedback varaint Here input output impedances are not consistent Input impedance of 2nd stage is Rm 2 Re Rf1 gm2R01gm239 Transimpedance of second stage is derive these Zn 2 Rf gm Gf GC Rf39 Overall gain is Av ngZTZ class notes ECE594A rodwell University of California Santa Barbara copyrighted CherryHooper GmZt amplifier Note to Rodwellwork impedances and gains both carefully and by backof envelope why is first order time constant so small class notes ECE594A rodwell University of California Santa Barbara copyrighted CherryHooper GmZt amplifierIimiting behavior If 11 lt 12 derive this amplifier will always limit on the gm stage not the Zt stage hence large signal operation maintains low impedances hence short time constants provided by feedback class notes ECE594A rodwell University of California Santa Barbara copyrighted CherryHoopers inclusive of DC biasing work through DC conditions in lecture class notes ECE594A rodwell University of California Santa Barbara copyrighted CherryHooper bandwidthzero39th order m1 By 1nspection 9 92 CL a1 CbeZ CL gm2 a2 RLCMCL gm2 work more detailed example in lecture Note immediately that first order time constant is small second order time constant is NOT Much more detailed analysis in Hitachi paper class notes ECE594A rodwell University of California Santa Barbara copyrighted GmZt amplifier understanding time constant behaviour Rf N This has input and output impedance of a 1 R0 1 gm a T l a TT a 1quot So each capacitor has charging time constant of C gm1 Rf Rf Rf 151 a C2 T a a T a Shorting C2 makes the C1 charging time constant 2 ClRf so terms in a2 are of the form C2 gm C1R f class notes ECE594A rodwell University of California Santa Barbara copyrighted CherryHooper bandwidthwith ch 00b 00b C Cb Rf Rf V Rf gm 1 gm2 gm3 gm gm1 Cbe2 gm2Vi CLCbe3 a1 CbeZ gm2 Cbe3 gm2 chRf a2 CbeZ gm2Cbe3Rf CbeZ gm2chRf Cbe3 gm2chRf note that ch has reduced bandwidth and has improved damping class notes ECE594A rodwell University of California Santa Barbara copyrighted Darlingtons 1 Why notjust use emitter followers to buffer the stage input capacitances class notes ECE594A rodwell University of California Santa Barbara copyrighted Darlingtons 2 R1 RL R1 RL Q1 Rbb2 Cbe1 Cbeg Taking Rex O and 6 2 oo a1 Cbe2Rbb2 rel ch2 RIM re11 ngRL RL ch1Rbb1 R1 Cbe10 a2 CbeZCbe1Rbb2 21le Rbb1re1 K721 Rbbz class notes ECE594A rodwell University of California Santa Barbara copyrighted Darlingtons 3 ch1 R1 RL Rbb2 fr Cbe1 Cbe 2 Note the greatly reduced charging time for Cbe2 a1 Cbez Rbbz rel inStead Of a1 Cbez Rbbz R1 This is the motivation for the Darlington commonly given in introductory texts But a more detailed consideration reveals that l the charging time for C be 2 is at a minimum Cbeszb2 more on this later and 2 that Che2 RM2 R1 must reappear in the second order time constant with consequent reduction in circuit damping class notes ECE594A rodwell University of California Santa Barbara copyrighted Darlingtons R1 RL Clearly exact problem is hardlets look at effect T of C be alone all other B T parasitics are zero Theane1 Cbe2 a1 Cbe2rel a2 CbeZCbelrelRl If we have a cascade of stages then note that RL 2 R1 and that gain 2 A R1 Md The damping factor is proportional to the ratio 611 AE Note we can make the first order time constant very small but not the second order time constant work through attempts to broadband response result in loss of damping class notes ECE594A rodwell University of California Santa Barbara copyrighted Darlingtons improving the damping Addition of Ree has 2 effects The Ql EF gain is reduced a1 Cbel Rbbl Avef 39 39 C1362 Rbe Ree R a2 Cbe1Rl Rbbl 1 Avef Cbe2 Ree R1 Rbbl So the terms in al associated with Cbel are increased More importantly terms in a2 associated with Cbe2 e g R2 are reduced due to the parallel loading of R66 class notes ECE594A rodwell University of California Santa Barbara copyrighted

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