Operating Systems COP 4600
University of Central Florida
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This 86 page Class Notes was uploaded by Luisa Beer on Thursday October 22, 2015. The Class Notes belongs to COP 4600 at University of Central Florida taught by Euripides Montagne in Fall. Since its upload, it has received 42 views. For similar materials see /class/227457/cop-4600-university-of-central-florida in Computer Programming at University of Central Florida.
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Date Created: 10/22/15
UCF School of Electrical Engineering ampComputer Science COP 4600 Operating Systems Fall 2004 Syllabus Instructor Euripides Montagne Tele 8232684 emaileurip csncfedu Lecture meetings MW 1200 Noon 7 ll5pmENG 427 Office hours CSB 239 MW 300 p m 7 500 p m and TR 200 p m to 400 pm TA Cheng Hao email haocheng csncfedu Office hours TBA CCI 20239 Course Outline The goal of the course is to teach fundamentals concepts and design principles of operating systems Course Topics Operating systems structure Process management Process scheduling Memory Management Virtual memory lO system Performance Evaluation Prerequisites COP 3530C 7 Computer Science III COP 3402C 7 System ConceptsProgramming Proficiency in C and Familiarity with UNIX If you have not satisfiedall of the above prerequisites you do not belong in this class and have little chance ofpassing Reference Guide The textbook for the course is H M Deitel P Deitel and D Choffnes Operating Systems 3ml Edition Prentice Hall 2004 We will cover Chapters 113 You are responsible for the material contained in all of those chapters even if it is not discussed in class Time permitting we may cover parts of Chapter 19 Style of Class Meetings Class meetings will not consist of traditional lectures with the instructor doing most of the talking and the student doing most of the listening Rather meetings will consist of discussions on each topic and the instructor will help guide the discussion by asking questions Grading Policy a 20 Exam 1 7 closed book closed notes exam given in class a 20 Exam 2 7 closed book closed notes exam given in class a 25 Final Exam 7 closed book closed notes comprehensive exam given during final exam week Note You must score at least 60 on this exam to pass the course a 25 Programming project7 a large multi part simulation of a multiprogramming operating system Written in C on a UNIX system this project is not easy but can be done in the time allotted The grade for this project will be divided between your C code one or more demonstrations of your project your documentation and quizzes given on selected topics from the project a 10 Concurrent programming assignment Letter grades 90100 A 8089 B 7079 C 5069 D Below 50 F Note Any academic dishonesty including but not limited to Cheating copying andor plagiarism with respect to any exam or assignment in this class will result in a grade ofF following by the usual procedures for dealing with such behavior as describe in the UCF GoldenRule 39 a handbookfor Students The Semester Plan Tentative Aug 26 Operating Systems Fundamentals Aug 31 Computer System Structure Sept 02 lnterrupt Handling 07lnterrupt Handling Sept 09Operating System Structure Sept l4 Processes and Threads Sept 16 Process Synchronization Sept 21 Process Synchronization Sept 23 Process Scheduling Sept 28 Review Sept 30 First Midterm Exam Oct 05Memory Management Oct 07 Memory Management Oct l2 Virtual Memory Oct l4 Virtual Memory Oct 19 10 structure Oct 21 Disk Scheduling Oct 26 Review Oct 28 Second Midterm Exam Nov 02 File System Nov 04 Resource Allocation and Deadlock Nov 09 Resource Allocation and Deadlock Nov 16 7 System Performance Evaluation Nov 18 7 System Performance Evaluation Nov 30 Review Dec 02 Final Exam 1 D E COP 4600 Programming Project Fall 2004 This project is divided into 4 pars to make it more manageable Details will be given out well before the due dates for each partthe parts of the project are calledobjectives This project must be written in Cnot OH on a UNIX system The standard for this class will be the Sun Sparc system in the main computer lab called Olympus You are welcome to write and test code on some other system ifyou wish but it will be graded on Olympus and if it does not work there it does not work You will be given an Olympus account and once the project has begun should check your email regularly for updates To pass this course you must successfully complete objectives 1 2 and 3 and the concurrent program No exceptions Each objective will have a due date and points will be subtracted for submission after that date Also after each due date some evaluations ofyou progress will be made This may include a walk through of your code with the instructor or grader a quiz on the objectives that was just completed including questions about code data structures andor algorithms or a short written description of the purpose and implementation of the objective Details will be handed out with each objective andl reserve the right to change the method of evaluation at any time In general this project will give you a better understanding of the data structures and control flow of a multiprogramming operating system and also provide you with experience in developing and debugging a complex software project Lets make this clear when working on the project you are allowed to talk to other students about programming concepts C syntax and general solutions to problems algorithms or questions about the project instructions but you are not allowed to share exchange or copy code Both the source and the recipient of any exchange of code are equally at fault Important Dates Classes Begin August 23rd Withdrawal Deadline is October 22 d Classes End December 40 Summer Holidays are Labor Day Sent 6 Veteran s November 11quot Thanksgiving Nov 25 27 Interrupt Handling by Euripides Montagne University of Central Florida Outline 1 The structure of a tiny computer The interrupt mechanism 9599J Interrupt Types Euripides Montagne University of Central Florida A program as an isolated system The hardware software interface H VonNeumann Machine VN MAR MEMORY 1R IOPI ADDRESS MDR Euripides Montagne University of Central Florida 3 Instruction Cycle Ill 9 Instruction cycle or machine cycle in VN is composed of 2 steps 39 1 Fetch Cycle instructions are retrieved from memory 2 Execution Cycle instructions are executed A hardware description language Will be used to understand how instructions are executed in VN Euripides Montagne University of Central Florida 4 De nitions l lll 9 IP Instruction Pointer is a register that holds the address of the next instruction to be executed MAR Memory Address Register is used to locate a speci c memory location to read or write its content 9 MEM Main storage or RAM Random Access Memory and is used to store programs and data Euripides Montagne University of Central Florida 5 De nition of MDR MDR Memory Data Register is a bidirectional register used to receive the content of the memory location addressed by MAR or to store a value in a memory location addressed by MAR This register receives either instructions or data from memory Euripides Montagne University of Central Florida 6 De nitions Cont l1l 0 IR Instruction Register is used to store instructions 9 DECODER Depending on the value of the IR this device Will send signals through the appropriate lines to execute an instruction 39 A Accumulator is used to store data to be used as input to the ALU 0 ALU Arithmetic Logic Unit is used to execute mathematical instructions such as ADD or MULTIPLY Euripides Montagne University of Central Florida 7 Fetch Execute Cycle In VN the instruction cycle is given by the following loop Fetch Execute In order to explain further details about the fetch execute cycle the data movements along different paths can be described in 4 steps Euripides Montagne University of Central Florida 8 Data Movement 1 Given register IP and MAR the transfer of the contents of IP into MEMORY MAR is indicated as MARIP I OPI ADDRESS 4 MDR Euripides Montagne University of Central Florida Data Movement 2 0 To transfer information from a memory locatlon to the register MDR we use MEMORY lDRMEMMAR A 0 The address of the memory I CPI ADDRESS H MDR location has been stored previously into the MAR register Euripides Montagne University of Central Florida 10 ll Data Movement 3 Il To transfer information from the MDR register to a memory location we use MEM MAR MDR gt see previous slide for diagram The address of the memory location has been previously stored into the MAR Euripides Montagne University of Central Florida 11 l 4 Instruction Register Properties The Instruction Register IR has two elds Operation OP and the ADDRESS These elds can be accessed using the selector operator Euripides Montagne University of Central Florida 12 ll39 l Data Movement 4 9 The operation eld of the IR register is sent to the DECODER as DECODERGIRDP The Operation portion of the eld is accessed as IROP DECODER If the value of IROPO then the decoder can be set to execute the fetch cycle again Euripides Montagne University of Central Florida 13 Data Movement 4 Cent DECODERGIRDP V MEMORY l OPI ADDRESS l4 l MDR Euripides Montagne University of Central Florida 14 Instruction Cycle l A The instruction cycle has 2 components Fetch cycle retrieves the instruction from memory Execution cycle carries out the instruction loaded previously Euripides Montagne University of Central Florida 15 OO Fetch Cycle 1MAR 61F 1C0py contents of IP into 2MDR Load content of memory 3 JR eMDR location into MDR 4IP GIP1 3 Copy value stored in 5DECODER IROP MDR into IR 4 Increment 1P register 5 Select Instruction to be executed Euripides Montagne University of Central Florida 16 Execution 01 LOAD MAR IRADDR 1 Copy the IR address MDR MEMMAR value eld into MAR 2 Load the content of a le k A MDR memory location into DECODER 00 MDR 3 Copy content of MDR into A register 4 Set Decoder to execute Fetch Cycle Euripides Montagne University of Central Florida 17 Execution 02 ADD 1 MAR 61RADDR 1 Copy the IR address 2 MDR eMEM VIAR value eld 1nto MAR Load content of memory 3 A A MDR location to MDR 4 DECODER 00 3 Add contents of MDR and A register and store result into A 4 Set Decoder to execute Fetch cycle Euripides Montagne University of Central Florida 18 le k Euripides Montagne Execution O3 STORE MAR IRADDR 1 Copy the IR address value 2 Copy A register MEMMAR MDR contents into MDR DECODER 00 3 Copy content of MDR into a memory location 4 Set Decoder to execute fetch cycle University of Central Florida 19 1 STOP Euripides Montagne Execution O4 END 1 Program ends normally University of Central Florida 20 Instruction Set Architecture 00 Fetch hidden instruction 01 M MAR 11 MAR IRAddress MDR MEMMAR MDR 39MEMlMAR IR MDR A MDR 1P 1P1 DECODER00 DECODER IROP 03 St0139e 02 Add MAR IRAddress MAR IRAddress MDR A MDR MEMMAR MEMMAR MDR A A MDR DECODER 00 DECODER 00 04 Sm 1 Euripides Montagne University of Central Florida 21 One Address Architecture A The instruction format of this oneaddress architecture is operationltaddressgt Address are given in hexadecimal and are preceded by an X for instance X56 Euripides Montagne University of Central Florida 22 Example OneAddress Program Memory Address X20 450 X21 3 00 X22 750 after program execution X23 Load ltX2Ogt X24 Add ltX2 lgt X25 StoreltX22gt X26 End Euripides Montagne University of Central Florida 23 Programs With Errors So far we have a computer that can execute programs free from errors What would happen if an over ow occurred While executing an addition operation We need a mechanism to detect this type of event and take appropriate actions Euripides Montagne University of Central Florida 24 Over ow Detection A ip op will be added to the ALU for detecting over ow The FetchExecute cycle has to be extended to FetchExecuteInterrupt cycle An abnormal end ABEND has to be indicated Euripides Montagne University of Central Florida 25 VN With Over ow FlipFlop I lt MAR OldIP MEMORY l OPI ADDRESS l4 l MDR Euripides Montagne University of Central Florida 26 Interrupt Cycle 0 In the interrupt cycle the CPU has to check for an interrupt each time an instruction is executed Modi cations have to be made to the instruction set to incorporate the interrupt cycle An operation code of 05 will be added to accommodate the Interrupt Cycle At the end of each execution cycle the DECODER will be set to 05 instead of 00 to check for interrupts at the end of each execution cycle Euripides Montagne University of Central Florida 27 Interrupt Cycle 05 E 1 If OV1 1 Abnormal End Then HALT ABEND for DECODER 00 OVCI HOW 2 Set Decoder to Fetch Cycle Euripides Montagne University of Central Florida 28 U ISA Interrupt cycle 01 Load 03 m MARGIRAddress MAReIR39AddreSS MDR MEMMAR MDR 39A A MDR MEMMAR MDR DECODEReos DECODER 05 02 Add 04 8amp1 MARGIRAddress MDR MEMMAR 05 Abend A A MDR IF OV 1 Then HALT DECODER 3905 DECODER 00 Euripides Montagne University of Central Florida 29 I Interrupt Handling Routine Instead of halting the machine the ow of execution can be transferred to an interrupt handling routine 0 This is done by loading the IP register With the start address of the interrupt handler in memory from NEWIP Causes a change in the Interrupt Cycle Euripides Montagne University of Central Florida 30 Interrupt Handler Takes Control of VN 39 IP NewIP 0000 MAR OldIP lt 0000 MEMORY INTERRUPT HANDLER USER PROGRAM I OPI ADDRESS 4 MDR I gt Euripides Montagne University of Central Florida 31 05 Interrupt Cycle i If OV1 O Jump to interrupt Then 1P NEWIP handler at memory location 1000 DECODER 00 39 Set decoder to fetch cycle Euripides Montagne University of Central Florida 32 l Hardware Software Bridge lll 01 w 03 St MARGIRAddress MAReIR39AddreSS MDR MEMMAR MDR 39A A MDR MEMMAR MDR DECODER05 DECODER 3905 02 Add 04 8amp1 MARGIRAddress MDR MEMMAR 05 Interrth Handler Routine A AMDR IFOV11PNEWIP DECODER 605 DECODER e 00 Euripides Montagne University of Central Florida 33 Virtual Machine The interrupt handler is the rst extension layer or Virtual machine developed over VN First step towards an operating system Interrupt Handler VN Interrupt Handler Virtual Machine Euripides Montagne University of Central Florida 34 Shared Memory The interrupt handler has to be loaded into memory along with any user program Sharing memory space raises a new problem the user program might eventually execute an instruction which may modify the interrupt handler routine Euripides Montagne University of Central Florida 35 Shared Memory Example Interrupt Handler is loaded at MEM0 with a length of 4000 words Interrupt Handler lt 3500 User program executes 4000 STORElt3500gt thus modifying the handler routine User Program Euripides Montagne University of Central Florida 36 H Memory Protection l il A new mechanism must be implemented in order to protect the interrupt handler routine from user programs 0 The memory protection mechanism has three components a fence register a device to compare addresses and a ip op to be set if a memory Violation occurs Euripides Montagne University of Central Florida 37 Memory Protection Components l il 9 Fence Register register loaded with the address of the boundary between the interrupt handler routine and the user program 0 Device for Address Comparisons compares the fence register with any addresses that the user program attempts to access FlipF lop is set to 1 if a memory Violation occurs Euripides Montagne University of Central Florida 38 VN With Memory Protection MEMORY l OPI ADDRESS l4 l MDR Euripides Montagne University of Central Florida 39 I Changes to the ISA With the inclusion of the mechanism to protect the Interrupt Handler some modi cations need to be made to the ISA Instruction Set Architecture Instructions Load Add and Store have to be modi ed to check the value of the Memory Protection MP once the rst step of those instructions has executed Euripides Montagne University of Central Florida 40 Modi ed ISA 01 Load 03 Store ihAddreSS MARIRAddress Z en MDR MEMMAR If MP O Then A MDR MDR 39A DECODER 05 MEMMAR 39MDR Decoder 05 02 Add 05 Interrupt Handler Routine MARIRAddress 1F 0V 2 1 IP NEWIP If MP0 Then IF MP 1 IP NEWIP A A MDR DECODER 05 Euripides Montagne University of Central Florida 41 Program State Word P SW The PSW or Program State Word is a structure that give us information about the state of a program In this register we have the 1P MODE Interrupt Flags and the Maskde ned later Euripides Montagne University of Central Florida 42 Program State Word Interrupt Flags MASK MP 0V To be de ned later Euripides Montagne University of Central Florida H Privileged Instructions l What if a user program attempted to modify the fence register The register is not protected so it does not fall under the previous memory protection mechanism Use the idea of privileged instructions to denote which instructions are prohibited to user programs Euripides Montagne University of Central Florida 44 Privileged Instruction Implementation II l To distinguish between times when privileged instructions either are or are not allowed the computer operates in two modes 9 User mode 0 39 Supervisor mode 1 39 From now on interrupt handler and supervisor are terms that can be used interchangeably 9 In User mode only a subset of the instruction set can be used 0 The supervisor has access to all instructions Euripides Montagne University of Central Florida 45 Implementing Privileged Instructions cont 0 1 Add another ip op ag to the CPU and denote it as the mode bit 39 2 Create a mechanism in the CPU to avoid the execution of privileged instructions by user programs 3 The instruction set has to be organized in such a way that all privileged instructions have operation codes greater than a given number For example if the ISA has 120 instructions privileged instructions will have operation codes Emiparsatgrethan 59 University ofcenwo da 46 ll39 ll quot V Mechanism for User Supervisor Modes l This device compares the opcode in the Instruction Register IROP with the opcode of the last nonprivileged instruction If the outcome yields a then this is a privileged instruction This outcome is then compared with the mode bit If the mode is 0 indicating user mode and it is a privileged instruction then the Privileged Instruction bit PI is set to one The hardware will detect the event and the interrupt handler routine will be executed Euripides Montagne University of Central Florida 47 Mechanism for User Supervisor Modes Cont Euripides Montagne University of Central Florida 48 CPU After Mode Flag Addition CPU I OVHMPHPI lMode I NeWIP 39 Euripides Montagne University of Central Florida Supervisor Mode PSW User Mode 49 Addition PSW After Mode and PI ag g E Interrupt Flags MASK IP Mode OV MP Pl To be de ned later Euripides Montagne University of Central Florida 50 Types of Interrupts E Traps Software InterruptS System Calls Interrupts Hardware Interrupts gt IO Interrupt External gt Timer Euripides Montagne University of Central Florida 51 Traps 9 An interrupt is an exceptional event that is automatically handled by the interrupt handler 39 In the case of an over ow memory addressing violation and the use of privileged instruction in user mode the handler will abort the program 9 These types of interrupts are called traps 9 All traps are going to be considered synchronous interrupts Euripides Montagne University of Central Florida 52 IO Interrupts l I 9 This type of interrupt occurs when a device sends a signal to inform the CPU that an IO operation has been completed 0 An IO ag is used to handle this type of interrupt 0 When an IO interrupt occurs the Program State of the running program is saved so that it can be restarted from the same point after the interrupt has been handled Euripides Montagne University of Central Florida 53 Saving the state of the running program I lt MAR OldIP MEMORY l OPI ADDRESS l4 l MDR Euripides Montagne University of Central Florida Program State Word 1 i Interrupt Flags MASK 1P Mode 1 0V MP P1 0 To be de ned later IO Device Euripides Montagne University of Central b orida 5 05 Interrupt Cycle l lll IF OV 1 THEN IP 6 NEWIP MODE 6 l ABEND IF MP 1 THEN IP 6 NEWIP MODE 6 l ABEND IF PI 1 THEN IP 6 NEWIP MODE 6 l ABEND IF 10 1 THEN OLDIP IP IP NEWIP MODE 6 l DECODER 6 00 Euripides Montagne University of Central Florida 56 1 Supervisor II The Supervisor can use both user and privileged instructions Sometimes a user program requires some services from the Supervisor such as opening and reading les A program cannot execute open or read functions itself and so needs a mechanism to communicate With the Supervisor Euripides Montagne University of Central Florida 57 I SuperVisorCall SVC An SVC is also known as a System Call It is a mechanism to request service from the Supervisor or OS This mechanism is a type of interrupt called a software interrupt because the program itself relinquishes control to the Supervisor as part of its instructions Euripides Montagne University of Central Florida 58 System Calls l There are two types of system calls 1 Allows user programs to ask for service instructions found below opcode 59 2 Privileged Instructions over opcode 5 9 Euripides Montagne University of Central Florida 59 SCVT The System Call Vector TableSCVT contains a different memory address location for the beginning of each service call 9 Service calls are actually programs because they require multiple instructions to execute 0 Each memory address contained in the SCVT points to runtime library generally written in assembly language which contains instructions to execute the call Euripides Montagne University of Central Florida 60 I Runtime Libraries Runtime Libraries precompiled procedures that can be called at runtime Runtime Libraries set a new ip op called the SVC ag to l Which causes the system to switch to Supervisor Mode in the Interrupt Cycle Euripides Montagne University of Central Florida 61 Properties of Runtime Libraries Libraries are shared by all programs Are not allowed to be modi ed by any program Euripides Montagne University of Central Florida 62 SVC Instruction Format l A SVCindeX is the format for system calls a The index is the entry point in the SCVT Read9 SVCindex IROPSVC IRADDRindex Euripides Montagne University of Central Florida 63 l 80 SVCindeX OLDIPIP B IRADDRESS 1P RTLADDRESS DECODER 05 Euripides Montagne 80 SVCindeX Save IP of current program The Index value is temporarily loaded into register B Address of Runtime Library a Transfer to Interrupt Cycle University of Central Florida 64 SVCread 804 MEMORY k Fence f 2 4000 J l OPI ADDRESS l4 l MDR Euripides Montagne University of Central Florida 65 Runtime Library and SVCT Example Ru ggedljlbmry for IH searching code 39 for Read quotnunquotn IF SVCFLAG1 quotquotquotquotquotquotquot quot User Program IP 6 SCVTB LOADIP OLDIP LOADIP OLD1P Address Address Address Address Address Open Close Write Read End SCVT l 2 3 4 5 Euripides Moniagne University of Central Florida 66 The IP is overwritten User Program Ru ggedglbmry for IH searching code for Read IF SVCFLAG1 SVC4 quotquotquotquotquot quot IP 6 SCVT B LOADIP OLD1P When SVC4 is executed OLDIP 6 IP and after executing SVCFLAG 1 OLDIP 6 IP in t e interrupt cycle Euripides ontagne University of Central Florida 67 80 SVCindeX OLDIPIP B IRADDRESS 1P RTLADDRESS DECODER 05 Euripides Montagne 80 SVCindeX Ill Save IP of current program The Index value is temporarily loaded into register B Address of Runtime Library a Transfer to Interrupt Cycle University of Central Florida 68 05 Interrupt Cycle If OV1 Then IP NEWIP MODE l ABEND If MP1 Then IP NEWIP MODE l ABEND If PI1 Then IP NEWIP MODE l ABEND IF 10 1 THEN OLDIP 1P 1P NEWIP MODE 6 l If SVC1 THEN OLDIP IP IP NEWIP MODE 1 DECODER 00 Euripides Montagne University of Central Florida 69 How can we handle nested interrupts Introducing the concept of a Stack 1 The OLDIP register is used as an stack pointer 2 OLDIP register will be rename Stack Pointer SP Euripides Montagne University of Central Florida 7O The Stack Will store all return addresses sAddress lt Fence E A Fence 4000 l I OPI ADDRESS 4 MDR Euripides Montagne University of Central Florida 71 I 05 Interrupt Cycle Including the stack mechanism 7 If OV1 Then IP NEWIP MODE l ABEND If MP1 Then IP NEWIP MODE l ABEND If PI1 Then IP NEWIP MODE l ABEND IF 10 1 THEN MEMSP IP SP 6 SP 1 IP eNEWIP MODEei If svc1 THEN MEMSP IP SP 6 SP 1 IP NEWIP MODE 1 DECODER 00 Euripides Montagne University of Central Florida 72 Program State Word including the SVC ag I A Interrupt Flags MASK IP Mode MP PI I SVC 0V 0 To be de ned later Euripides Montagne University of Central Florida 73 Timer Interrupt l 0 What if a program has an in nite loop 9 We can add a time register set to a speci c value before a program stops which is decremented with each clock tick When the timer reaches zero the Timer Interrupt bit TI is set to 1 indicating that a timer interrupt has occurred and transferring control to the interrupt handler Prevents a program from monopolizing the CPU Euripides Montagne University of Central Florida 74 I Timer Interrupt cont NeWIP I Timer Euripides Montagne University of Central Florida 5 739Q IovHMPHPI Hsvci Supervisor HFence Mode MOde User Mode 75 Program State Word g E Interrupt Flags MASK IP Mode OV MP Pl Tl lO SVC To be de ned later Euripides Montagne University of Central Florida 76 Interrupt Vector Switching between user and supervisor modes must be done as quickly as possible 39 In the case of the VN machine control is transferred to the interrupt handler which then analyzes the ags and determines which is the appropriate course of action to take A faster form of switching directly to the procedure or routine that handles the interrupt can be implemented using an interrupt vector Euripides Montagne University of Central Florida 77 Interrupt Vector cont The idea of an interrupt vector consists of partitioning the interrupt handler into several programs one for each type of interrupt The starting addresses of each program are kept in an array called the interrupt vector which is stored in main memory Euripides Montagne University of Central Florida 78 lI Il H Interrupt Vector Structure l For each type of interrupt there is a corresponding entry in the array called IHV Instead of transferring control just to the Interrupt Handler we specify the element in the array that corresponds to the interrupt that occurred This way the routine that handles that interrupt is automatically executed Euripides Montagne University of Central Florida 79 05 Interrupt Cycle With the Interrupt Vector ii If OV1 Then 1P IHVO Mode 1 0V IfMP1 Then 1P IHV1 Mode 1 0 If PI1 Then IP IHV2 Mode 1 1 IP 2 PI If TI1 Then MEMSP IP SP 6 SP 13 TI IP IHV3 MODE 1 4 10 5 SVC Euripides Montagne University of Central Florida 80 05 Interrupt Cycle With the Interrupt Vector Cont l If IO1 Then MEMSP IP SP 6 SP 1 OV IP IHV4 0 MODE 1 1 IP If SVC1 Then MEMSP IP SP 6 SP 1 2 T IP IHV5 MODE 1 3 TI DECODER 00 4 10 5 SVC Euripides Montagne University of Central Florida 81 I Multiprogramming and Timers Multzprogmmming allowing two or more user programs to reside in memory If we want to run both programs each program P1 and P2 can be given alternating time on the CPU letting neither one dominate CPU usage Euripides Montagne University of Central Florida 82 H Process Concept In order to implement multiprogramming we need to utilize the concept of a process Process de ned as a program in execution We ll explore this concept further in the next lecture Euripides Montagne University of Central Florida 83
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