COMPUTER ARCHITECTURE CDA 4150
University of Central Florida
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This 86 page Class Notes was uploaded by Genoveva Bogisich on Thursday October 22, 2015. The Class Notes belongs to CDA 4150 at University of Central Florida taught by Staff in Fall. Since its upload, it has received 42 views. For similar materials see /class/227527/cda-4150-university-of-central-florida in Computer Design Architecture at University of Central Florida.
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Date Created: 10/22/15
Interrupt Handling by Euripides Montagne University of Central Florida Outline 1 The structure of a tiny computer The interrupt mechanism 9599J Interrupt Types Euripides Montagne University of Central Florida A program as an isolated system The hardware software interface H VonNeumann Machine VN E MAR MEMORY 1R l OPI ADDRESS l4 l MDR A l W Euripides Montagne University of Central Florida 3 Instruction Cycle 39 Instruction cycle or machine cycle in VN is composed of 2 steps 39 1 Fetch Cycle instructions are retrieved from memory 2 Execution Cycle instructions are executed A hardware description language will be used to understand how instructions are executed in VN Euripides Montagne University of Central Florida 4 De nitions IP Instruction Pointer is a register that holds the address of the next instruction to be executed MAR Memory Address Register is used to locate a speci c memory location to read or write its content MEM Main storage or RAM Random Access Memory and is used to store programs and data Euripides Montagne University of Central Florida De nition of MDR MDR Memory Data Register is a bidirectional register used to receive the content of the memory location addressed by MAR or to store a value in a memory location addressed by MAR This register receives either instructions or data from memory Euripides Montagne University of Central Florida 6 De nitions Cont IR Instruction Register is used to store instructions DECODER Depending on the value of the IR this device will send signals through the appropriate lines to execute an instruction 39 A Accumulator is used to store data to be used as input to the ALU ALU Arithmetic Logic Unit is used to execute mathematical instructions such as ADD or MULTIPLY Euripides Montagne University of Central Florida 7 Fetch Execute Cycle In VN the instruction cycle is given by the following loop Fetch Execute In order to explain further details about the fetch execute cycle the data movements along different paths can be described in 4 steps Euripides Montagne University of Central Florida 8 Data Movement 1 Given register IP and MAR the transfer of the contents of IP into MEMORY MAR is indicated as MARIP I OPI ADDRESS 4 MDR Euripides Montagne University of Central Florida 9 Data Movement 2 To transfer information from a memory location to the register MDR we use MEMORY lDR MEM MAR A The address of the memory I CPI ADDRESS H MDR location has been stored previously into the MAR register Euripides Montagne University of Central Florida 10 H l Data Movement 3 To transfer information from the MDR register to a memory location we use MEM MAR MDR gt see previous slide for diagram The address of the memory location has been previously stored into the MAR Euripides Montagne University of Central Florida 11 Instruction Register Properties The Instruction Register IR has two elds Operation OP and the ADDRESS These elds can be accessed using the selector operator Euripides Montagne University of Central Florida 12 Data Movement 4 The operation eld of the IR register is sent to the DECODER as DECODERGIRDP 39 The Operation portion of the eld is accessed as IROP DECODER If the value of IROPO then the decoder can be set to execute the fetch cycle again Euripides Montagne University of Central Florida l3 Data Movement 4 Cent DECODERGIRDP V MEMORY l OPI ADDRESS l4 l MDR Euripides Montagne University of Central Florida 14 Instruction Cycle The instruction cycle has 2 components Fetch cycle retrieves the instruction from memory Execution cycle carries out the instruction loaded previously Euripides Montagne University of Central Florida 15 OO Fetch Cycle E 1MAR 61F 1C0py contents of IP into 2MDR MEMMAR Load content of memory 3 JR eMDR location into MDR 4IP IPlrl 3 Copy value stored in MDR into IR 5DECODER IROP Euripides Montagne Increment IP register 5 Select Instruction to be executed University of Central Florida 16 Execution 01 LOAD MAR IRADDR 1 Copy the IR address MDR MEMMAR value eld into MAR 2 Load the content of a M II A MDR memory locat1on1nto DECODER 00 MDR 3 Copy content of MDR into A register 4 Set Decoder to execute Fetch Cycle Euripides Montagne University of Central Florida 17 a H Execution 02 ADD 1 MAR 61RADDR 1 Copy the IR address 2 MDR eMEMMAR value eld 1nto MAR Load content of memory 3 A 6A MDR location to MDR 4 DECODER 600 3 Add contents of MDR and A register and store result into A 4 Set Decoder to execute Fetch cycle Euripides Montagne University of Central Florida 18 Execution O3 STORE MAR IRADDR 1 Copy the IR address M II MDR A value eld into MAR 2 Copy A register MEMlMAR MDR contents into MDR MDR into a memory location 4 Set Decoder to execute fetch cycle Euripides Montagne University of Central Florida 19 1 STOP Euripides Montagne Execution O4 END 1 Program ends normally University of Central Florida 20 Instruction Set Architecture 00 Fetch hidden instruction 01 M MAR 11 MAR IRAddress MDR MEMMAR MDR MEMlMAR IR MDR A MDR IP IP1 DECODER00 DECODER IROP 03 St0139e 02 Add MAR IRAddress MAR IRAddress MDR A MDR MEMMAR MEMMAR MDR A A MDR DECODER 00 DECODER 00 4 Sta 1 Euripides Montagne University of Central Florida 21 One Address Architecture The instruction format of this oneaddress architecture is operationltaddressgt Address are given in hexadecimal and are preceded by an X for instance X56 Euripides Montagne University of Central Florida 22 Example OneAddress Program Memory Address X20 450 X21 3 00 X22 750 after program execution X23 Load ltX2Ogt X24 Add ltX2 lgt X25 StoreltX22gt X26 End Euripides Montagne University of Central Florida 23 Programs With Errors So far we have a computer that can execute programs free from errors What would happen if an over ow occurred While executing an addition operation We need a mechanism to detect this type of event and take appropriate actions Euripides Montagne University of Central Florida 24 Over ow Detection A ip op Will be added to the ALU for detecting over ow The FetchExecute cycle has to be extended to FetchExecuteInterrupt cycle An abnormal end ABEND has to be indicated Euripides Montagne University of Central Florida 25 VN With Over ow FlipFlop I lt MAR OldIP MEMORY l OPI ADDRESS l4 l MDR A I ALU Euripides Montagne University of Central Florida Interrupt Cycle In the interrupt cycle the CPU has to check for an interrupt each time an instruction is executed 39 Modi cations have to be made to the instruction set to incorporate the interrupt cycle An operation code of 05 will be added to accommodate the Interrupt Cycle At the end of each execution cycle the DECODER will be set to 05 instead of 00 to check for interrupts at the end of each execution cycle Euripides Montagne University of Central Florida 27 Interrupt Cycle 05 1 If OV1 1 Abnormal End Then HALT ABEND for DECODER 00 OVGI HOW 2 Set Decoder to Fetch Cycle Euripides Montagne University of Central Florida 28 ISA Interrupt cycle 01 w MARIRAddress MDR MEMMAR A 6 MDR DECODERGOS 02 Add MARIRAddress MDR MEMMAR A 6 A MDR DECODER 605 Euripides Montagne 03 St MARIRAddress MDR 6A MEMMAR MDR DECODER 605 04 Sir 05 Abend IF OV 1 Then HALT DECODER 00 University of Central Florida 29 H Interrupt Handling Routine Instead of halting the machine the ow of execution can be transferred to an interrupt handling routine This is done by loading the IP register With the start address of the interrupt handler in memory from NEWIP Causes a change in the Interrupt Cycle Euripides Montagne University of Central Florida 30 Interrupt Handler Takes Control of VN 39 IP NewIP 0000 MAR OldIP lt 0000 MEMORY INTERRUPT HANDLER USER PROGRAM OPI ADDRESS l4 l MDR A A I A L U Euripides Montagne University of Central Florida 05 Interrupt Cycle IfOV1 39 Jump to interrupt Then 1P NEWIP handler at memory location 1000 DECODER 00 39 Set decoder to fetch cycle Euripides Montagne University of Central Florida 32 Hardware Software Bridge 01 Load 03 m MARGIRAddress MAReIR39AddreSS MDR MEMMAR MDR 39A A MDR MEMMAR MDR DECODER05 DECODER 3905 02 Add 04 mg MARGIRAddress MDR MEMMAR 05 Interrth Handler Routine A AMDR IFOV11PNEWIP DECODER 605 DECODER e 00 Euripides Montagne University of Central Florida 33 Virtual Machine The interrupt handler is the rst extension layer or Virtual machine developed over VN First step towards an operating system Euripides Montagne Interrupt Handler VN Interrupt Handler Virtual Machine University of Central Florida 34 Shared Memory The interrupt handler has to be loaded into memory along With any user program Sharing memory space raises a new problem the user program might eventually execute an instruction which may modify the interrupt handler routine Euripides Montagne University of Central Florida 35 Shared Memory Example Interrupt Handler is loaded at MEM0 with a length of 4000 words Interrupt Handler 3500 User program executes 4000 STORElt3500gt thus modifying the handler routine User Program Euripides Montagne University of Central Florida 36 Memory Protection ID A new mechanism must be implemented in order to protect the interrupt handler routine from user programs The memory protection mechanism has three components a fence register a device to compare addresses and a ip op to be set if a memory Violation occurs Euripides Montagne University of Central Florida 37 Memory Protection Components 39 Fence Register register loaded with the address of the boundary between the interrupt handler routine and the user program 39 Device for Address Comparisons compares the fence register with any addresses that the user program attempts to access FlipF lop is set to 1 if a memory Violation occurs Euripides Montagne University of Central Florida 38 VN With Memory Protection I lt MAR OldIP MEMORY l OPI ADDRESS l4 l MDR A I ALU Euripides Montagne University of Central Florida 39 l l 4 Changes to the ISA With the inclusion of the mechanism to protect the Interrupt Handler some modi cations need to be made to the ISA Instruction Set Architecture Instructions Load Add and Store have to be modi ed to check the value of the Memory Protection MP once the rst step of those instructions has executed Euripides Montagne University of Central Florida 4O Modi ed ISA 01 Load 03 Store E i fddress MARIRAddress en MDR MEMMAR If MP O Then A lVlDR MDR 6A DECODER 05 MEMMAR MDR Decoder 05 02 Add 05 Interrupt Handler Routine MARIRAddress 1F 0V 2 1 IP NEWIP If MP0 Then IF MP 1 IP NEWIP A A MDR DECODER 05 Euripides Montagne University of Central Florida 41 Program State Word P SW The PSW or Program State Word is a structure that give us information about the state of a program In this register we have the 1P MODE Interrupt Flags and the Maskde ned later Euripides Montagne University of Central Florida 42 Program State Word Interrupt Flags MASK IP OV MP To be de ned later Euripides Montagne University of Central Florida 43 Privileged Instructions ID I What if a user program attempted to modify the fence register The register is not protected so it does not fall under the previous memory protection mechanism Use the idea of privileged instructions to denote which instructions are prohibited to user programs Euripides Montagne University of Central Florida 44 Privileged Instruction Implementation To distinguish between times when privileged instructions either are or are not allowed the computer operates in two modes 39 User mode 0 39 Supervisor mode 1 s From now on interrupt handler and supervisor are terms that can be used interchangeably 39 In User mode only a subset of the instruction set can be used 39 The supervisor has access to all instructions Euripides Montagne University of Central Florida 45 I l 1 Add another ip op ag to the CPU and denote it as the mode bit 39 2 Create a mechanism in the CPU to avoid the execution of privileged instructions by user programs 3 The instruction set has to be organized in such a way that all privileged instructions have operation codes greater than a given number F or example if the ISA has 120 instructions privileged instructions will have operation codes University of Central Florida Implementing Privileged Instructions cont 46 l l 439 Mechanism for User Supervisor Modes This device compares the opcode in the Instruction Register IROP with the opcode of the last nonprivileged instruction If the outcome yields a 1 then this is a privileged instruction This outcome is then compared With the mode bit If the mode is 0 indicating user mode and it is a privileged instruction then the Privileged Instruction bit PI is set to one a The hardware will detect the event and the interrupt handler routine will be executed Euripides Montagne University of Central Florida 47 Mechanism for User Supervisor Modes Cont Euripides Montagne University of Central Florida 48 1 CPU After Mode Flag Addition CPU I OVHMPHPI lMode I NeWIP 39 Euripides Montagne University of Central Florida Supervisor Mode PSW User Mode 49 PSW After Mode and PI ag Addition Interrupt Flags MASK IP Mode MP PI 0V To be de ned later Euripides Montagne University of Central Florida 50 Interrupts Euripides Montagne Types of Interrupts Traps SO Ware Interrupts E System Calls Hardware Interrupts gt IO Interrupt External gt Timer University of Central Florida 51 Traps An interrupt is an exceptional event that is automatically handled by the interrupt handler 39 In the case of an over ow memory addressing violation and the use of privileged instruction in user mode the handler will abort the program 39 These types of interrupts are called traps All traps are going to be considered synchronous interrupts Euripides Montagne University of Central Florida 52 IO Interrupts This type of interrupt occurs when a device sends a signal to inform the CPU that an IO operation has been completed 39 An IO ag is used to handle this type of interrupt When an IO interrupt occurs the Program State of the running program is saved so that it can be restarted from the same point after the interrupt has been handled Euripides Montagne University of Central Florida 53 Saving the state of the running program I lt MAR OldIP MEMORY l OPI ADDRESS l4 l MDR l l A l A I ALU Euripides Montagne University of Central Florida 54 Program State Word E1 Interrupt Flags MASK IP Mode 1 0V MP P1 0 To be de ned later IO Device Euripides Montagne University of Central b orida 5 05 Interrupt Cycle IF OV 1 THEN IP 6 NEWIP MODE 6 l ABEND IF MP 1 THEN IP 6 NEWIP MODE 6 l ABEND IF PI 1 THEN IP 6 NEWIP MODE 6 l ABEND IF 10 1 THEN OLDIP IP IP NEWIP MODE 61 DECODER 6 00 Euripides Montagne University of Central Florida 56 Supervisor The Supervisor can use both user and privileged instructions Sometimes a user program requires some services from the Supervisor such as opening and reading les A program cannot execute open or read functions itself and so needs a mechanism to communicate With the Supervisor Euripides Montagne University of Central Florida 57 H SuperVisorCall SVC An SVC is also known as a System Call It is a mechanism to request service from the Supervisor or OS This mechanism is a type of interrupt called a software interrupt because the program itself relinquishes control to the Supervisor as part of its instructions Euripides Montagne University of Central Florida 58 System Calls There are two types of system calls 1 Allows user programs to ask for service instructions found below opcode 59 2 Privileged Instructions over opcode 5 9 Euripides Montagne University of Central Florida 59 SCVT The System Call Vector TableSCVT contains a different memory address location for the beginning of each service call 39 Service calls are actually programs because they require multiple instructions to execute Each memory address contained in the SCVT points to runtime library generally written in assembly language which contains instructions to execute the call Euripides Montagne University of Central Florida 60 Runtime Libraries Runtime Libraries precornpiled procedures that can be called at runtirne Runtime Libraries set a new ip op called the SVC ag to l which causes the system to switch to Supervisor Mode in the Interrupt Cycle Euripides Montagne University of Central Florida 61 Properties of Runtime Libraries Libraries are shared by all programs Are not allowed to be modi ed by any program Euripides Montagne University of Central Florida 62 SVC Instruction Format SVCindeX is the format for system calls a The index is the entry point in the SCVT Read SVCindex1R0Psvc IRADDRindex Euripides Montagne University of Central Florida 63 80 SVCindeX OLDIPIP B IRADDRESS 1P RTLADDRESS DECODER 05 Euripides Montagne 80 SVCindeX Save IP of current program a The Index value is temporarily loaded into register B Address of Runtime Library 0 Transfer to Interrupt Cycle University of Central Florida 64 SVCread 804 MEMORY L Fence f 2 4000 J I OPI ADDRESS 4 MDR A I ALU Jr Euripides Montagne University of Central Florida 65 Runtime Library and SVCT Example User Program Ru ggedglbmry for IH searching code for Read SVC4 1P 6 SCVTlB LOADIP OLD1P LOADIP OLDIP Address Address Address Address Address Open Close Write Read End SCVT l 2 3 4 5 Euripides Moniagne University of Central Florida 66 The IP is overwritten R L39 f User Program 221 lbrary or IH searchlng code for Read SVC4 1P 6 SCVTlB LOADIP OLDIP When SVC4 is executed OLDIP 6 IP and after executing SVCFLAG 1 OLDIP 6 IP Eurgdgi Interrupt cycle ontagne University of Central Florida 67 80 SVCindeX OLDIPIP B IRADDRESS 1P RTLADDRESS DECODER 05 Euripides Montagne 80 SVCindeX Save IP of current program a The Index value is temporarily loaded into register B Address of Runtime Library 0 Transfer to Interrupt Cycle University of Central Florida 68 05 Interrupt Cycle L l If OV1 Then IP NEWIP MODE l ABEND If MP1 Then IP NEWIP MODE l ABEND If Pll Then IP NEWIP MODE l ABEND IF 10 1 THEN OLDIP 1P 1P NEWIP MODE 6 l If SVC1 THEN OLDIP IP IP NEWIP MODE 1 DECODER 00 Euripides Montagne University of Central Florida 69 How can we handle nested interrupts Introducing the concept of a Stack 1 The OLDIP register is used as an stack pointer 2 OLDIP register Will be rename Stack Pointer SP Euripides Montagne University of Central Florida 70 The Stack Will store all return addresses Address lt Fence E A Fence 4000 l OPI ADDRESS l4 l MDR lt gtA A I ALU Euripides Montagne University of Central Florida 71 05 Interrupt Cycle f Including the stack mechanism If OV1 Then IP NEWIP MODE l ABEND If MP1 Then IP NEWIP MODE l ABEND If PI1 Then IP NEWIP MODE l ABEND IF 10 1 THEN MEMSP IP SP 6 SP 1 1P eNEWIP MODEei If svc1 THEN MEMSP IP SP 6 SP 1 IP NEWIP MODE 1 DECODER 00 Euripides Montagne University of Central Florida 72 Program State Word including the SVC ag Interrupt Flags MASK IP Mode MP PI 10 C 0V SV To be de ned later Euripides Montagne University of Central Florida 73 Timer Interrupt What if a program has an in nite loop 39 We can add a time register set to a speci c value before a program stops which is decremented with each clock tick When the timer reaches zero the Timer Interrupt bit TI is set to 1 indicating that a timer interrupt has occurred and transferring control to the interrupt handler Prevents a program from monopolizing the CPU Euripides Montagne University of Central Florida 74 Timer Interrupt cont OVHMPHPI Hsvci NeWIP lTimer Mode H Fence I01 I PU Euripides Montagne University of Central Florida at Supervisor Mode User Mode 75 Program State Word 1 Interrupt Flags MASK IP Mode 0 MP PI Tl lO SVC V To be de ned later Euripides Montagne University of Central Florida 76 Interrupt Vector i l Switching between user and supervisor modes must be done as quickly as possible 39 In the case of the VN machine control is transferred to the interrupt handler which then analyzes the ags and determines which is the appropriate course of action to take A faster form of switching directly to the procedure or routine that handles the interrupt can be implemented using an interrupt vector Euripides Montagne University of Central Florida 77 H Interrupt Vector cont The idea of an interrupt vector consists of partitioning the interrupt handler into several programs one for each type of interrupt The starting addresses of each program are kept in an array called the interrupt vector which is stored in main memory Euripides Montagne University of Central Florida 78 l l Interrupt Vector Structure For each type of interrupt there is a corresponding entry in the array called IHV Instead of transferring control just to the Interrupt Handler we specify the element in the array that corresponds to the interrupt that occurred This way the routine that handles that interrupt is automatically executed Euripides Montagne University of Central Florida 79 05 Interrupt Cycle With the Interrupt Vector If OV1 Then 1P IHVO Mode 1 0V IfMP1 Then 1P IHV1 Mode 1 0 IfPI1 Then 1P IHV2 Mode 1 1 IP 2 PI If TI1 Then MEMSP IP SP 6 SP 13 TI IP IHV3 MODE 1 4 10 5 SVC Euripides Montagne University of Central Florida 80 05 Interrupt Cycle With the f f Interrupt Vector Cont If IO1 Then MEMSP IP SP 6 SP 1 0V IP IHV4 0 MODE 1 1 IP If SVC1 Then MEMSP IP SP 6 SP 1 2 PI IP IHV5 MODE 1 3 TI DECODER 600 4 10 5 SVC Euripides Montagne University of Central Florida 81 l H Multiprogramming and Timers Multiprogmmming allowing two or more user programs to reside in memory If we want to run both programs each program P1 and P2 can be given alternating time on the CPU letting neither one dominate CPU usage Euripides Montagne University of Central Florida 82 H Process Concept In order to implement multiprogramming we need to utilize the concept of a process Process de ned as a program in execution We ll explore this concept further in the next lecture Euripides Montagne University of Central Florida 83 UCF School of Computer Science CDA 4150 Computer Architecture Spring 2005 Syllabus Professor Euripides Montague Tele 8232684 emaileuripcsucfedu Lecture meetings MWF 1130 noon 7 1220 pm ENG2 105 Of ce hours Of ce hours MW from 900 am to 1100 am CSB 239 TR from 43000 pm to 630 pm CSB 239 TA Jingei Kong Tele 407 8233228 email jfkongcsucfedu Of ce hours WF from 200 pm to 400 pm CSB 107 Course Outline This course is intended to provide students an understanding in the fundamental concepts and design principles of computer architecture The students will gain a suf cient understanding of the relationships between higherlevel programming languages and machine language Course Topics Organization and architecture of computer systems hardware register transfer notation Instruction set architecture ISA addressing modes computer arithmetic processor design for sequential execution pipelining and superscalais memory systems Virtual memory U0 system interrupt handling introduction to multiprocessors Prerequisites 0 CDA 3103 7 Computer Organization Required textbook The textbook for this course is J Hennesy and D Patterson Computer Architecture A Quantitative Approach Morgan Kaufman 3rd edition 2002 Style of Class Meetings Class meetings will not consist of traditional lectures with the instructor doing most of the talking and the student doing most of the listening Rather meetings will consist of discussions on each topic and the instructor will help guide the discussion by asking questions Grading Policy 20 Exam 1 7 closed book closed notes exam given in class 20 Exam 2 7 closed book closed notes exam given in class 25 Final Exam 7 closed book closed notes comprehensive exam given during nal exam week Note You must score at least 60 on this exam to pass the course 25 Programming project Teams of two 7 a large multipart simulation of a Computer Architecture The grade for this project will be divided between your C code one or more demonstrations of your project your documentation and homeworks given on selected topics from the project 10 Home works Letter grades 90 100 A 80 89 B 70 79 C Note Any academic dishonesty including but not limited to Cheating copying andor plagiarism with respect to any exam or assignment in this class will result in a grade of F following by the usual procedures for dealing with such behavior as describe in the UCF Golden Rule 39 a handbook for students The Semester Plan Tentative Week 1 Logistics team organization Introduction to computer Architecture Flynn s Taxonomy Week 2 7 SISD architecture register transfer notation 7 Cost of a Die Performance Amdahl s Law Jan 21 Martin Luther King Jr Day Week 3 7 ISA instruction encodings addressing modes Interrupt handling Case Studies IBM 360 B5000 MIPS Computer Arithmetic Floating point arithmetic Pipelining in the ALU Week 4 Vector processing Memory InterleavingCray1 Chajning loop unrolling skewed matrix representation Week 5 7 Review 7 First Midterm Exam Week 6 7 The Processor Data Path and Control Unit Pipeleined Execution Pipeline data path Week 7 Pipeline Data Hazards Control Hazards Exception Handling Week 8 ILPSuperscalars ScoreboardingCDC6600 Tomasulo s Algorithm MIPS and IA 64 Architectures Week 9 7 Systolic Arrays and Data Flow Architectures Spring Break314 to 319 Week 10 Review Second Midterm Exam Week 11 Cache Memory Virtual Memory Week 12 U0 Devices and Performance Measures R Week 13 7 Detecting Parallelism in Programs Multiprocessors Week 12 7 Interconnection Networks ReView Final Exam April 27 2005 from 1000 to 1250 Website httpwwwcoursescda4150sgring05 Important Dates Classes Begin Janan 10th Withdrawal Deadline is March 4th Classes End April 25th Spring Holidays are Maltin Luther King Jr Day Janan 17th Spring Break March 14 19
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