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Computer Organization

by: Isaac Hauck

Computer Organization EEL 3801

Isaac Hauck
University of Central Florida
GPA 3.7

Ronald Demara

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Ronald Demara
Class Notes
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This 18 page Class Notes was uploaded by Isaac Hauck on Thursday October 22, 2015. The Class Notes belongs to EEL 3801 at University of Central Florida taught by Ronald Demara in Fall. Since its upload, it has received 96 views. For similar materials see /class/227656/eel-3801-university-of-central-florida in Electrical Engineering at University of Central Florida.

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Date Created: 10/22/15
EEL3801 Computer Organization Midterm Exam SOLUTION June 21 2011 NAME SIGNATURE PID Closed books closed notes no crib sheets Only non programmable 4 function calculators are allowed Show all your work and circle your mal answer All papers will be collected at 150PM 1 Computer Organization Fundamentals 25 pts a 10 pts A program can be executed either on a RISC or CISC architecture The average number of clock cycles to execute one machine instruction for the CISC machine is 3 and 1 for the RISC machine However one fth as many CISC instructions are required to execute a program than on the RISC machine Ifthe clock period of the RISC machine is 025 nsec then what is the minimum frequency required for the CISC machine to outperform the RISC machine ANS TSNR TiCISC 3N R7CISC 3N R7CISC TiRISC 1 5 N RiRISC 5N RiRISC Setting TiCISC lt TiRISC yields RiRISCR7CISC 35 06 and since RiRISC1025nsec4GHz then R7CISC gt 064GHZ 24GHz b 10 pts Suppose that the execution time for a program is directly proportional to instruction access time and that access to an instruction in the cache is 50 times faster than access to an instruction in the main memory Assume that a requested instruction is found in the cache with probability 075 and also assume that if an instruction is not found in the cache it must first be fetched from the main memory to the cache and then fetched from the cache to be executed Compute the speedup factor resulting from the presence of the cache All instructions are encoded in a two words Express your answer as a dimensionless ratio ANS Let cache access time be 1 and main memory access time be 50 Every instruction that is executed must incur 2 fetches from the cache and an additional two fetches from the main memory must be performed for 25 of these cache accesses Therefore Speedup factor 1050101 0255037 c 5 pts What is the difference between the functions that the MAR and the MDR perform inside the CPU Or if they re two names for the same component then write SAME Ans MAR Memory Address Register it contains the memory address that the CPU provides to the memory device for loadstore operations MDR Memory Data Register it holds that value that the CPU has read as pointed to by the MAR during a load operation or the value to be written to memory during a store operation Page 1 of 4 II Data Representation 25 pts a 12 pts Given a processor with an 8bit word width complete the following table to express each decimal value in the corresponding binary format or else state NOT POSSIBLE if the value cannot be represented accordingly Decimal Value SignandMagnitude One s Compliment Two s Compliment 117 01110101 01110101 01110101 13 10001101 11110010 11110011 5 10000101 11111010 11111011 128 NOT POSSIBLE NOT POSSIBLE 10000000 b 5 pts Given a processor which has a 4bit word size Consider the decimal ie base ten numbers A 6 andB 3 Perform binary arithmetic using 2 s complement representation to compute C A B using the techniques developed in lecture Express C in 2 s complement notation Also state if Over ow occurs and explain why or why not Ans A B A B 101011010111 Over ow because Carry into MSB Carry out ofMSB c 8 pts Consider a processor with byteaddressable memory organized in 32bit words according to the littleendian scheme A program reads ASCII characters entered at a keyboard and stores them in successive byte locations starting at location 1000 given the memory map shown below prior to execution List the contents of the two memory words at locations 1000 and 1004 after the word quotCocoaquot has been entered Express your answer in hexadecimal Memory map prior to execution 0996 2E2E0049 1000 04B20CDF 1004 0CDF04B2 1008 313131313390 zzrmuumn a p a o c ANS Byte values in hex for the characters 43 6F 636F 61 respectively from left to right for Cocoa Thus the two words at 1000 and 1004 will be 6 F6 3 6 F4 3 and OCDFO 4 6 1 respectively Page 2 of 4 III Addressing Modes and Assembly Language 25 pts Answer all ofthe questions using only the Generlc Assemblz Language notation from Chapter 2 a 10 pts Registers R3 and R4 contain the decimal values 200 and 600 respectively What is the effective address of the memory operand in each of the following instructions V Load 20R3R5 2 Move 3000R5 3 Store R530R3R4 4 Add 7R4R5 5 Subtract R3R5 ANS 220 part of the instruction 830 599 200 b 10 pts Write a generic assembly language program to divide a two s compliment number by 2 where any fractional remainder is ignored The value to be divided is already in R0 and the integer portion of the nal division result should be stored at the memory address currently contained in R1 For maximum credit use the fewest possible number of assembly language instructions ANS AShi R 1 R0 Move R0 R1 Example 1 Initial value of R0 00001001 2 s complement notation of 9 After ARITHIVIETIC shift RIGHT R0 00000100 2 s complement notation of 4 Example2 Initial value of R0 11110011 2 s complement notation of 13 After ARITHIVIETIC shift RIGHT R0 11111001 2 s complement notation of 7 rounding 6 towards negative in nity d 5 pts Both of the following statements cause the value 300 to be stored in location 1000 but at different times Explain the difference ORIGIN 1000 DATAWORD 300 and Mov 300 1000 ANS The assembler directives ORIGIN and DATAWORD cause the object program memory image constructed by the assembler to indicate that 300 is to be placed at memory word location 1000 at the time the grogram is loaded into memory prior to execution The Move instruction places 300 into memory word location 1000 when Mov instruction is executed as part of a grocess Page 3 of 4 IV Write an Assembly Language Program 25 pts Write a Generic Assembly Language program to convert from Little Endian format to Big Endian format on a CPU with a w32bit word width for all registers and memory which is byteaddressable Speci cally assume R1 is already loaded with a 32bit value in Little Endian format The output of the program which is to be stored in location RESULT upon completion of execution is the value in R1 after it is converted to Big Endian format For maximum credit use the fewest possible number of assembly language instructions hint shift and rotate operations could be useful or byteaddressable data transfer instruction logical OR or some combination of these Also for maximum credit please provide a comment for each instruction and a table listing the role of each register used in your program a 25 pts MOV LOCR0 R0 is a pointer Move R1R0 Temporarily store R1 in memory Add 4R0 MoveByte R0R1 Load last byte into R1 first LshiftL 8 R1 Shift Left R1 by 8 bits MoveByte R0R1 LshiftL 8 R1 MoveByte R0R1 LshiftL 8 R1 MoveByte R0R1 Extra Credit 2 pts Cursor is Latin for what English word Express your answer only as a single English word Ans Runner Page 4 of 4 EEL 3801 Com39puter Organization i Spring 2010 Chapter 1 Basic Structure of Computers Hamacher et al Computer Organization Acknowledgment and appreciation for various slide materials from Dr Philip Wilsey Dr Randy Katz Dr Philip Leong Chapter 1 Introduction 0 Computer an electronic calculating machine which accepts digitized input information processes the information according to a program stored in its memory and produces the resulting output information 0 Many types of processor exist that differ widely in size cost computational power and intended use desktop computers notebook computers workstations enterprise systems mainframes servers supercomputers etc Computing Intensive and Communication Intensive Applications 0 Email 0 ComputerAided Design 0 Internet Browsing 0 AirTraf c Control Games Weather Prediction Databases Weapons Word Processing 0 Designer Drugs Spreadsheets Oil Exploration DesktopWeb Publishing Human Genome Project AccountsStock 0 Financial Markets ControlBanking Nuclear Reactor Control 0 Payroll 0 Exploring Space Education 0 Art Music Pictures Movies 0 MachinesAppliancesElectronic creation and distribution Devices The 5 fundamental Components of a Computer System o In its simplest form a computer can be viewed as consisting of 5 functionally independent main components an input unit a memory unit an arithmetic logic unit ALU an output unit and a control unit Arithmetic Input and logic Memory Output Control lO CPU lO InputOutput CPU Central Processing Unit Interaction between components a Block diagram view black box view Central Processing Unit CPU contro Signa 5 data conditions instruction unit execution unit instruction fetch and functional units interpretation FSM and registers Instruction and Data Representation Von Neumann s stored program concept Information in a computer be it stored in memory fed in through an input device or fed out through an output device is either data or instructions Instructions are commands to the computer Which govern the transfer of information Within the computer and between the computer and its IO devices specify the arithmetic and logic operations to be performed Data are numbers and encoded characters that are used as operands by the instructions Integer oating point ASCII Comp1ex data structures lists stacks heaps Information Instruction Types Data Staging Processor 69 Memory Loadstore data tofrom memory We will coxer all of that inst math Re gister to re gister move Data ManiA ulation Processor DataA ath in this dams Add subtract AM W t Icts Increment decrement 5an thasc most t p y mac45M Shlft rotate thmotipms 1mmed1ate operands Control Processor Control Path I conditionalUlluu11u1Liu11 u u1 culullus ill Program OW Subroutine call and return Information Data Kl analog signals binary numbers 00111001010101011 1110 alphanumerlc characters 11000110101116961 y k 1010 1101 01001011011105960 coltrain this course Re resentatiorL of diita desi ns Physical devices 139 Ifl ion 391 l of o 39 I J ft 039 on SW1tches o I A10 41 J Truth tables Boolean algebra Gates Waveforms Finite state behavior Register transfer behavior Concurrent abstract speci cations Instruction Execution Sequence A set of instructions which perform a task is called a program 9 process input the program and store it in memory in a controlled manner select and execute instructions from memory output the results of the program a process is a program in execution different than static code sitting in memory Control State Diagram for each instruction Reset Fetch instruction Decode Execute nitiaize Machine Instructions partitioned into three classes Branch Load store Regi ster to regi ster Each instruction type Different sequence according to diagram for i ste r to eg ister InputOutput Devices and Channels Input Devices keyboard mouse j oysticks microphone etc Output Devices graphic display printer etc 9 under the control of one or more inputoutput units IO units sumquot I Eh39ueno 7 an ineguh 7 Memory System Memory Units are generally divided into 2 classes namely primary or ma1n memory and secondary memory Primary memory is a fast memory capable of operating at electronic speeds This is typically Where programs and data are stored during a program39s execution by the CPU Typically data is stored in xed sizes called words Each word is assigned a unique address and the words can be accessed in a random order ex Random Access Memory RAM Secondary memory Secondary storage is a slower less expensive storage system Typically used for data that is accessed infrequently ex magnetic disks tapes and optical disks CD ROMs Processor CPU The Central Processing Unit CPU is the workhorse of a computer system Arithmetic Logic Unit ALU performs computations e g add multiply logical operations etc Operands taken from registers Control Unit Orchestrates the transfer of data and sequencing of operations between memory registers ALU IO Devices Registers Small but fast storage of intermediate values in a computation Putting the 5 components together the new Androidaph m Google NEXUS one Size and weight Power and battery Removable 1400 mAH battery Internet use Height 119mm mm 59 3mm 5 l3er 11 5mm Weigm 130 grams wrbauerv long W10 Dallely Dis la 3 74nch rdlyagclrlall wldescreen VVVGA AMDLED touchscreen sou x 430 wens mu can 1 lyplcal cunllasl lcuc lms lyplcal response at Talk time Standby Lime Charges al 48 mA frum USE at QBDmA mm upplled charger Up m 10 hours an 26 Uplu 7 hours an 35 Up In 25m hours on 25 Up in 250 hours on 33 Up in 5 haul in 36 Up to 6 5 hours an erFl Video playback Up to 7 hours Audio playback Up in 2a huxlrs Processor uualccmm est 5250 I OH Camera amp Flash 5 megapixels Aurolocus from 6cm ll ln nlty dlgltal zoom LED Hash Use can mclucle lucallan of photos from phene s AGPS recenev Vldao captured at 20mm plxels at 20 frames per second or lugher depending on llgimng urldltlol ls Cellular amp Wireless UMTS Band luS 2100AVVSSllol 1900 MHZI GSMWEDGEiBEO 900 1800 AZDF39 Sterem Eluetuoth Operating system Androm Mobile Technology F39lalfarm 2 l Edam Capacity 512MB Flash 512MB RAM JGE Mllzlc SD Card I r lel 39 Ll Locatlon Asslsled glccel posmnnlng syslem lAGPS recelvei Cell icwer and VVlFl posltlunlng Dlgltal compass Accelemmeter


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