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Computer Architecture

by: Isaac Hauck

Computer Architecture EEL 4768

Isaac Hauck
University of Central Florida
GPA 3.7

Brian Petrasko

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Brian Petrasko
Class Notes
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This 5 page Class Notes was uploaded by Isaac Hauck on Thursday October 22, 2015. The Class Notes belongs to EEL 4768 at University of Central Florida taught by Brian Petrasko in Fall. Since its upload, it has received 65 views. For similar materials see /class/227659/eel-4768-university-of-central-florida in Electrical Engineering at University of Central Florida.

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Date Created: 10/22/15
EEL 4768C and CDA 4150 Fall 2007 Tentative Course Outline Computer System Design IIComputer Architecture PR EEL4767C or CDA3103 Control and data path design using a hardware description language micro programmed architectures instruction pipelines cache and virtual memory and RISC This includes basic processor design hardwired and microprogrammed control ALU memory organization pipelining IO and computer arithmetic Instructor Dr Brian Petrasko Of ce HEC 211 Tel 8232549 Email petraskomailucfedu Of ce Hrs MW 1230230 TR 330430 Home page http wwweecsucfeducourseseel4768 Text Hennessy J and Patterson D Computer Architecture Fourth Edition Morgan Kaufmann Reference Texts Patterson D and Hennessy J Computer Organization and Design Third Edition Morgan Kaufmann Cragon Harvey G Computer Architecture and Implementation Cambridge University Press Roth C H Jr Fundamentals of Logic Design 5th Edition Pellerin David and Douglas Taylor VHDL Made EasyPrentice Hall Grading 2 Exams20 and Final 30 Laboratory 20 Homework and Quizzes 10 Note 1 Assigned homework may be collected for grading or may be replaced by an unannounced quiz 2 Unprofessional behavior may result in a lowering of the grade in an evaluation unit andor the course 3 Attendance is expected and may enter into the grade calculation 4 Cell Phones are to be turned off during class Lecture Topics Schedule Tentative Review of Logic Design and Intro To VHDL Notes 3 weeks RTL Data Path and Control Level of Design and VHDL Notes 3 weeks Instruction Set Principles and MIPS Chapter 1 and Appendix B Topics 2 weeks CPU Design Notes and Appendix A Topics 3 weeks Memory System Design Appendix C Topics 2 weeks IO and Current Architectures Notes 1 week Laboratory Topics Schedule Lab will begin in the second week This is the rst offering of this colocated course The laboratory component is structured as an open lab Laboratory assistants will be in the laboratory Rm ENl257 at speci ed times EEL 4768C lab sections times to assist in the coding and the interpretation of results The laboratory exercises will be presented in class and performance will be evaluated by completion and reporting Laboratory topics will also be included in homework quizzes and exams There will be ve assignments on the following topicsVHDL Introductory Examples 6 weeks VHDL Simple Microcomputer SM Design Project 3 weeks VHDL Extension of the Simple Microcomputer 3 weeks Objectives Tlme References Links Discussion Procedure Reporting Requirements EEL47 68 Fall 2007 Laboratory 1 Modeling Combinational Logic using the data ow styles of description One week Listing of model of an ANDINVERT circuit Class Notes VHDL References httpesdcsucredulabstut0rialVHDL7Pagehtml Contrasting VHDL Verilog and C httpwwwangelf1rec0m inrajesh52verilogvhdlhtml VHDL is a Hardware Description Language HDL It is used to model and simulate digital circuits A VHDL environment consists of a library and software tools which support the design and testing of digital circuits The VHDL environment that is used in this laboratory is Electronic Workbench s Multisim 2001 In this laboratory you will code and test the models of the simple sequential logic circuit presented in class Access the VHDL package of Mulisim 2001 See the notes on the white board or access the course web page Code the LevelitoiPulse Converter of Notes 1 using the data ow description style Use 2ns delays and a lOns 1 pulse that begins 5ns after t0 Modify your model by changing all of the delays to delta delays and rerun your model Exercise the debug features by creating and correctng errors in the source code This is an individual laboratorynot a team effort The report is due at the start of the period for the next laboratory experiment The report is to include the design documentation shown below The timing diagrams and0r text report must be annotated to highlight the results of your work Design Documentation A Cover pageiCourse Number Lab Experiment Number Name and Date submitted B Executive SummaryiA circuit that performs Level to Pulse Conversion was modeled using Attachment xxx presents The signal has a false l or glitch The glich is due to Attachments 2 Logic Diagram 3 Listingiwith header and comments 4 Annotated Timing Diagram C Questions What is the delay and duration of the false 1 for the lns delay model Of the delta delay model Example Listing See Notes 1 for annotated listing The following example is an AND gate followed by an inverter Three types of descriptions for the architecture of the circuit system are presented This example has 4 entitiesthe test bench for system is tbsystem The testbench performs an exhaustive test COMPONENT AND2 entity and2 is portab in bit c out bit end and2 architecture df of and2 is begin c lt a and b after 2nsdelay oftwo nanoseconds end df COMPONENT INVl entity invl is porta in bit c out bit end invl architecture df of invl is begin c lt not a after 2nsdelay of two nanoseconds end df ENTITY SYSTEM THIS IS THE UNIT UNDER TEST OR UUT entity system is portxlx2 in bit 2 out bit end system library and use statements are not needed because components are in the same file as the architecture that uses themthis file is referenced as work for configuration statements Multisim does not support configuation declarations The default confiuration is the last architecture compiled STRUCTURAL ARCHITECTURE FOR SYSTEM architecture eXl of system is signal a bit component and2 portab in bit c out bit end component component declation is not required for 1993 standard component inVl porta in bit c out bit end component begin and21 and2 port mapXlX2a inVll inVl port mapaz end eXl DATAFLOW ARCHITECTURE FOR SYSTEM architecture eX2 of system is signal a bit begin alt X1 and X2 after 2ns zlt not a after 2ns end eX2 BEHAVIORAL ARCHITECTURE FOR SYSTEM architecture eX3 of system is begin plabel processXlX2 variable a bit begin a X1 and X2 2 lt not a after 4ns end process end eX3 TEST BENCH TBSYSTEM FOR TESTING SYSTEM entity tbsystem is end tbsystem architecture eX of tbsystem is signal tVltV2tV3 bit component system portXlX2 in bit 2 out bit end component for all system use entity worksystemeXlcon gure for structure architecture begin uut system port maptVltV2tV3 tVl lt 1 after 20nsINPUT TEST VECTORS FOR EXHAUSTIVE TEST tV2 lt 391 after lOns 390 after 20ns 391 after 30ns 39039 after 40ns end eX


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