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## Digital Logic

by: Fredy Okuneva

17

0

5

# Digital Logic ECE 240

Fredy Okuneva
UI
GPA 3.81

Staff

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COURSE
PROF.
Staff
TYPE
Class Notes
PAGES
5
WORDS
KARMA
25 ?

## Popular in ELECTRICAL AND COMPUTER ENGINEERING

This 5 page Class Notes was uploaded by Fredy Okuneva on Thursday October 22, 2015. The Class Notes belongs to ECE 240 at University of Idaho taught by Staff in Fall. Since its upload, it has received 17 views. For similar materials see /class/227742/ece-240-university-of-idaho in ELECTRICAL AND COMPUTER ENGINEERING at University of Idaho.

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Date Created: 10/22/15
COEEE 243 Session 34 Page 15 Digital Logic Spring 2003 EECompE 243 State Machine Analysis Examples 1 For the state machine shown in the gure below do the following a Find the excitation equations for the ip ops Then construct a transition table a state table and a state diagram Is this a Moore Machine or a Mealy Machine b What is the output sequence when the input sequence is X01100 c Draw a timing diagram for the input sequence from part b Show PC X A B and Z Assume input changes between clock pulses a Derive state equations JA X B XB 39 X39B XB KA X39B JBX A39 XA KBX39A3939 XA A JAQ K Q X39B XB A39 X B39A A BX39A39B XAXAB 3JBQ KgQ XAB39XA39B COEEE 243 Session 34 Page 25 Digital Logic Spring 2003 AB X BX39 A39B Z A39B39 AB It is a Moore machine since Z only depends on A B not on X Present State Next State AB Present State Next State AB X0 X 1 Z AB X0 X 1 Z 00 00 10 0 SO S0 S3 0 0 1 1 1 0 1 0 S 1 S2 S 1 0 1 1 01 10 1 32 S 1 S3 1 10 10 1 1 0 S3 S3 S2 0 1 1 0 1 0 b Based on the stateoutput diagram above we see that Z will be 1 only whenAB 11 Note also that we can consider the initial output for Z to be a false output until the rst falling edge of the clock So we get Z 000101 as shown in the gure below c Timing diagram for network Propagation delay is assumed to be 0 Pc X COEEE 243 Digital Logic Session 34 Page 35 Spring 2003 2 Do the following for the state machine shown below a Construct a state table and state diagram Q1Q2Q3 Z state Q1Q2Q3 X0 X1 X0 X1 S0 000 001 001 0 1 S1 001 011 011 0 1 S2 010 100 101 1 0 S3 011 010 011 1 0 S4 100 001 001 0 1 S5 101 011 011 0 1 S6 110 100 101 1 0 S7 111 010 011 1 0 00 11 COEEE 243 Session 34 Page 45 Digital Logic Spring 2003 b Draw a timing diagram for the network Show X clock Q1 Q2 and Q3 Use the input sequence X01011 and assume that X changes midway between clock pulses Indicate any false output changes Clock T False c Compare output sequence from timing diagram with the one predicted by the state diagram From timing diagram 0 l 0 l 0 1 From state diagram 0 l l 0 l d How can you correct the difference By changing input on falling edge of the clock the false outputs can be eliminated 3 A Mealy synchronous state machine has 1 input 1 output and 2 ip ops A timing diagram is shown below Construct a state table and a state diagram Propagation delay is assumed to be 0 diVision Clock X A B Z Since the timing diagram shown here is for a Mealy sequential network we know that the Mealy network depends on both the present state and the inputs For this network X is the input and Z is the output and Q1 Q2 represent the present states COEEE 243 Session 34 Page 55 Digital Logic Spring 2003 The state table can be constructed by simply nding the output valueZ for various input combi nations from the timing diagram Present State Next State Q1 Q2 2122 Q1Q2 Xo X1 Xo X1 oo 01 1o 1 o 01 oo 11 o 1 1o 11 oo 1 o 11 1o 01 o 1 Present State Next State Q1 Q2 2122 Q1Q2 X0 X1 Xo X1 so 31 sz 1 0 31 so 33 o 1 sz 33 so 1 0 s3 sz 31 o 1

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