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High Performance Computer Architecture

by: Tamia Bernhard

High Performance Computer Architecture 22C 160

Marketplace > University of Iowa > ComputerScienence > 22C 160 > High Performance Computer Architecture
Tamia Bernhard
GPA 3.87


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Class Notes
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This 5 page Class Notes was uploaded by Tamia Bernhard on Friday October 23, 2015. The Class Notes belongs to 22C 160 at University of Iowa taught by Staff in Fall. Since its upload, it has received 26 views. For similar materials see /class/228056/22c-160-university-of-iowa in ComputerScienence at University of Iowa.


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Date Created: 10/23/15
Very Long Instruction Word VLIW Architectures 5513222C160 High Performance ComputerArchitecture What Is VLIW o VLIW hardware is simple and straightforward o VLIW separatelydirects each functional unit VLIW Instruct n Execution Historical Perspective Microcoding nanocoding and RISC microcode q r I store datapath control I Macro Instructions nanocode store datapath control Horizontal Microcode and VLIW o A generation of highperformance applicationspeci c computers relied on h Wally microprogramme computing engines microcode level provided performance well above sequential processors Principles of VLIW Operation 0 Staticalty scheduled ILP architecture VLIW Instruct n 9 10071000 bits 0 Multiple functional units execute all ofthe operations in an instruction concurrently providing negrain parallelism within each instruction Instructions directly control the hardware with no interpretation and minimal deco ing 0 A powerful optimizing compiler is responsible for locating and extracting ILP from the program and for scheduling operations to exploit the available parallel resources 9 The plosessor doe s nof make any FUDMUG comm I decisions beiow ma program level Formal VLIW Models 0 Josh Fisher proposed the rst VLIW machine at Yale 1983 o Fisher s Tram Sched 39 galgorithmfor microcode compaction could exploit more ILP than any existing processor could provide 0 The ELI512 was to provide massive resources to a single instruction stream 16 processing clusters multiple functional unitscluster partial crossbarinterconnect multiple memory banks attached processor no IIO no operating system 0 Later VLIW models became increasingly more regular Compilercomplexity was a greaterissue than originally envisioned Ideal Models for VLIW Machines 0 Almost all VLIW research has been based upon an ideal processor model 0 This is primarily motivated by compiler algorithm developers to simplify scheduling algorithms and compiler data structures This modelincludes Multiple universal functional units Singlecycle global register le and often Singlecycle execution UnrestrictedMultipo1ed memory Multiway branching and sometimes Unlimited resources Functional units registers etc VLIW Execution Characteristics Global MultiPorted Register File ill IL FunctionaI39rl Functionalll Functionglr FunctlonalIl I IUnltUnltlll nitlllUnltl nn E n SequenceZE Saw VLIW gruntsrunes are 9 generazed form omcmomIy microptogrammed marmes VLIW Design Issues 0 Unresolved design issues The best functional unit mix Register le and interconnect topology e m design Best instruction form at 0 Many questions could be answered through experimental research Dif cult needs effective retargetable compiler Compatibilityissues still limit interest in generalpurpose VLIW technology 0 However VLIW ma y be the only way to build 8 l 5 Operationcycle machines Realistic VLIW Datapath v I I FMul I I FMU 139 I FDW 1r NoBypass MVC pipe E 4cyc nplpg l i 16 cycle No 35 F n 1 I l I Condition Codesl I Sequenc E I Scheduling for FineGrain Parallelism o The program is translated into primitive RISCstyle three address operations 0 Data ow analysis is used to derive an operation precedence graph from a portion of the original program 0 Operations which are independent can be scheduled xecute concurrently contingent upon the availability of resources 0 The compiler manipulates the precedence graph through a variety of semanticpreservin transformations to expose additional parallelism eab cd Original Program VLIW Instructions VLIW List Scheduling o Assign Priorities 9 ist all 39 r A have been scheduled 0 Select from DRL in priority order while checking resource constraints 0 Add newly ready operations to DRL and repeat for next instruction 5 x A Eajhait t L l bL A L Enabling Technologies for VLIW o VLIW Architectures attempt to achieve high performance through the combination ofa number of key enabling hardware and software technologies Optimizing Schedulers compilers Static Branch Prediction Symbolic Memory Disambiguation Predicated Execution Software Speculative Execution Program Compression Strengths of VLIW Technology 0 Parallelism can be exploited at the instruction level Available in both vectorizable and sequential programs 0 Hardware is regular and straightforward Most hardware is in the datapath performing useful computations Instruction issue costs scale approximatety linearly olenialiy vary53 doc rat 0 Architecture is Compiler FriendV r r quot layer 39 r Compile time information is easily propagated to run time o Exceptions and interrupts are easily managed o Runtime behavior is highly predictable Allows realtime applic tio s a Greater potential for code optimization Weaknesses of VLIW Technology 0 No object code compatibility between generations 0 Program size is large explicit NOPs Mu quot raw Hines was uynaml memmy r encoding mains Me mast52m u o Compilers are extremely complex ssem ycode is almost impossible o Dif culties with variable memory latencies caching o VLIW memory systems can be very complex Sim ple memory systems may provide very low performance Program controlled multilayer multibanked memory 0 Parallelism is underutilized for some algorithms VLIW vs Superscalar Real VLIW Machines IBM Yorktown VLIW Computer research machine 0 SingleChip VLIW Processors Intel iWarp Philip39s LIFE Chips research 0 SingleChip VLIW Media throughput Processors Trimedia Chromatic MicroUn39ty o DSP Processors Tl TMS32OCBX o IntelHP EPIC lA64 Explicitly Parallel Instruction Comp 0 Transmeta Crusoe x86 on VLIW 0 Sun MAJC Microarchitecture for Java Computing


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