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# ETEE Laboratory VII (Comp Emp) ETEE 3255

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GPA 3.66

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This 71 page Class Notes was uploaded by Paolo Thompson IV on Sunday October 25, 2015. The Class Notes belongs to ETEE 3255 at University of North Carolina - Charlotte taught by Stephen Kuyath in Fall. Since its upload, it has received 13 views. For similar materials see /class/228974/etee-3255-university-of-north-carolina-charlotte in Electrical Engineering at University of North Carolina - Charlotte.

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Date Created: 10/25/15

Topic 11 Finite State Machines Objectives To understand and be able to implement Finite State Machines FSM The difference between Mealy and Moore type FSMs The concept of states and their implementation with flip flops Synchronous control using a clock Behavior of synchronous sequential circuits Design techniques for synchronous sequential circuits VHDL design specification of FSMs 1 0222007 Sequential Circuits Sequential Circuits A class of circuits in which the outputs depend on both the inputs to the circuit and the present state of the circuit past behavior Synchronous uses a clock for control Easierto design than asynchronous Used in the vast majority of practical applications Asynchronous does not use a clock 1 0222007 Synchronous Sequential Circuits Synchronous Sequential Circuits Use combinational logic Use one or more flipflops Sometimes referred to as registers Outputs of the flipflops is referred to as the State of the circuit or state of the machine Flipflops change their state based on the input logic W L Input Flip39 ops L Output Logic or gt Circuit Reglsters 39 Logic Q Circuit Clock 1 0222007 Synchronous Sequential Circuits Input Logic Circuit Acquires inputs from two sources Primary inputs w Register outputs Q Changes in state of the FSM depend on both Present State Primary Inputs W L Input Flip39 ops L Output Logic 3 or r Logic Circuit Reglsters Q Circuit Clock 1 0222007 Synchronous Sequential Circuits Output Logic Circuit Moore FSMs acquire inputs from register outputs only The present state of the machine The connection in blue does not exist Mealy FSMs acquire inputs from register outputs AND the primary inputs The present state of the machine The connection in blue does exist W L Input Flip39 ops L Output Logic or 7 Logic Circuit Registers Q Circuit Clock 1 0222007 FSM Design Steps 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states I Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6quot Implement the design 1 0222007 Design Example 1 Design a FSM that will continuously perform the following count 042 1042 10 1 0222007 Design Example 1 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states 1 Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 1 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states 1 Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 1 There is no enable or any other input to this machine so we will Choose 0 as the starting point arbitrary Choice and then progress through the sequence 1 0222007 Design Example 1 There is no enable or any other input to this machine so we will choose 0 as the starting point arbitrary choice and then progress through the sequence This state diagram shows all of the possible states The conditions for progressing to the next state is just the current state 1 0222007 Design Example 1 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states 1 Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 1 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states I Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 1 From the state diagram develop the state table The state table should show both the current state and the next state Start a 0 Current 1 0222007 Design Example 1 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states 1 Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 1 From the state diagram develop the state table The state table should show both the current state and the next state Start a 0 Current We must now determine how many state variables are needed Any Ideas 1 0222007 Design Example 1 From the state diagram develop the state table The state table should show both the current state and the next state Start a 0 Current We must now determine how many state variables are needed The number 4 in the count requires that we have 3 state bits name these bits A B and C Current Next I ll also expand the State Table to show this 1 0222007 Design Example 1 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states 1 Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current St t Start a e ABC 000 100 010 001 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Next Sta rt State State ABC ABC 000 100 100 010 010 001 001 000 The excitation table for D flipflops is shown below QT D QM 0 0 1 1 To change a D flipflop s output Q from a O to a 1 place a 1 at the input D To change a D flipflop s output Q from a 1 to a 0 place a O at the input D 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Next Sta rt State State ABC ABC 000 100 100 010 010 001 001 000 The excitation table for D flipflops is shown below QT D QM 0 0 1 1 To change a D flipflop s output Q from a O to a 1 place a 1 at the input D To change a D flipflop s output Q from a 1 to a 0 place a O at the input D So the table above must be filled in to show what inputs are necessary at the inputs D to change from the current state to the next state 10222007 22 r Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current St t Start a e ABC 000 100 010 001 We must now develop the next state logic for the Input Logic Circuit But before we do this we must include all the possible current states for A B and C even if they are not used 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Sta rt ABC 000 001 010 011 100 101 110 meme xo l l l Note that all possible values for A B and C are now in the table For those states that are not used the Next State column specifies don t care states This is because the FSM should never enter those states 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Start a 0 ABC 000 001 010 o a 100 101 110 meme xo l l l We can now determine the inputs to the Registers for each state develop the Input Logic Circuit We will use Karnaugh maps to do this 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs a o Current DA 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs a o Current ABC 000 001 010 011 100 DA 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Next Sta rt a 0 State State State D DR Dr ABC ABC 0 000 100 1 0 0 1 001 000 0 0 0 2 010 001 0 0 1 n a 3 011 4 100 010 0 1 0 5 101 l 6 110 7 111 DA r 1 0 o o 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Next Sta rt a 0 State State State D DR Dr ABC ABC 0 000 100 1 0 0 1 001 000 0 0 0 2 010 001 0 0 1 n a 3 01 1 4 100 010 0 1 0 5 101 6 1 10 7 1 1 1 I DA 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Sta rt ABC 000 001 010 011 100 101 110 meme xo l l l DA lt9 f DAABC 0 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Sta rt ABC 000 001 010 011 100 101 110 meme xo l l l 03 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Sta rt ABC 000 001 010 011 100 101 110 meme xo l l l Dc 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Start a 0 ABC 000 001 010 o a 100 101 110 meme xo l l l There is no need to develop expressions for the Output Logic Circuit because the outputs will be taken directly from the register outputs Qs 1 0222007 Design Example 1 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states I Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 1 I chose D flipflops to implement this counter The State Table was expanded to include the three required D inputs Current Sta rt ABC 000 001 010 011 100 101 110 meme xo 111 So now we must implement the design We have three D flipflops and the following expressions for the Input Logic Circuit 1421 35 DBA DCB 1 0222007 Design Example 1 Simulation To simulate impemented a schematic Note Xilinx didn t have any flipflops with a connection for Q so I had to use inverters E o a 1 D3A L FD 1 0222007 Design Example 1 Simulation Atest bench waveform was then developed Note it only needed to have a Clock assigned End Time 2000 quot5 100115 300 ns SUD ns VEIIJ ns 900 ns 1100 ns 1303ns 1503n9 HDJns 1QUJI39IS I l I DDDD 1 0222007 Design Example 1 Simulation Atest bench waveform was then developed Note it only needed to have a Clock assigned End Time 200 quot5 100 ns 300 ns sun ns 700 ns 900 ns 1100 ns 1303ns 1503ns HDJns 1ElDJns I 1 I Then Modelsim was activated to determine if the Circuit simulated as it should 1 0222007 Design Example 1 Simulation Atest bench waveform was then developed Note it only needed to have a Clock assigned EndTime 2000 100113 sunns 500m mnns Q ns 11EIDns iaujns isujns HDJns lg jns llllll MCI l 111A 1119 MC Boot Then Modelsim was activated to determine if the Circuit simulated as it should lcnt wf clk quot lentilwfla r cntrlwfib fcnt wfc 1 0222007 Design Example 1 VHDL library IEEE use EEESTDLOGC1164ALL use EEESTDLOGCARITHALL use EEESTDLOGCUNSIGNEDALL entity CntrV1 is Port Clk reset in stdlogic Q out stdlogicvector 2 DOWNTO 0 end CntrV1 architecture Behavioral of CntrV1 is Signal Count stdlogicvector 2 DOWNTO O begin Process Clk reset Begin IF Reset 39039 THEN Count lt quot000quot ELSIF CIk39EVENT AND Clk 39139 THEN If Count quot000quot then Count lt quot100quot Elsif Count quot100quot then Count lt 0quot Elsif Count quot010quot then Count lt quot001quot Else Count lt quot000quot End If End If End Process Q lt Count end Behavioral lt5 4 The VHDL Design Description was developed for the FSM Note Xilinx seems to like Double Quotes better than single The errors I got were unexpected tick 1 0222007 Design Example 1 VHDL library IEEE use EEESTDLOGC1164ALL use EEESTDLOGCARITHALL use EEESTDLOGCUNSIGNEDALL entity CntrV1 is Port Clk reset in stdlogic Q out stdlogicvector 2 DOWNTO 0 end CntrV1 architecture Behavioral of CntrV1 is Signal Count stdlogicvector 2 DOWNTO O begin Process Clk reset Begin IF Reset 39039 THEN Count lt quot000quot ELSIF CIk39EVENT AND Clk 39139 THEN If Count quot000quot then Count lt quot OOquot Elsif Count quot100quot then Count lt quot010quot Elsif Count quot010quot then Count lt quot001quot Else Count lt quot000quot End If End If End Process Q lt Count end Behavioral A The VHDL Design Description was developed for the FSM Note Xilinx seems to like Double Quotes better than single The errors I got were unexpected tick When the description synthesized a testbench waveform was developed that was very similar to the previous The previous had A B and C whereas this one had Q2O 1 0222007 Design Example 1 VHDL This is the testbench waveform End Time 2000 1DUns sunns SUUns mans Q ns HUUns 1300M 1SDDnS 1TEIDnS 1900n3 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Monk WW I I I I I I l I I I a 3mm 111912 111 QIIQIUI DDDD D This is the output from Modelsim Jcntr lvwfinlk 7 1 J Ibnt vwh39reset H I rt 6 1 0222007 Design Example 2 Description We wish to design a circuit that Has one input w and one output z The output z should go high if there were two consecutive high inputs on w All changes in the circuit occur on the positive edge of the clock 1 0222007 Design Example 2 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states 1 Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 2 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states 1 Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 2 The state diagram below describes the specified circuit 1 0222007 Design Example 2 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3D Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states I Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 2 The state diagram below describes the specified circuit The state table describes in tablature style the state diagram But this table doesn t have enough information Reset Present Input Next Output State W State 2 A 0 A 0 1 B 0 B 0 A 0 1 C 0 C 0 A 1 1 C 1 w1 We must decide how many state variables are required to fully implement this design with registers Each registerwill require a state variable 1 0222007 Design Example 2 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states 1 Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 2 This State Table provides all the information we need There are 3 possible states so we will need 2 state variables yO and y1 With 2 state variables with can have 4 possible states that s how D came into the picture Reset Present Next State Input State Y1YO W Y1 Yo 0 0 w1 Output This FSM should never enter state D so it had no effect on the next state orthe output but it will have an impact when designing the Input Logic Circuit and possibly the VHDL file 1 0222007 Design Example 2 This State Table provides all the information we need There are 3 possible states so we will need 2 state variables yO and y1 With 2 state variables with can have 4 possible states that s how D came into the picture Reset Present Next State Input State Y1YO W Y1 Yo 0 0 w1 Output This FSM should never enter state D so it had no effect on the next state orthe output but it will have an impact when designing the Input Logic Circuit and possibly the VHDL file We now have to decide what kind of flipflops will be used 1 0222007 Design Example 2 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states 1 Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 2 This State Table provides all the information we need Because there are 3 possible states we will need 2 state variables yO and y1 With 2 state variables with can have 4 possible states that s how D came into the picture Reset Present Next State Input State Y1YO W Y1 Yo 0 0 w1 Output This FSM should never enter state D so it had no effect on the next state orthe output but it will have an impact when designing the Input Logic Circuit and possibly the VHDL file We now have to decide what kind of flipflops will be used I ll choose D flipflops again because they are easy to implement 1 0222007 Design Example 2 For D flip flops the output Q always follows the input D on transitions of the clock So for D flipflops we only need to look at the Next State state variables Pre sent State Output 1 0222007 Design Example 2 For D flip flops the output Q always follows the input D on transitions of the clock So for D flipflops we only need to look at the Next State state variables Pre sent State Output Note that the next state for state A state variable y1 is always 0 so the input D can always have a 0 applied for this state 1 0222007 Design Example 2 For D flip flops the output Q always follows the input D on transitions of the clock So for D flipflops we only need to look at the Next State state variables Pre sent State Output Note that the next state for state A state variable yO is 0 when w is O and 1 when w is 1 so the input D follows the state ofw forthis state Look over States B and C to confirm the inputs to the D fipfops 1 0222007 Design Example 2 We can now put these values in a Karnaugh map to determine the logic expression for the input to D1 Pre sent State Output D1 1 0222007 Design Example 2 We can now put these values in a Karnaugh map to determine the logic expression for the input to D1 Pre sent State Output 10222007 58 Design Example 2 We can now put these values in a Karnaugh map to determine the logic expression for the input to D0 Pre sent State Output Do 1 0222007 Design Example 2 We can now put these values in a Karnaugh map to determine the logic expression for the input to D0 Pre sent State Output Do 1 0222007 Design Example 2 We now must develop an expression for the output 2 Pre sent State Output Upon examination you can see that z y1 1 0222007 Design Example 2 1 Obtain the specifications of the desired circuit 2 Derive the states of the machine and develop a state diagram 1 Should show all possible states 2 Provide the conditions for which the circuit moves from one state to the next 3n Develop the state table from the state diagram 4 Decide on the number of state variables needed to represent all states 1 Minimize the number of states if possible 5 Choose the type of flipflops that will be used in the implementation 1 Derive the nextstate logic expressions to develop the Input Logic Circuit 2 Derive the logic expressions for the Output Logic Circuit 6 Implement the design 1 0222007 Design Example 2 Implementation The circuit was implemented as a schematic and a VHDL description in Xilinx Xilinx did not have a D flip flop with active low CLR inputs so an inverter was used on the Reset input the specifications called for an active low Reset 10222007 63 Design Example 2 Simulation The test bench waveform shown below was entered to test the circuit End Time 2500 HS 100 ha 500 ha 900 ns 1300 ns 1mm ns 21 00 ns 2an n l I I I I I I I I l I I I I I I I I I Clock 0 IIIIIIIIIIIIIIIII I39IJIReset 0 I I I I I I I I I I I 1112 0 I I I I I I I I I I 1 0222007 Design Example 2 Simulation The test bench waveform shown below was entered to test the circuit End Time 2500 NS 100 ha 500 ns 900 ns 1300 ns 1mm ns 21 no he 2an n l I I I I I I I I I l I I I I I I I I I Clock 0 W MReset 0 I I I I I I I I I I I W U I I I I I II JI linz 0 I I I I I I I I I I I I 18381 swffclock fesB1 395wa reset 39 Jein swffw 39 I m81 awffz The output 2 was to provide a high output whenever the input w remained high for two consecutive clock cycles i 1 0222007 Design Example 2 VHDL Then the VHDL Design Description was developed for the FSM in example 2 it was a little too long to fit on 1 page library lEEE use lEEESTDLOGC1164ALL use lEEESTDLOGCARTHALL use lEEESTDLOGCUNSIGNEDALL entity ex81 is Port Clock in stdlogic Reset in stdlogic w in stdlogic z out stdlogic end ex81 1 0222007 architecture Behavioral of ex81 is Type StateType Is A B C Signal y StateType begin Process Clock Reset Begin If Reset 39039 Then y lt A Elsif Clock39Event AND Clock 39139 then CASE y IS When A gt lF w 39039 then y lt A Else y lt B End If When B gt lF w 39039 then y lt A Else y lt C End If When C gt lF w 39039 then y lt A Else y lt C End If End CASE End If End Process 2 lt 39139 When y C Else 39039 end Behavioral Design Example 2 VHDL This file used a couple new statements The 1st is the TYPE statement TYPE allows us to create a new data type The new data type in this example is StateType and can take on values of A B or C The variable y was then declared a StateType variable 1 0222007 architecture Behavioral of ex81 is Type StateType Is A B C Signal y StateType begin Process Clock Reset Begin If Reset 39039 Then lt A Elsif Clock39Event AND Clock 39139 then CASE y IS When A gt lF w 39039 then y lt A Else y lt B End If When B gt IF w 39039 then y lt A Else y lt C End If When C gt lF w 39039 then End Process 2 lt 39139 When y C Else 39039 end Behavioral Design Example 2 VHDL This file used a couple new statements The 1st is the TYPE statement TYPE allows us to create a new data type The new data type in this example is StateType and can take on values of A B or C The variable y was then declared a StateType variable The CASE statement is then used to switch on y and assign the appropriate next state based on the value of w Finally at the end 2 is assigned a value based on the current state State C is the only time 2 should go high architecture Behavioral of ex81 is Type StateType Is A B C Signal y StateType begin Process Clock Reset Begin If Reset 39039 Then lt A Elsif Clock39Event AND Clock 39139 then CASE y IS When A gt lF w 39039 then y lt A Else y lt B End If When B gt IF w 39039 then y lt A Else y lt C End If When C gt lF w 39039 then End Process 2 lt 39139 When y C Else 39039 end Behavioral Design Example 2 VHDL Below is the circuit synthesized by Xilinx It is a little different than the other but functions the same 10222007 69 Design Example 2 Simulation Below is the test bench waveform used to test the VHDL description End Time 2500 HS 100 ns 500 ha 900 ns 130D n3 HDIU ns 2100 ns 2500 n I 1 I Clock 1 uReset 1 meII IIIIIIIII I Illz o quot JekB i wffclock quot R2331 wfi resel quot 22331 wiiw v39eMB i wf z 1 0222007 Summary 39 In this topic we implemented several FSMs and Determined the difference between Mealy and Moore type FSMs Learned and applied the concept of states and their implementation with flip flops Implemented synchronous control using a clock Noted the behavior of synchronous sequential circuits Developed and tested a set of Design techniques for FSMs Developed several VHDL design specifications for specified FSMs and then implemented the descnp ons 1 0222007

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