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# Digital Logic Design ETEE 3183

UNCC

GPA 3.81

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This 112 page Class Notes was uploaded by Della Daniel on Sunday October 25, 2015. The Class Notes belongs to ETEE 3183 at University of North Carolina - Charlotte taught by Stephen Kuyath in Fall. Since its upload, it has received 32 views. For similar materials see /class/228975/etee-3183-university-of-north-carolina-charlotte in Electrical Engineering at University of North Carolina - Charlotte.

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Date Created: 10/25/15

Digital Logic Design Prerequisites by Topic 8282007 Prerequisites Demonstrated understanding of binary octal decimal and hexadecimal number systems and arithmetic operations A demonstrated understanding of fundamental digital electronics including the logic and electrical operating characteristics of AND OR XOR NAND and NOR gates Ability to apply circuit reduction techniques using Boolean algebra and Karnaugh maps 23 8282007 Number Systems Number Systems Binary base 2 Decimal base 10 Hexadecimal base 16 Octal base 8 Arithmetic Add Subtract Multiply and Divide Conversions Between any two number systems W33 8282007 Logic Gates AND 17 OR 0 NOT Inverter 3 NAND 3 D XOR Exclusive OR 8282007 8282007 NOT Inverter XOR Exclusive ORE AND oo oo w Aooolx NAND Truth Tables Electrical Characteristics Voltage levels for equivalent logic levels What we say Logic 1 2 5v Actual Typical Logic 1 z 32 34V Range of allowable Logic 1 z 2 55V What we say Logic 0 2 UV Actual Typical Logic 0 2 04V Range of allowable Logic 0 2 O 08V 8282007 Other Electrical Characteristics Fanout Source Current Sink Current Timing Characteristics Propagation Delays Rise Fall Times Positive Negative Logic Conversion Noise Margins Open Collector Drain Circuits and PullUp Resistors1 73 8282007 1 We will review and expand this topic Boolean Arithmetic Sumof Products SOP Minterms Ex XABCDAC Productof Sums POS Maxterms Ex X ABCCD Identify amp Convert Axioms Theorems Properties W83 8282007 A oms OOO 111 111 OOO O11OO 1OO11 If XOthen71 Ifx1thenYo 8282007 Theorems Identities XOO X11 X1X XOX XXX XXX XYo 71 X X X 8282007 Properties Laws Commutative XYYX XYYX Associative XYZXYZ XYZXYZ Distributive XYZXYXZ XYZXYXZ 8282007 Properties Laws Absorption XXYX XXYX Combmkg XYXV X YX X X 8282007 DeMorgan s Theorem oXYY oXYR ltrlt XYYXY oXHYwXY YVX Y Y X lt 8282007 Synthesis Once a Boolean expression is known the student should be able to implement the circuit using the basic logic gates Student should be able to convert from positive to negative logic and vice versa Student should be able to simplify a Boolean expression to its simplest terms Using Boolean Algebra Using Karnaugh Maps1 8282007 1 We will review and expand this topic 14 Other Concepts Flip Flops amp Latches1 SR JK amp D MSI ICs1 Counters Multiplexers MUXs DeMultiplexers DeMUX Decoders Encoders 8282007 1 We will review and expand this topic 15 Digital Logic Design Topic 2 Logic Gates and Families Definitions and Characteristics Objectives To review several basic logic gates To review positive and negative logic To become familiar with several static and dynamic characteristics of several logic families Understand fanout Noise margins Open collectordrain resistance calculations 3 Logic Gate Forms Positive Logic A i B AB 3 A Lgto A Negative Logic i Application of Positive Logic Active Level TRUE 1 i X Quiescent Level FALSE 0 Easier for us to analyze and interpret Application of Positive Logic Active Level TRUE 1 i X Quiescent Level FALS 0 Easier for us to analyze and interpret Application of Negative Logic Active Level TRUE 0 Y 1 3 Quiescent Level FALS Circuitry takes less space and draws less power EH Application of Positive Logic Active Level TRUE 1 i X Quiescent Level FALS 0 Easier for us to analyze and interpret Application of Negative Logic Active Level TRUE 0 Y Quiescent Level FALS 1 i Circuitry takes less space and draws less power Negative logic is more commonly used i Neqative Loqic Circuitrv Consider for a moment the schematic diagram of an inverting buffer gt W3 Neqative Loqic Circuitrv Consider for a moment the schematic diagram of an inverting buffer If A VCC the transistor saturates causing the 0 A output to go low 1 A Closed Switch EH Neqative Loqic Circuitrv Consider for a moment the schematic diagram of an inverting buffer A If A VCC the transistor saturates causing the output to go low K Open If A O the transistor Switch cuts off causing the output to go high EH Neqative Loqic Circuitrv The inverting buffer becomes a 2input NOR gate by allowing two inputs to saturate the transistor AB Neqative Loqic Circuitrv Adding an inverting buffer creates an OR gate Note One transistor is always turned on AB This circuit is larger and draws more current EH Neqative Loqic Circuitrv Advantages of using negative logic 0 Smaller footprint allows more dense circuits Lower power consumption Can be used to generate any logic 0 Better noise immunity in quiescent high state Faster switching speed EH Example Convert positive logic to negative logic y AB CD QDM a 3 CD IABCD new Example Convert positive logic to negative logic y AB CD 3 EM H C D IABCD D Replace the summing junction with its negative logic equivalent EH Example Convert positive logic to negative logic yABCDECTD AD B AB Lj mm AME C gt CD D were Example Convert positive logic to negative logic yABCDECTD A B AB 3ABCD AB CD cw D Move bubbles back to product junctions EH Example The negative logic is more ef cient because the circuit is faster amp uses all the same logic gates all on one IC 3 37 AB A Be AB Amco 0 gt CD Positive Logic 1mm ej n D Negative Logic EH Family Characteristics TTL Voltage and Current Characteristics1 Family quotEH V11 V OH V 0L 11 1 11H I0L I0H min V max V min V 111ax vquot max 111A max 111A min 111A 11113911 111A 7431 2 0 08 24 04 16 04 16 04 5433 20 08 24 04 16 04 16 04 HEX 20 03 24 04 20 05 20 05 54km 20 08 24 03 018 01 2 01 74SXX 20 08 27 05 20 05 20 10 T491319 20 08 30 05 05 02 20 20 74LSXX 20 08 27 05 04 02 8 04 20 08 30 04 01 02 8 04 Standard LS S AS Power Dissipation 10111W 2111 1011le 1111W 85111505r Propagation Delay 10118 10113 311 4113 1 5115 1 These are Ballpark values Actual Specification Sheet should be consulted Family Characteristics CMOS Voltage and Current Characteristics1 Family IVIH 00301409 VogTTL VOL CMOS VOLTTL If Io CMOS IOLTTL 103011110 log TTL mm V 00 mm V 1111110 max V max V m mm mm mA mm mA mm 111A mm mA 74HCxx 335 135 334 44 01 033 0001 0001 002 40 002 40 T4HCTxx 20 03 334 44 01 033 0001 0001 002 40 002 40 341ch 335 135 330 44 01 044 0001 0001 005 30 005 30 MAHCTXX 20 03 330 44 01 044 0001 0001 005 30 005 430 Speci cation for CMOS Loads Speci cation for TTL Loads 1 These are Ballpark values Actual Specification Sheet should be consulted Family Characteristics CMOS Power and Timing Characteristics1 HC HCT AlIC AHCT Power Dissipation 001251391 1W 00125mW 0025mm 0025mW Propagation Delayr 9nS IUnS 3nS 5nS TTL Power and Timing Characteristics1 Standard LS S ALB AS Power Dissipation 1 UmW ZmW 19mW ImW 8 infH Propagation Delayr 1018 10113 3nS 4118 15113 1 These are Ballpark values Actual Specification Sheet should be consulted Operation TTL Inverter If input A goes high Transistor turns on saturated output goes low If input A goes low Transistor turns off output gets pulled high Operation TTL NOR Au ATE B N If either A OR B goes high Transistor turns on saturated output goes low If both A and B are low Transistor turns off output gets pulled high Operation TTL OR A At Batik i1 1 l i o If either A OR B goes high Transistor on stage 1 turns on saturated turns off stage 2 transistor and output goes high 0 If both A and B are low Transistor on stage 1 turns off turns on stage 2 AB transistor and output goes low i 23 Operation TTL OR NOTE Stage 1 or stage 2 transistor AB is ALWAYS On A1 31 1 TTL uses a lot of power II o If either A OR B goes high Transistor on stage 1 turns on saturated turns off stage 2 transistor and output goes high o If both A and B are low Transistor on stage 1 turns off turns on stage 2 transistor and output goes low i 24 CMOS Primer NMOS Gate Source J Drain VD Substrate Body T VG NMOS transistor VS 0 V r VG l I I VS VD Simplified symbol for an NMOS transistor VDOV Closed switch when VG VDD NMOS transistor VD Open switch when VG O V CMOS Primer PMOS Gate Drain J 1 Source VS VDD VDD VDD VDD Substrate Body I J VG C I PMOS transistor T VD VD VD VDD Open switch Closed switch VG when VG VDD when VG O V L PMOS transistor I VS VD Simplified symbol for a PMOS transistor CMOS Primer VG NMOS transistor VS 0 V T 1 T Closed switch Open switch when VG VDD when VG O V VS VDD VDD VDD we I PMOS transistor VD VD VD VDD Open switch Closed switch when VG VDD when VG O V i iwff 27 Operation CMOS Inverter Q1 is an Ntype MOS FET this is a simplified circuit and is turned on when a high gate voltage is applied Q2 is a Ptype MOS FET this is a simplified circuit and is turned on when a low gate voltage is applied o lfthe input goes high Q1 turns on Q2 turns off output goes low If the input goes low Q1 turns off Q2 turns on output goes high EH Operation CMOS NAND M Q1 amp Q3 are Ntype MOS FETs and are turned on Q2 Tl Q4 when a high gate voltage is applied 7 X Q2 amp Q4 are Ptype MOS FETs and are turned on A 4 Q1 when a low gate voltage is applied BAEr o If both inputs go high Q1 amp Q3 turn on Q2 amp Q4 turn off output goes low o lfA goes low Q1 turns off Q2 turns on output goes high If B goes low Q3 turns off Q4 turns on output goes high 7 F i 29 Operation CMOS NOR Q1 amp Q3 are Ntype MOS FETs and are turned on A l 92 when a high gate voltage is applied B Q Q2 amp Q4 are Ptype MOS FETs and are turned on X when a low gate voltage is applied Q1 Li Q3 o If both inputs go low Q2 amp Q4 turn on Q1 amp Q3 turn off output goes high o lfA goes high Q2 turns off Q3 turns on output goes low If B goes high Q4 turns off Q1 turns on output goes low W i 30 Comparison In TTL circuits one or more transistors are always on which requires current and causes higher power dissipation In CMOS circuits at least one of the transistors in a pair is off preventing current flow and reduces power significantly as compared to TTL Current flows in CMOS circuits only as the inputsoutputs are changing Definitions VOHMm Minimum Output High Voltage VOLMAX Maximum Output LOW Voltage VDD Gnd Definitions VIHMIN Minimum Input LOW Voltage VILMAX Maximum Input Low Voltage VDD Gnd Definitions NMHIGH HighLevel Noise Margin NMLOW LowLevel Noise Margin VDD Gnd V OH MIN V IH MIN Definitions For devices to be compatible VOLMAX lt VILMAX AND V gt V OHMIN IHMIN DD VOHMIN Gnd Definitions IILMAX Maximum LowLogic Input Current IIHMAX Maximum HighLogic Input Current IOLMIN Minimum LowLogic Output Current IOHMIN Minimum HighLogic Output Current For devices to be compatible IOLMIN gt IILMAX AND IOH MIN gt2 IIH MAX Definitions FAN OUT The maximum number of device inputs that can be driven by a single device output Minimum of IIOLMIN IILMAX I OHMIN IHMAXI 0139 II Why be worried about fanout Example Two TTL Inverters One driving the other A B 1 4le Why be worried about fanout Example Two TTL Inverters Gate A driving Gate B B Vo 34V Why be worried about fanout Example Two TTL Inverters Gate A drivin Gate B A IOH IIH r av zI H Vol a a a a T a a in When Gate A is producing a logic 1 output and is driving too many Gate Bs OH increases causing the output voltage to drop because the voltage across R is increasing This will cause V0 to drop possibly below an identifiable Logic 1 2v Why be worried about fanout Example Two TTL Inverters Gate A driving Gate B A B Vo 04V 4le Why be worried about fanout Example Two TTL Inverters Gate A driving Gate B A x B B B B When Gate A is producing a logic 0 output and is driving too many Gate Bs OL increases causing the output voltage to increase because the voltage across D is increasing This will cause V0 to rise possibly above an identifiable Logic 0 08V Fanout in CMOS VDD VDD The capacitive load at node A Fanout in CMOS Current flow when input VX Changes from O V to 5 V 1D Vx l VDD Vf I Current flow when input VX Changes from 5 V to O V xx 139 V l39YH w d u The effect of fanout on propagation delay N1 Vf To inputs of x To inputs of n other inverters n other inverters L fquot Inverter that drives n other inverters Equivalent circuit for timing purposes Vf for n 1 kaforn 4 0 Time Propagation times for different values of n Example Similar Family HOW many 7400 series TTL inputs can be driven by a single 7400 series TTL output Example Similar Family HOW many 7400 series TTL inputs can be driven by a single 7400 series TTL output IOLMIN 39 oma IILMAX IOHMIN 0 4ma IIHMAX 0 04ma 16ma IIOLMINIILMAX I160 1 6 10 I0HMINIIHMAX 04o 04 10 Fan Out 0 Example Mixing Families HOW many 74ALSOO series TTL inputs can be driven by a single 7400 series TTL output Example Mixing Families How many 74ALSOO series TTL inputs can be driven by a single 7400 series TTL output I 160ma I 01ma OLMIN ILMAX IOHMIN 0 4ma IIHMAX 0 02ma IIOLMINIILMAX I16 0 o 1 1 60 I0HMINIIHMAX 04o 02 20 Fan Out 20 Logic Families To mix logic families 1 Logic Levels must be compatible VOL MAX lt2 VIL MAX V gt2 V OHMIN IHMIN Logic Families To mix logic families 1 Logic Levels must be compatible V lt V OL MAX IL MAX VOH MIN gt2 VIH MIN 2 Current Levels must be compatible IOL MIN gt2 IIL MAX IOH MIN gt2 IIH MAX 3 Fanout must not be exceeded Definitions Propagation Delay The time delay between an event on a device input and a corresponding change on its output VDD Viquot 50 Gna Propagation delay Propagation delay gt gt VDD 90 Veal 50 Gm 10 l r Definitions Rise Time TR The time required for a signal to rise from 10 of its amplitude to 90 of its amplitude VDD 90 90 Voul 39 Gnd 10 10 F tr tf Fall Time TF The time required for a signal to fall from 90 of its amplitude to 10 of its amplitude Common Loqic Families TTL TransistorTransistor Logic Bipolar transistors in commonemitter con guration Over 30 years old Switches currents Slow lOnsdeV typical 100 MHz 0 High power dissipation typically IOmWdev 0 Very reliable commonly used Power supply voltages 5V 0V Common Loqic Families ECLzEmitter Coupled Logic Bipolar highspeed multiemitter transistors eliminate several buffer stages Switches currents Fast 1nsdev typical 1 GHz 0 High power dissipation typically 40mWdev 0 Typical power supply voltages 8V 0V Approx 1V swing in signal from High to Low 0 Low noise margin 015V Common Loqic Families GaAszGaliumArsenide Logic Bipolar highspeed transistors use a Galium Arsenide substrate that is signi cantly faster than silicon Switches currents Very Fast OlnsdeV typical 10 GHz 0 High power dissipation typically ZOOmWdev Power supply voltages 35V 55V 0V Approx 1V swing in signal from High to Low Common Loqic Families MOSMetalOxide Semiconductor Logic Uses a metaloxide gate in a eldeffect transistor as the switch Switches voltages Slow IOOnsdev typical 10 MHz Low power dissipation typically ImWdev Power supply voltages 5 9V Varies Approx 25V swing in signal from High to Low Large gateto drain capacitances limit speed Common Loqic Families CMOSComplementary MOS Logic Uses MOSFET transistors in a comple mentary biased totem pole so that one transistor is always turned off Switches voltages Slow SOnsdev typical 20 MHz Very Low power dissipation lt OlmW 0 Excellent for batterydriven applications Complex power supplies Common Loqic Families Advances in CMOS Technology HCHCT High SpeedHS TTL Compatible Faster than the 4000 level CMOS 10ns Propagation Delay 100 MHz AHCAHCT Advanced HSAHC TTL Compatible Faster than the HCHCT CMOS 37 to 5ns Propagation Delay 200 MHz Open Collector Drain Outputs First let s take a look at a typical TTL TotemPole output EL39 OUT Open Collectorl Drain Outputs If the output is a LOW logic level the Lower transistor must be saturated Open Collectorl Drain Outputs If the output is a HIGH logic level the upper transistor must be saturated and the lower transistor must be off Open Collectorl Drain Outputs What happens if these two TTL outputs are tied together Logic LOW on the left circuit pulls the entire output low IEmFI Open Collectorl Drain Outputs What happens if these two TTL outputs are tied together IEmFI What is the current through the lower transistor in the first stage i 16 mA Open Collectorl Drain Outputs What happens if we tie a third TTL output to the other two 15m 15m What is the current through the lower 3 transistor in the first stage 32 mA Open Collectorl Drain Outputs If we add another the first transistor will have to sink 48 mA i i i 48m i1 Open Collectorl Drain Outputs A LOW on any single gate output pulls the entire circuit output LOW Wire NOR Excessive currents can permanently damage the circuits What can we do Solutions 1 Use an AND gate to combine the outputs TT TT TT TT Solutions 2 Use OpenCollector circuits Such circuits are specially designed to drive a single line with several device outputs Provides capability to switch currents up to 16mA 74XX with flexible Voltage supply values UTPUT 1 V 1 Solutions 2 Use OpenCollector circuits Useful for switching o Relays o Lamps 0 DC Motors 0 Stepping Motors 0 Etc UTPUT Open Collectorl Drain Outputs Any gate can pull the output line low Quiescent HIGH Active LOW Negative Logic RP limits current allowing any V VMAX vceBREAKDOWN Open Collectorl Drain Outputs To determine RP If RP is too small currents through the open collector circuits will be too large and the circuit will be damaged quotIii quotquot T Open Collectorl Drain Outputs I To determine RP If RP is too large insufficient current will be available to switch the junction to a low level EU W RP l x v v i quotIE Fquot I o u quotlquotquotquot39 quotIquotquotquot3939 Open Collectorl Drain Outputs To determine RP The minimum RP current state exists when all 00 circuits are in the high state EU W RP r W w I quotIii quotquot I o u quotlquotquotquot39 quotIquotquotquot3939 Open Collectorl Drain Outputs To determine RP The minimum RP current state exists when all 00 circuits are in the high state N1 N0 of QC Circuits EU Firm e e quotIii quotquot I o u Open Collectorl Drain Outputs To determine RP The minimum RP current state exists when all 00 circuits are in the high state N1 No of 00 Circuits N2 No of driven circuits T g i i e e quotIii quotquot Open Collectorl Drain Outputs To determine RP The minimum RP current state exists when all 00 circuits are in the high state IRPN1OHN2H EU Firm i quotIE Fquot I o u Open Collector Drain Outputs VC C VIHMIN RPMAX N110H N211H 5U R m E fig K I l 4 4 l IIH 53u Open Collector Drain Outputs VC C VIHMIN N110H N211H 50V 27V RPMAX RPMAX 4250uA 2SOyA Open Collector Drain Outputs VC C VIHMIN RPMAX N110H N211H 50V 27V RPMAX 4250A 2501A 23V RPMAX 1100M Open Collector Drain Outputs The maximum RP current state is 0L in any single 00 output The 00 output must sink both RP and NZIIL IOL IRP NZIIL EU R m v29 390L 7 EL Open Collectorl Drain Outputs So the current through RF is shown by the formula below IRPOL39 NZIIL EU R 39 GUTPUT t v29 quotquot 39quotquot I Fo u Ir Open Collector Drain Outputs VCC VILMAX RPMIN 10L N 211L 9 11 EBmFI RP DUTPUT Inquot 252141 E l l 1 1 IIquot 53un Open Collector Drain Outputs VCC VILMAX RPMIN 0L N211L RPM 50V O5V 20 mA 2 20mA Open Collector Drain Outputs VCC VILMAX RPMIN 0L N211L RP 50V 05V MIN 20 mA 2 20mA RPMIN 16mA Open Collector Drain Outputs RPMAX RPMIN RP 2 9 11E m P III 35Elu DUTPUT 39 z 1200 Open Collector Drain Outputs VC C VIHMIN RPMAX N 1 OH N 211H VCC VILMAX RPMIN 2 UL N 211L RPMAX RPMN P 2 Open Collectorl Drain Outputs Determine RP for the following circuit 5U II1EEImFI RP 39 In 25uaun D H H F H I3939 39339 N 39l E I Ii C lMC II E 59 J I39J39I C C Open Collector Drain Outputs VCC VIHMIN RPMAX N 110H N 21m 5U II1EEImFI 3 Y IIL EITFI UIL 3 EU L L Open Collector Drain Outputs 50V 27V R PMAX 2250A 350uA 5U II1EEImFI 9 1 D pa IIL EmFI UIL 3 EU T Open Collector Drain Outputs 23V RPMAX 3538KQ 650yA 5U I1E m 3 FE Open Collector Drain Outputs VCC VILMAX RPMIN 0L N211L 5U RP I l 25 u IIH E uFI UIH E39 W RPMAX 3 Y9quot Open Collector Drain Outputs 50V 05V 20 mA 320mA R PMIN 5U II1EEImFI RP 39 I l 25 u I I 5EuFI i i UIH 2 Tr39U RPMAX 3 Open Collector Drain Outputs Rpm 2 i 14 mA 5U Ill EBmFI R P InH E39S u I I 5EIuFI i i UIH 2 U 321 40 quotquot39 9V RPMAX 3 Open Collector Drain Outputs R PMAX R PMIN 2 EU RP RP 37 quot quotquotquot 39 l39 RPMIN I RPMAX 353 SKQ iv Open Collector Drain Outputs 3538 321 RP z 2000 Q EU RP 37 quot quotquotquot 39 l39 RPMIN I RPMAX 353 SKQ i613 Summary In this topic we Reviewed several basic logic gates Reviewed positive and negative logic Became familiar with several static and dynamic characteristics of several logic families including o Fanout Noise margins Open collectordrain resistance calculations

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