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# Logic System Design II ECGR 3181

UNCC

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This 98 page Class Notes was uploaded by Sidney Stehr on Sunday October 25, 2015. The Class Notes belongs to ECGR 3181 at University of North Carolina - Charlotte taught by Arindam Mukherjee in Fall. Since its upload, it has received 8 views. For similar materials see /class/228996/ecgr-3181-university-of-north-carolina-charlotte in Electronics and Computer Technology at University of North Carolina - Charlotte.

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Date Created: 10/25/15

Digital Design Chapter 4 Datapath Components Slides to accompany the textbook ngxml Design First Edition by Frank Vahxd John Wiley and Sons Publishers 2007 ttp www ddvahxd com a warm mmmpmma hyJohn mm and SW haw pmmn 2939 mm am M I W 3aMixdidas v uszomavyfquzEq m daam ms mmdg ad Wm Maya maxim mmmprWpush 39 m a s a u tara umumm mm PowavP a may a g m ammg may who pomp m 1 lngylctovgmay ma pmgloitts m min Fowir i wum a mam 17mm mm mm mm to mamm a quotMaurphozmpm4mgmm mmnfngroyalm Aw othnnitsauqitwg uplmipammnhymen Introduction 1 Chapters 2 amp 3 Introduced increasingly complex digital building blocks Gates multiplexers decoders basic registers and controllers Controllers good for systems with control inputsoutputs Control input Single bit orjust a few representing environment event or state eg 1 bit representing button pressed Data input Multiple bits collectively representing single entity eg 7 bits representing temperature in binary Need building blocks for data akargilrirnrri IRTL Datapath storetra nsform data Put datapath components together to form a datapath This chapter introduces numerous datapath components and simple datapaths Next chapter will combine controllers and datapaths into processors 9 5 Copyright 2006 2 Frank Vahxd um snags with ammtmnm dzmtzdwnhasmllnd t hearth Ammatzditems pr Registers Can store data very common in datapaths Basic register of Ch 3 Loaded every cycle Useful for implementing FSM stores encoded state For other uses may want to load only on certain cycles 7 ammo m 51 l at a A l l ll I load a7 t 2 Basie register loads on every clock cycle How extend to only load on certain cycles Digxtal Design Copyright mm 3 pm mu v Register with Parallel Load Add 2x1 mux to front of each ip op Register s load input selects mux input to pass Either existing ip op value or new value to load 0 load Digital Desxgn oapyngm 2on6 Frank Vahld This example will show how registers on clock Notice that all load inputs set to 1 in this example Just f r demonstration purposes Dims Design Capynght 2 Frank Vahld Basic Example Using Registers load cycles Elm Basic Example Using Registers Dims Design Capynght 2mm Frank Vahld seful to compare present item with previous item Use register to store weight Pressing button causes present weight to be 0 ed in reg e a Weight appears Digital Design Capyngm 2mm Frank Vahld Register Example using the Load Input e Weight Sampler Scale has two displays Present we39 Saved weight Weight Sampler v v Present Weight un Saved Weight Recall Chpt 3 example Timer pulse every hour Digital Design Capyngm 2mm Frank Vahld Register Example Temperature History Display Previously used as clock Better design only connects oscillator to clock inputs use registers with load input connect to timer pulse Register Example AboveMirror Display Xhorzhandnotatmw Loaded on clock edge ers 7 Was 8888 32 Wires NOW 8 2 11 WH ngmi Design V Copyright mm 9 pm ma Register Example Computerized Checkerboard Each register OED holds values for one column of i hts 1lights light Microprocessor loads 0 register at a time Occurs fast enough that user sees entire board change at once Digital Design Capynght 2 6 1n pmvtm 17 Register Example Computerized Checkerboard 7 minnmn mm mnnmm mnnmm muuu m 12mg mm mm 2 ciklllllllllllll Digital Deggn Copyright mm 11 pm de Shift Register 4 Regisiev cuniems berm shi rigm Shift right u Move each bit one position right R39eaistsr39cunfms 3 ms ring 1 Shi in 0 to le most bit Q Do four right shi s on 1001 showing value a er each shift A1 001 on39ginal 0 00 00 0 Implementation Connect ip op output to next ip op s input 000 A shun 0000 IZIEHZI Digital Deggn Capynght 2 6 12 Frank de 1 1 Shift Register P shr 0 means retain 1 shi shrin value to shi in To allow register to either shift or retain use 2x1 muxes Note Can easily design shi register that shi s le instead Rotate right Like shif t right but leftmost bit comes from rightmost bit Digital De gn Capynght 2mm Frank de Registey cuntents belure shin right Registey cuntents attey shin right r example 8 Earlie 21 1WIres 39om Better than 32 wires but 11 still a lot want fewer for smaller wire bundles Use shitt registers Wres39121 Computer sends one value at a time one bit per clock cycle Digital Design oapyngm 2mm Frank Vahld Many registers have multiple functions Load shi clear load all Us And retain present value of course Easily designed using muxes nect each mux input to achieve desired function Digital Design oapyngm 2mm Frank Vahld Multifunction Registers Sm W are m Maintain Parallel in n present value ad quotgm sad 7 let s luad Us Multifunction Registers all m 32m 03 02 Digital Design cppyngut o znn Frank Vahld 32m Multifunction Registers with Separate Control Digital Design cppyngut o znn Frank Vahld Inputs l hr spl I pEVatlurl n vialrltaln present value 1 llth la n pllt llgpt l pllt llgpt 75hr has pllullty ENE spl u arallelluad l l l l l arallelluadrld hasprlurlly n arallel load 7 la has pllullty l arallel load 7 id has pllullty inputs Outputs Nate hr sill 1 0P2 l rl n n Malntalnvalue l l Shl l ti o n Silth llgpt 1 El Silth rl ht D t pamllgl luau 51 ld shr shl ld shrshl ld shrshl l l Parallel luad El l Parallel lead 50 ld shr shl ld l 1 Parallel luad 7 Register Operation Table two rows Register operations typically shown using compact version oftable a me operation whether value is 0 or One X expands to Two X5 expand to fourrows inputonlnn I t a I inputs Outputs Note tu snt st sEI Operatiun id snt sni I Opsatiun n n t t n n 1 1 Mantamvaiue t Shit ie x Shin ttgm x Paraiieiiuad Kw Paraiiei iuad nutmeg Capynght 2 6 19 FrankVahtd r Can design register with desired operations using simple fourstep process IABlE 41 routstep prncess tut dnslgnlnn a mtmttunctmtt muster sxrtt mu Iitlll Dmrtntttu L ttuttt lht Hllmhuvi tutumutt tttutt t tt tltt m unmiil tlhiL39 mm 6 ttttmttttttr ttu tutu ttt mm nt cik ii quotI39antlp t tttttt tt tttt tt imq I m mt ttttttt lY tlll mIH Clcilchnanranun ubln tJL tHH 3 them 4 tttmutttttt rut C Aih mt lekINL turnt ttt lhc ttttn wtul ttttux huntcunt V39 39 39I gt 39 WW tttttntttt numttutttttttttttt tt ttttttatttttuttpttmtttymtttgtttntu t mum in ct n uIttm VIIC m mi nlk mlilvllt J Mtqtuuttttti C umutnttlttuttk ittttttttuut t uttttittutttttltuttttt ittt t It tt I tttm ilh ippleiltllA Vihilillt x dull Iih39il chigll ht it in nutmeg Capynght 2 6 zu FrankVahtd at Desired register operations Load shi lelt synchronous clear synchronous set Step 1 Determine mux size 5 operations above plus maintain t present value don t forget this one gt Use 8X1 mux Stgg 2 Create mux ogeration table Step 3 Connect mux inputs Step 4 Map control lines Szcksa eii in am 2 st clr set ld shl clr D E39 E39 D D D u u u i u i u sorclr set ldclr n n i x u u i U l X X l U U Diem Design t X X X n t t cumumum memd Register Design Example gelatinquot Maintain piesent value u Register Design Example inputs tputs set 50 Du eii in am 2 st S clr set 51 clr set ld shl clr D D E39 E39 E39 tr set ld clr D D 1 n 1 n S C I I l X I I l U l X X l U U Diem Design t X X X n t t cumumum memd Evatlun Maintain piesent value snitt le cleai tu all Us 7 Adders Adds two Nbit binary numbers mm 0mm 2bit adder adds two 2bit numbers outputs 3bit result eg01 11 100 1 34 Can design using combinational design process of Ch 2 but doesn t work well for reasonablesize N Why not Digital Design Capynght 2006 23 pm mu v Why Adders Aren t Built Using Standard 4393 Combinational Design Process Truth table too big 2bit adder s truth table shown Has 29 16 rows 8bit adder 2 65536 rows 16bit adder 215 4 billion rows in uls om aElp 1 uls 1 1 b adder Big truth table with numerous 1sIOs yields big logic shows number oftransistors for Nbit adders using stateof the art automated combinational design tool Q Predict number of transistors for 16bit adder A 000 transistors for N5 doubles for each A increase of N So transistors 1000 2N395 Thus for N16 transistors 1000205395 10002048 2048000 Way too many 013ml Design Capynght 0 2006 Frank mm franslstnrs Alternative Method to Design an Adder Imitate Adding by Hand Alternative adder design mimic how people do A t t l l i i i i 1 1 1 A additionbyhand 5 l U W in Mn One column at a l time 1 n1 lEIl lEIlEIl Compute sum add carry to next column Digital Design Copyright mm 25 pm ma v Alternative Method to Design an Adder Imitate 5 Adding by Hand Create 7 component for each column l HalfAdder Halfadder Adds 2 bits generates sum and carr Design using combinational design process 39om h 2 Steg 1 Cagture the function Stgg 2 Convert to eguations c0 ab sa bab sameassaxorb a b a b Stgg 3 Create the circuit Halfadder m s an s 27 FullAdder L Fulladder Adds 3 bits generates Digital De gn Capynght 2mm Frank vim Design using combinational design process 39om h 2 lhaul 4 Stgg 1 Cagture the function SE2 2 Convert to squamous Step 3 Create the circuit in m I I a I Outputs coa bc ab c abc abc co a bcabc ab cabc abc ab abc b bac c cab co c 4 36 ab sa b c a bc ab c abc er b xor c I Digital Deggn m s Capynght mm 28 memd quot CarryRipple Adder Using halfad der and fulladders we can build adder that adds like we would by hand Called a car 39t ryripple adder 4bl adder shown Adds two 4bit numbers generates 5bit output 57bit Output can be considered 47bit Sum plus lrblt carry out Can easily build any size adde a aZalaU b bzblb A bladder 535251 SH b Dlglta De gn Capynght 2mm mid viiiid CarryRipple Adder Using fulladder instead of halfadder for first bit we can i clude a carry in bit in the addition Mll be useful later when we connect smaller adders to form bigger adders a aZalaU b bzblb adder 39 El Dlglta De gn Capynght 2mm mid viiiid CarryRipple Adder s Behavior Assume all inputs mrtrally 0 D111DDD1 answer should be 01000 mum after 2 ns MFA de ay DWI DEW Wrong answer something wrong N0 just need more u39me Capyngm 0 2006 for carry to ripple through the chain of full adders 31 MW 7 CarryRipple Adder s BehaVIor D1110001 answer should be 01000 oumms a ewns 2 FA de avs oumms a ev ns 3 FA de avs 00mm a ev Ens a FA dewavs ngml Desxgn quot 1 quot a quot quot CDWHSM2 5 Correct answer appears a er 4 FA delays 32 Frank Vahld rs Cascading Adders 37363534 b7b6b5b4 33323130 b3b2b1b0 33323130 b3b2b1b0 33323130 b3b2b1b0 3730 b7b0 4bit adder ci 4bit adder ci 8bit adder c 00 53525150 00 53525150 co 5750 lllll l lll 00 57565554 53525150 3 b mm new Copynght 2 l 33 memd v Adder Example DIPSwitchBased Adding Calculator Goal Create calculator that adds two 8bit binary numbers speci ed using DIP switches DIP switch Dualinline package switch move each switch up or down Solution U5e 8bit adder DlP switches Digital Design Copyright mm 34 pmvtm Adder Example DIPSwitchBased Adding Calculator To prevent spurious values 39om appearing at output can place register at output 7 Actually the llght fllckers from Spurlous values would be too fast forhurnarls to detect external devlces Whlch normally aren t humans applles here D P swltches cu Digital Design cdpyngtd 2on6 Frank Vahld Adder Example Compensating Weight Scale Weight scale with compensation amount of 07 To compensate for inaccurate sensor due to physical wear Use 8bit adder Erblt adder 57 SD Welght AW Digital Design Copynght 2 6 to dlsplay 36 pm mm W Shifters Shi ing eg le shitting 0011 yields 0110 useful for Manipulating bits Converting serial data to parallel remember earlier abovemirror display example with shi registers L39 A 39 39 39 20011 L 106 Why Essentlally appending a 0 7 Note that multlplyll lg declrnal numberby l0 accomplisnediust p a pending or i e i byshlitll lg lell 55 becomes 550 Shilt right once same as dividing by 2 3 2 H in l3 l2 ii in m 1 q3 q2 q1 qEI Symb 01 Le shi er shin right shin pm new 51139 Wm 1 and no shi Capynght 2006 shl or no Shl Frank Vania Shifter Example Approximate Celsius to Fahrenheit Converter Convert 8bit Celsius input to 8bit Fahrenheit output F C 95 32 Approximate F 0 2 32 Use le shitt F le shi C 2 0000110012 2 0shi in0 00011000 24 3 WOW 32 8bit adder 00111000 56 F Digital De gn Capynght 2mm Frank vma 38 Shifter Example Temperature Averager Four registers storing a history of temperatures Want to output the average of those temperatures Add then divide by four Same as shi right by 2 Use three adders and right shi by two 0000111 7 001000 8 001100 12 001111 15 T Digital De gn Capynght 2mm Frank de Barrel Shifter A shi er that can shi by any amount 4bit barrel lelt shilt can shilt lelt by 0 1 2 or 3 positions 8bit barrel lelt shilter can shi lelt by 5 6 or7 positions Win a 87 u p m n i5 pointless W youiust lose all the bits Could design using 8X1 muxes an Q lots of wires Too many wires More elegant design Chain three shilters 4 2 and 1 Can achieve any shilt ofO7 by LJ39 1 0 those three shilters ie shilts should m to desired amount 2 lt Digital De gn Net result shift by 5 8 Capynght znn Frank de Comparators er Nbil equality comparator Outputs 1 iftwo Nbit numbers are equal 4bit equality comparator with inputs A a d B asmuste bzalbta0b0 7 mm 1 i or bath a 7 ed aSbS aS bS asz aZ bZ albl al bl aEIbEI aEI bEI Recall thatXNOR outputs l mts two ll iput bltS aret e same q a3 Xnur b3 a2 Xnur b2 at Xnur m a xnurb 0110 0111 33323130 b bzblb 47m equality cumpaiatui Digital De gn Capynght 2mm Frank de Magnitude Comparator Nbit magnitude comparator Indicates whether AgtB AB or A1011 B1001 AltB for its two Nbit inputs A and B 1011 1001 Equal How design Consider how compare 1011 1001 Equal by hand First compare a3 and b3 If equal compare a2 and b2 And so on 1011 1001 Unequal Stop If comparison n tequal so A gt B whichever s bit is 1 is greater If never see unequal bit pair AB Digital De gn Capynght 2mm Frank him 42 Magnitude Comparator By hand example leads to idea for des39g Start at lelt compare each bit pair pass results to the right Each bit pair called a stage Each stage has 3 inputs indicating results of higher stage passes results to lower stage 3 91 3525150 b3b2 lbO A918 Digital Design 39 l 5 Capynght 2 6 ankVahtd Magnitude Comparator Each stage out gt ngt ineq a t b o AgtB s 5t5ge iiiiiigii i e this stage ai ahg b0 outlt inltineq a t b AltB so stage iiiiiigiii e h this stage ao ahg bi out eq In B so far if5lre5dy determined in higher stage 5l id in this stage 5b too 4 L L 39 Justa ew Digital De gn Capynght 2 6 ankVahtd Magnitude Comparator How does it 101171001 work 1 n n a ha 32 n2 a1 m an nu E Izq1 musesthxs 12 stage 20 compm 11 13131111 Desxgn oapyngm 2on6 Frank Vahld Magnitude Comparator 1 1 n n 1 1 1011 10017 a3 b3 32 m Q an bu Final answer appears on the Fa right Takes time for answe npple aw r to from le to right Thus called arryripple stylequot a er the carryripple adder Even though there s no a 11 Drgml Desxgn Copyright mm 45 pm de Magnitude Comparator Example er Minimum of Two Numbers Design a combinational component that computes the minimum of two 8bit numbers Solution Use 8bit magnitude comparator and 8bit 2X1 mux lfAltB passAthrough mux Else pass I 01111111 11000000l MlN A is lit l 01111111 Digital Desxgn Capynght mm 47 pm ma v Counters Nbit upcounter Nbit register that can increment add 1 to its own value on each clock cycle 0000 0001 0010 0011 1110 1111 0000 Note how count rolls overquot from 1111 000 Terminal last count tc equals1 1 g I Internal design Register incrementer and Ninput AND gate to detect terminal count Digital Desxgn Capynght mm 48 pmvtm Incrementer Counter design used incrementer lncrementerdesign added pe um three bits carries 01 1 Digital Design a Capynght 2mm Frank Vahld Could use carryripple adder with B input set to 00001 But when adding 00001 to another number the leading 0 s obviously don t need to be considered sojust two bits being r col n Use halfadders adds two bits rather than fulladders adds 53 52 al 50 1 CO 53525150 Digital Design Capynght 2mm Frank Vahld 49 739 Incrementer L inputs Outputs can build faster incrementer 33 32 31 an m 53 2 51 5D using combinational logic u u u u u u u u t El El I 1 El El El l U design process U U 1 U U U U 1 1 Capture truth table U U i i n n t n n El 1 El El El El 1 El 1 Derive equation for each output D 1 D 1 D D 1 1 D c0 a3a2 1a0 n t t n n n t t t El 1 l 1 El 1 El El El i n n n n t n n i s0 a0 t n n i n t n i n Results in small and fast circuit 1 E 1 239 E 1 239 SI 21 Note works for small N larger t t n n n t t n i N leads to exponential growth 1 l U l U i i i n l l 1 El U l l l i like for N bit adder 1 1 1 1 1 D D D D Counter Example Mode in AboveMirror Display Recall abovemirror display example from Chapter 2 As umed component that incremented Xy input each time button pressed 00 01 10 11 0 01 10 11 00 Can use 2bit upcounter Assumes mode1 forjust one cl ck cycle during each button press Re ter3 0 call Button press synchronizer example from Chap 3 3 4 3a 32 8 Eu 53 35 mg in W lldesrgn IS Digital Deggn Capynght 2 6 51 pm de v Counter Example 1 Hz Pulse Generator Using 256 Hz Oscillator a Suppose have 256 Hz oscillator but want 1 Hz pulse 1 Hz is 1 pulse per second useful for keeping time 1 DESlgn USlng 8bit up gt counter use tc output as gt to c pu se osc 256 H2 3 Counts 39om 0 to 255 256 P unused counts so pulses to every 1 HZ 256 cycles Digital Deggn Copyright mm 52 pmvma e DownCounter a 4bit downcounter 1111 1110 1101 1100 0011 0010 0001 0000 Terminal count is 0000 Use NOR gate to detect Need decrementer 1 design like designed incrementer Digital De gn oapyngm 2on6 Frank de Arblt downrcounter 47bit register UpDownCounter a Can count either up or down lncl d both 47bit updown counter u es Incrementer and decrementer c m m 2 5 1 S 6 Likewise dir selects appropriat terminal count valu Digital De gn oapyngm 2on6 Frank de e e Counter Example Light Sequencer Illuminate 8 lights from right to left one at a time one per second Use 3bit upcounter to counter from 0 to 7 Use 3x8 decoder to illuminate appropriate light mt 37bit uprcou nter Note Used 3bit counter with 3x8 decoder NOT an 8bit counter why not Digital Design Capynght 2mm Frank Vahld Counter with Parallel Load Upcounter that can be loaded with external value Load the internal register when loading externa value or when counting Digital Design Capynght 2mm Frank Vahld 56 Counter with Parallel Load Useful to create pulses at specific multiples of clock Not just at Nbit counter s natural wraparound of 2N 9 Example Pulse every 9 clock cycles Use 4 bit downcounter with parallel load Set parallel load input to 8 1000 Use terminal count to reload When count reaches 0 next cycle loads 8 Why load 8 and not 9 Because 0 is included in count sequence 8 7 6 5 4 3 2 1 0 9 Scounts Digital Design Copyright mm 57 pm ma Counter Example L New Year s Eve Countdown Display Chapter 2 example previously used microprocessor to counter from 59 down to 0 in binary Can use 8bit or 7 or 6bit downcounter instead initially loaded with 59 reset fire orks gt rbt d5 quot plantings Capynght 2006 58 memd Counter Example 4 1 Hz Pulse Generator from 60 Hz Clock US electricity standard uses 60 Hz signal Device may convert that to 1 Hz signal to count seconds Use 6bit upcounter Can count from O to 63 Create simple logic to detect 59 for 60 counts Use to clear the counter back to 0 orto load 0 Digital Design Copyright 2006 t Frank Vahid V Timer A type of counter used to measure time If we knowthe counter s clock frequency and the count we know the time that s been counted Example Compute car s speed using two sensors First sensor a clears and starts timer Second sensor b stops timer Assuming clock of 1kHz timer output represents time to travel between sensors Knowing the distance we can compute spee quota gt Snow 5 wvr39b Me SUlEV a cnt0 compute time and output I Digital Design Copyright 2006 Frank Vahid speed Multiplier Array Sule Can build multiplier that mimics multiplication by hand Notice that multiplying multiplicand by 1 is same as ANDing with 1 0110 the top number is called the nmliphcmrd 0011 the bottom number is called the nmhipier each row below is called a partial product 01 10 because the rightmost bit of the multiplier is 1 and 0 1 1 01201 1 0 0110 because the second bit of the multiplier is 1 and 0110120110l 0000 because the third bit of the multiplier is 0 and 01 10100000 0000 because the leftmost bit of the multiplier is 0 and 0110020000 00010010 the product is the sum of all the partial products 18 which is 6quot Digital Design Copyright 2005 Frank Vahid lt 7 Multiplier Array Style Generalized representation of multiplication by hand a3 a2 a1 a0 x b3 b2 b1 b0 b0a3 b0a2 b0a1 bOaO ppl b1a3 blaZ blal Mat 0 pp b2a3 b2a2 b2a1 72610 0 O pp3 b3a3 b3a2 b3a1 b3a0 0 0 0 pp4gt p7 p6 p5 p4 p3 p2 p1 p0 Digital Design Copyright 2005 Frank Vahid I Multiplier Array Style AND gates Multiplier design array of 1 3 bid Dial bla b2u3 DZHZ qul D353 DSEJZ b3al b35111 p5 p6 Block 5ymbo DtgtLBIDestgn Copyn 2006 p7p0 63 FrankVahtd pf I 48 5 Can build subtractor as we built carryripple adder Mimic subtraction by hand Compute borrows from columns on left Use fullsubtractor component 39 i borrow by column on right we borrow 39om column on lelt 15toolumn 2ndoolumn 3rdoolumn 4thoolumn o 1 10 1 1010 1010101044110 010 0111 0111 01110111 1 1 1 o 1 1 o o 1 1 a3a2a1ao b3b2b1b0 4bit5ubtractor wi n we 53525150 we 53 52 51 50 b 0 Digital Design Copyrighrozoos 64 FrankVahtd quot 7 I Subtractor Example DIPSwitch Based AddingSubtracting Calculator Extend earlier DlPswitches calculator example SNltCh findicates whether want to add f0 or subtract f1 Use subtractor and 2x1 mux 8bit adder 8bit Subtractor 8bit register 09000000 LED Dlgtal Desxgu Copyright 2006 55 Frank Vahld Subtractor Example Color Space Converter RGB to CMYK Color l Often represented as weights l ofthree colors red green and blue GB v Perhaps 8 bits each so specific color is 24 bits White R11111111 G11111111 B11111111 Black Roooooooo G00000000 Boooooooo betweeneg R00111111 39 Gooooooooy 300001111 Printers use opposlte color scheme would be a reddish Purple Because inks absorb light Good for computer monltors Use complementary colors of RGB WhICh mIX red green and blue ann absorbs red reflects green lights to form all colors and blue Magenta absorbs green and iellow absorbs blue Dlgtal Desxgu Copyright 2006 66 Frank Vahld I 33 Subtractor Example er Color Space Converter RGB to CMYK Printers must quickly convert RGB to CMY C255R M255G Y255B Use subtractors as shown Digital Design Capynghl 2on6 Frank Vahld 39L Color Space Converter RGB Try to save colored inks Expensive Imperfect mixing C M Y doesn t yield goodlooking black Solution Factor out the black or gray from the color print that part using black ink eg CMY of 250200200 200200200 5000 200200 200 is a dark gray use C In Digital Design Capynghl 2on6 Frank Vahld Subtractor Example39 68 Subtractor Example er Color Space Converter RGB to CMYK Call black part K I Compute minimum ofC M Y values Use MIN component designed earlier using comparator and mux to Output resulting K value and subtract K value 39om C nd Y values Ex Input of 250200200 yields output of 5000200 Digital Design Capyngm 2006 Frank Vahld Representing Negative Numbers Two s L Complement Negative numbers common How represent in binary Signedmagnitude Use le most bit for sign bit So 5 would be 1101 using four bits 10000101 using eight bits Better way Two s complement Big advantage Allows us to perform subtraction using addition Thus only need adder component no need for separate subtractor component Digital Design Copyright 0 2006 70 pmvtm Ten s Complement F l gtB 1 gt8 Before Introducing two 5 complement lets gt7 consrder ten 5 complement 4 gt6 But be aware that computers DO NOT USE TEN S COMPLEMENT Introduced forintuition only 5 5 E gt4 Complements for each base ten number shown to right Complement is the number that when added 7 gt3 results in 10 3 gt2 Digital Design Copyright mm 71 pm ma a Ten 5 Complement L Nice feature often s complement 39 quot 39 number 39 39 39 answer exactly 10 too much So just drop the 1 results in subtracting using addition only mmplements t m 39 E El 7 u I W 2 3 13 X3 3 Mada 3 Adding the mmplement results in an awevar many lEItuu mum rdmpplng thetensculumn glvEs theright ansver u in Digital Design Copyright mm 72 pmvtm e Two s Complement is Easy to Compute 9 Just Invert Bits and Add 1 Hold on Sure only is 6 by subtracting 1046 in the rst pl True but in binary it turns out that the two s complement can be computed easi y Two s complement of011 is 101 because 011 101 is 1000 Could compute complement of011 as 1000 011 101 Easier method Just invert all the bits and add 1 The complement of 011 is 1001 101 it works Q What is the two s complement ofOlOl A 101011011 check 0101101110000 A 110011101 AL complement in the rst place eg we only know that the complement of4 ace Q What is the two s complement ofOOl 1 Digital Deggn Copyright mm 73 pm mm v Two s Complement Subtractor Built with an Adder Using two s complement A B A B A two s complement of B A invertbitsB 1 So build subtractor using adder by inverting B s bits and setting carry in to 1 Digital Deggn Copyright mm 74 memd e AdderSubtractor a Addersubtractor control input determines whether add or subtract Can use 2x1 mux sub input passes either B or inverted B Alternatively can use XOR gates if sub input is O B s bits pass through if sub input is 1 XORs invert B s bits adder s B inputs 393 Digital Design Copyright 2005 75 Frank Vahid lt AdderSubtractor Example Calculator Previous calculator DPswitches used se arate 1 p OHHEEIHH HEEEUEQH adder and 8 8 subtractor A B 0 s addersubtractor a clk gt complement 8 W numbers 00 LEDs m E A E cl I A E wi I m adder m sumamr Bhilvegi er Digital Design 8 Copyrightmoos oooouoo LED 75 Frank Vahid quot Overflow 9 Sometimes result can t be represented with given number of bits Either too large magnitude of positive or negative eg 4bit two s complement addition of01110001 718 But 4 bit two s complement can t represent number gt7 01110001 1000 WRONG answer 1000intwo s complementisB not 8 Addersubtractor should indicate when overflow has occurred so result can be discarded Digml Deggn capynghi o mo 77 pm de Detecting Overflow Method 1 Assuming 4bit two s complement numbers can detect over ow by detecting when the two numbers sign bits are the same but are different from the results sign b39t lfthe two numbers sign bits are different over ow is impossible nega ve Simple circuit over ow a3 b3 s3 a3b3s3 Include over ow output bit on addersubtractor Sign bits 111 111 o o o o 01 o o o 111 o o o 111 j overflow overflow no overflow a b c D D lft umbers srgnonehavemesamevaiuewmo on egg Cammm differs from the results Sign bit overflow has occurred memm 111 Detecting Overflow Method 2 Even simpler method Detect difference between carryin to sign bit and carryout 39om si n bi Yields simpler circuit over ow c3 Xor c4 1 l l 0 0 0 0 0 0 l l l l l l l l 0 0 0 0 0 0 l l 0 0 0 0 l l l 0 l 0 0 0 l J l l l overflow overflow no overflow a b C lfthe carry into the Sign bit column differs rrorn the carry out or that column overflow has occurred Digital Deggn Copyright c mm 79 pm de v ArithmeticLogic Un t39 ALU ALU Component that can perform any of various arithmetic add subtract increment mm etc and logic AND OR etc operations based on control inputs Motivation Suppose want multi function calculator that not only adds and subtracts but also increments ANDs ORs X etc Digital Deggn Copyright c znn an pmvma i39 ll 39lltlml Multifunction Calculator without an ALU 4 Can build multifunction calculator using separate components for each operation and muxes But too many wires and wasted power computing all those operations when at any time you only use DlF39 switches Erbll E l Erblt regiser Digital Design Copyright 2005 Frank Vahid mum 81 7 ALU More efficient design uses ALU ALU design notjust separate components multiplexed same problem as previous slide Instead ALU design uses single adder plus logic in front of adder s A and B inputs Logic in front is called an arithmeticlogic extender Extender modifies the A and B inputs such that desired operation will appear at output of the ad Al Bl ia7 ib7 iaG ib6 b is t a Digital Design Copyright 2006 Frank Vahid ahext nnexl iaB lbs 30 mo cm b xy 0 xyz001 Want SA B pass a to ia b to ib and set cin1 Xyz010 Want SA1 pass a to ia set ib0 and set cin1 xyz01 1 Want SA pass a to ia set ib0 and set cin0 xyz1000 Want SA AND B set iaa b b0 and cin0 others likewise ove create logic for iaxyzab and ibxyzab for each abext and create logic for cinxyz to complete design of the ALextender compo n ent Digital Design Capynght 2 6 83 mt de ALU Example Multifunction Calculator Design using ALU is elegant and efficient No mass of wires No big waste of power Erbitvegistev Digital Design Copyright mm 84 pmvtm f Register Files MXN register file component provides efficient access to M N bitwide registers Ifwe have many registers but only need access one or two at a time a register le is more ef cient EX Abovemirror display earlier example but this time having 16 32bit registers Too many wires and big mux is too slow Digital Design Capynght 2mm Frank Vahld Register File 4 Instead want component that has one data input and one data output and allows us to specify which internal register to write and which to read R aim in m d a Wjddr a ll 5 n w m s4 m w a u dzazrmlsiarme like no connection Digital Design Capynght 2mm Frank Vahld Register File Timing Diagram Can write one register and read one register each clock cycle May be same register Digital Destgn oapyngm 2on6 Frank Vahld r RegisterFile Example AboveMirror Display 16 32bit registers that can be written by car s computer and displayed Use 16x32 register le 0 32 Wm Simple elegant design 35 W A R t E WWiadm egisler le t es ES W72quot comp eXIty in erna y vegggm time simpl Digital Destgn oapyngm 2on6 Frank Vahld internal design is e 88 Chapter Summary Also known as registertransferlevel RTL components Components introduced Registers Shilters Subtractors ArithmeticLogic Units Register Files we ll combine knowledge of combinational logic des39gn sequential logic design and datapa components to build digital circuits that can perform general and powerful computations Digital Deggn oapyngm 2mm Frank de Need datapath components to store and operate on multibit data Digital Design Chapter 2 Combinational Logic Design Slides to accompany the textbook Digital Design First Edition byka 39 i y d VahldJohnWle an Sons Publishers2007 http ddvahid com Copyn39glit 2007 Fi ar ikiVa bid Instructor ofcouvx ngvlvig Vahnik DigXHI D lng mxtboakhubltghizd by 7th1 Wllizy MdSOYIShwgt pemtssmnm madtjl mduserhizsiz td v customiziy muvsrzlyizianzd amvma 12 1022p yum ih dlA gdi gd 1h 41 dfw toy mi acesapiegoiiygajwabsm PoweiPaImk omit gab i gr diva iy to by qmizy gig p axe m 21 Introduction Detector Detector Digital System Digital circuit Let s learn to design digital circuits 1 1 We start With a Simple form of Circuit a C Tb39quotquot quota39F bgt digital circuit Combinational circuit A digital circuit whose outputs depend solely on a Se usmial 7 the present combination of the circuit inputs ogt q 39gti bgt digital circuit values Digital Design Copyright 2006 2 rankde Nuie Slides with amrrauun are de ated mm a mu red 2 nmr the amrraled aws Switches binary digital circuits Electrical terminology v oltage Difference in electric potential between two poln s e Analogous to Water press Current Flow of charged particles 7 Analogous to Water low Resistance Tendency current ow a Analogous V R OhmsL w Digital Deogii Capynght 2on5 Frank Voliio Electronic switches are the basis of ure ofwire to resist to Water plpe dlarneter a 3 A switch has three parts Source input and output Current lnput to nput yoltag curren The amaz 30s e to acuum tubes 1950s Discrete transistor Wants to ow rrorn source output that controls Whetherthat an ow ing shrinking switch Relays Switches eorrtrol rrrpu souree 1960s Integrated circuits le lnltlallylust a few transrstors on K Then tens nunoreos thousands Digital Deogii Capynght 2on5 Frank Voliio o tr relay vacuum tube quarter tn see the relatlye size A t lsclete arrsrstor Moore s Law f IC capacity doubling about every 18 months for several deca own as Moore s Lawquot alter Gordon Moore cofounder of Intel 39 Predicted in 1965 predicted that components per lC would double roughly eyery year or 50 Book cover depicts related phenomen r a particular hurhber onrahsrstore 5h ll lkS by halfevery l8 rh l h a he lC Wmuch shrhhhg occurs hiust about 1 years 7 Enables lnErE incredibly tiny Today s le hold billions of transistors The rst Pehhurh proce550rearly 19905 heeded only 3 million Digital Design oapyngiii 2on6 Frank viiiu dibly powerful computation in devices An Imetpennm pmce c o I having mxllxon oftmnnxtor CMOS transistor Basic switch in modern le quotMOS gale I altvadselemunshem lopamags a silicon e not quite a conductor or insulator Szmim r mama Digital Design oapyngiii 2on6 Frank viiiu The CMOS Transistor i conducts 4 does hm conduct hi duesnut conduct l conducts Boolean Logic Gates Building Blocks for Digital Circuits Because kaches are Hard to Work With TraviSisluls me Q 0000 haul in work wil These blocks fr III enahle greater desrgns rm logic galus um we ll 5min inlmdurf enable greater designs The light building blocks Logic gatesquot are better digital circuit building blocks than switches transistors WW7 Digital De gn capyngm 2on6 Frank de Boolean Algebra and its Relation to Digital Circuits To understand the benefits of logic gates vs switches we should first understand Boolean algebra Traditional algebra Variable represent real numbers Operators operate on variables return real numbers Boolean Algebra Variables represent 0 or 1 only Operators return 0 or 1 only Basic operators a NDb returns 1 only when both a1 and b1 5 OR b returns 1 ifeither or both a1 or b1 NOT NOTa returns the opposite ofa 1 ifa0 Oif a1 1M 1 u Digital De gn capyngm 2on6 Frank de OR Boolean Algebra and its Relation to Digital Circuits Developed mid1800 s by George Boole to formalize human thought Ex I ll go to lunch if Mary goes OR John goes AND Sally does not goquot Let F represent my goll lg to luncn 1 means l 90 o l don t go leewlse m for Mary goll lg l for John and s for Sally Then F m oRjAND NDTs Nice features Formally eyaluate e m1llol 51 quotgtFl on oAND NOTl 1ANDo o Formally transform 7 F m and NOTS one and NOTS Looks dlfferent but same runaan We ll showtransformatlon technluues soon Digital Deggn Copyright o mm 9 pm de v Evaluating Boolean Equations Evaluate the Boolean equation F a AND b OR c AND d for the given values of variables a b c and d Q1 a1 b1 c1 d0 Answer F1 AND 1 OR 1 AND 0 1 OR0 1 Q2 a0 b1 00 d1 Answer F 0 AND 1 OR 0 AND 1 0 OR o o Q3 a1 b1 c1 d AnswerF1 AND 1 0R1 AND 11 OR1 1 Digital Deggn Capynght 2 6 in Franklin Converting to Boolean Equations Convert the following English statements to a Boolean equation Q1ais1andbis1 Answer F aAND b Q2 either of a or b is 1 Answer F a OR b Q3 both a and b are not 0 Answer 7 a Optionl F NOTaAND NOTb r bOpthl l 2 F 5 OR b Q4ais1andbisO Answer F a AND NOTb Digxtal Deggn Copyright mm 11 pm de Converting to Boolean Equations Q1 A fire sprinkler system should spray water if high heat is sensed and the system is set to enabled Answer Let Boolean variable h represent high heat is sensedquot e represent enabled and F represent spraying waterquot Then an equation is Q2 A car alarm should sound if the alarm is enabled and either the car is shaken or the door is opened Answer Let a represent alarm is enabledquot 5 represent car is shakenquot d represent door is openedquot and F represent alarm soundsquot Then an equation is F a AND 5 OR d a Alternatively assuming that our door sensor d represents door is closedquot instead of open meanin d1 when the door is closed 0 when open we obtain the following equation F a AND 5 OR NOTd musings Capynght 2 6 Fmvma F hANDe Relating Boolean Algebra to Digital Design Boole39s inlenl formallze n uman thought midst 8005 SWltcheS For ieiepnone i930s swllchlng and olnei electronic uses Showed appllcallon ofBooean algebra to deslgn ofswlcn based Clmulls snannon i938 Ynnllnr mum x Digital deSlgl l D Implement Boolean operators using transistors i m Tnese omwo Call those implementations logic gates Wiemeniaims 59 meme 5 us 70quot b do math we ll snow why and snow better ones later powerful conce t Digital Deggn Copyright 2006 pm mm NOTORAND Logic Gate Timing Diagrams Digital De gn ospyngm 2005 Frank vma Building Circuits Using Gates Detector a Detector Digital 39 h Recall Chapter 1 motionindark example Turn on lamp F1 when motion sensed a1 and no light b0 F a AND NOTb Build using logic gates AND and NOT as shown We just built our first digital circuit Digital Design Copyright 2005 Frank Vahid Example Converting a Boolean Equation to a Circuit of Logic Gates Q Convert the following equation to logic gates F a AND NOT b OR NOTc 53 a a b F c b Digital Design Copyright 2005 Frank Vahid Example Seat Belt Warning Light System Design circuit for warning light Sensors s1 seat belt fastened k1 key inserted 1 person in seat Capture Boolean equation person in seat antilnsseeattezelt not W p AND NOTS AND k Convert equation to circuit o ice k BeltWam Boolean algebra enables easy quot capture as equation and conversion 1 A to circuit How design With Switches or course logic gates are built from s switches butwe think at level ofloglc gates not SW 0 es Digital Deggn Copyright e mm 17 pm de v Some Circuit Drawing Conventions no yes x F y no yes nutuk Digital Deggn Copynght 2 6 18 memd fr Boolean Algebra By de ning logic gates based on Boolean algebra we can use algebraic methods to manipulate circuits So let s learn some Boolean algebraic methods Start with notation Writing a AND b a OR b and NOTa is cumbersome Use symbols a t b a b and a in fact a t b can be just ab Original w p AND NOTaAND llt 0 New wps lltt L e Spoken as Wequals p and s prime and K art 7 or eveniust Wequals p s prime K art 7 s known as cumplementufs Wnile svmbols come from regularalgebra don39lsav times or plus a el an algebra precedence nignestpreeedeneenrst Symhnl Name Parantheses Evaluate expressmnsnesled m parmtheses rst AND Evaluate 39um 123 in ngpr D ital D29 11 cfwngmggmm OR Evaluate 39umle re right 19 ankValud Boolean Algebra Operator Precendence Evaluate the following Boolean equations assuming a1 b1 c0 d1 Answer nas precedence overt so we evaluate tne equation as F 0 0 i o i 02 F ab c n0 notation for t 03 F ab Answer we first evaluate o because NOT nas precedence overAND resulting in Fl i l0l00 Q4 F ac Answer we first evaluate wnat is inside tne parentheses tnen we NOTthe result vielding my 0 o i QSFab cd Answer lnsidelelt parentneses i i precedence overt vielding tne ores giving 0 i 0 0 Digital Depgn Capynght o 2on6 zu pm me 01 0i Nevtrnas i The NOT nas precedence over Boolean Algebra Terminology Example equation Fabc a bc abc ab c Variable Represents a value 0 or 1 Three variables a b and c Litera Appearance of a variable in true or complemented form Nine literals a b c a b c a b and c Product term Product ofliterals Four product terms a bc abc ab c Sumofproducts Equation written as OR ofproduct terms only Above equation is in sumof products form F abc dquot is not Digital Deggn Cupynght 2 6 21 pm Vmu r Boolean Algebra Properties Commutative Example uses of the properties 7 a p p a 7 a s b b s a Show abc equivalent to c ba Distributive 7 Use commiutati vepropertv 7 to a o c a b emote e e a bcabac the 5b 0ab lta0 Showabcab 39 a W W 7 Use first distributive property Associative abc abc abcc abcab0 e Complementpro rt a b0a b 0 Repiae c byl some om Identity 7 ldentity propert t a i e i ab 7 Ma 5 how x e ivalen toxz Complement 7 Second distributive propertv ai 1 R i 2 gtlt z o w ytm 0 To prove just evaluate all possibilities W Digital Deggn replace pm by gtltz Cupynght o zuuo 22 pm Vmu i a a 3 E u S u a Example that Applies Boolean Algebra Properties Want automatic door opener circuit eg for grocery store Found inexpensive chip that computes Output f1 opens door Inputs f c hp c hp c h p Can we use it 39 lsitth e sarne as f c Use Boolean algebra pers n detected pm i sWitch forcing hoio open ci key forcing cioseo Want open door when 39 l1l arid 00 or ho and pi and co Equation f hc h pc f c hp c hp c h p f on p p c h p by the distnbutwe property c hi c h p by the conplementpropa39ty f c h c h p by the identity property f hc h pc by the commutative property Samel Dene new Capynght 2 6 23 mama Nuiieiemems Aircraft lavatory sign example 1 Behavior i 0 0 Three lavatunes each vnth iightin l a 39 sensufa b c euuais i if light i ldempotent Law dml m e Opposite of a a 3 tight Available Sign 5 if iAva iabiei when S anylavatury available W i i a t a a e a o c Equation and circuit 7 SO 8 a bi w lnvolution Law s a b c i t bi W i i i a c a 3 Transforrn by DeMergan s DeMorgan s Law 5b a fb f W LEW H e organs avv siearbruby a b 7 a by my involution Law ab a b New equation and circuit 7 Makes ll itultlve sense Very useful Occupied if aii door To prove just are lucked evaluate all a a Cm possibilities b b S c Digiiuoeagn oapynghi o zuuo 24 FrankVahtd Boolean Algebra Additional Properties Alternative instead of Re resentations of Boolean Functions English1 F uutputsl when a lSU and b lsUquhEn a lSU and b lsl EnglishZ F outputs i when a isDvegavdlessufb svalue a Equminn1 Ham EqualinnZ Ftah b Circuil1 A function can be represented in different ways Abov s eh representations ofthe same functions Fab using four different methods English Equation Circuit and Truth Table Digital Design Copyright mm 25 pm ma v Truth Table Representation of Boolean Functions Define value of F for S S S S 3 each possible SI 3 SI combination of input 1 l u l i values a l E 2 input function 4rows 1 1 239 3input function 8 rows 3 4 inputfunction 16 rows 3 b E F Q Use truth table to E E 2 define function Fabc 3 1 2 that is 1 when abc is 5 or t u u n greaterin binary l g l l l l I Digital Design Copyright mm 25 pmvtm Converting among Representations Can convert from any representation to any other Common conversions Equation to circuit we did this earlier Truth table to equation which we can ircuit converttoc Easthust OR each rnput terrn that should output t n Equation totruthtable a b E Easthustevaluate equatrorrforeach D D D n rrrputcornbrrratrorrrovv D D r n Creatrngrnterrnedrate corurnnsherps u t u o u t t u Fa a b t n n n inputs Output 1 U l 1 abc t t u t abc t t t t b b a F u 1 U 1 F ab c abc abc t n t n a D t DrgxtalDe gn oapyngnt to zone B 27 pmvtna v Standard Representation Truth Table How can we determine if two functions are the same Recall automatic door example f c hp t c hp t CH T 0WD D 0WD r c htt c h p Same as r Used argeorarc rnethods l 0 9 But rfvve failed does that prove What rfwe stopped here 7 t uar No thcrwpcr Solution Convert to truth tables o fa39given Q Determine ifFaba is s m function functron as Fa b a bab by converting each to truth table rst standard representatron W for grverrfurrctrorr only one version Rab wt in standard form exrs s Digital Deagn oapyngnt to zone Frank vma Canonical Form Sum of Minterms Truth tables too big for numerous inputs Use standard form of equation instead Known as canonical form Regular algebra group terms ofpolynomial by power ax1bxc 3x14x2x131gt 5x14x4 Boolean algebra create sum of minterms Minterm product term with every function literal appearing exactly once in true or complemente form Just multiplyout equation until sum ofproduct terms Then expand each term until all terms are minterms Q Determine if Fababa is same function as Faba b a bab by converting rst equation to canonical form second already in canonical form F aba already Sum ofproducts ab a bb expanding term D s DEW F ab at a b SAME W Same three terms as other equation Capynght 2 6 ankValud v MultipleOutput Circuits Many circuits have more than one output Can give each a separate circuit or can share gates Ex Fabc Gabbc b 3 Option 1 Separate circuits Option 2 Shared gates Digital Deagn Copyright mm in Maximum 7quot E YAELEZ o Multiple Output Example BCD to 7Segment Converter PUG I l LEI lJLI39ILLI L 030 l a w x y z w x yz w x yz Des Digital gn Copyngm 2006 Frank Vahld b W x y z w x y z W x yz w x yz w xy z w xyz vvx y z vvx y z w xy z w xyz w xyz vvx y z vvx y z Step 1 Step 2 Step 3 Combinational Logic Design Process Step Description Capture the Convert to desired Implement For each output create a circuit corresponding s a gate to the outputs equation Sharing gates among based multiple outputs is OK optionally circuit Des Digital gn Copyngm 2006 Frank Vahld Create a truth table or equations whichever is ctIon most natural for the given problem to describe the desired behavior of the combinational logic This step is only necessary if you captured the equations function using a truth table instead of equations Create an equation for each output by ORing all the minterms for that output Simplify the equations if 9 11110000 Step 1 Capture the function Truth table or equation Step 2 Convert to equation already done Step 3 Implement as a gatebased circuit Digital De gn oapyngm 2006 Frank de Example Three 15 Detector Problem Detect three consecutive 15 in 8 bit input abcdefgh 00011 101 1 10101011 0 1 th table too big 218256 row a Equatan create termsrur each possible case or three consecutive 1s Problem Output in binary on two outputs yz the number of 15 on three inputs 0109 01 101910 0009 00 Step 1 Capture the function r Truth table or equation 1 i 7 Truth table l5 straightforward I Step 2 Convert to equation y abc abc abc abc E Example Number of 15 Count Illpuh mi I r qum v 39 Z abc a bc abc abc g E Step 3 Implement as a gate E E 1 based circuit E c E a c b a Digital Dengn E oapyngm 2006 Frank de L NAND F 1 1 1 n More Gates NOR XOR XNOR n n NAND Opposite ofAND NOT ANDquot NAND same as AND with power amp o NOR Opposite of OR NOT ORquot XOR Exactly1 input is 1 for 2input XOR For more inputs odd number f 1s ground switche 39 Nhy HMOS conducts 05 Well but not 15 reasons beyond our scopequot s XNOR Opposite ofXOR NOT XORquot Likewise NOR same as OR with Digital Deagn Cammmm So NAN DNOR more common 35 memd v powerground switched AND in CMOS NAND with NOT OR in CMOS NOR with NOT More Gates Example Uses Aircraft lavatory sign I a I s examp e g S abc Detecting all Os 39H an Use NOR bEI Detecting equality al W Use XNOR Detecting odd of is 3 Use XOR Useful for generating parity bit common for detecting errors Digital Deggn Copyright e mm 35 pm 1mm 7 Completeness of NAND F Any Boolean function can be implemented using just NAND gates Why Need AND OR and NOT NOT 1input NAND or 2input NAND with inputs tied together AND NAND followed by NOT OR NAND preceded by NOTs D Likewise for NOR 9 Digital Design Copyright to 2mm 37 pm mu v Number of Possible Boolean Functions How many possible functions of 2 variables 22 rows in truth table 2 choices for each 212 2 16 possible functions N variables N F U ml 2 choices ml 2mm U ml 2 choices U ml 2 choices a n n l l 2015 2 rows possible functions N 22 gt possible functions abll fllZC39lfA f lEWfEfolUflllefl flAllS e 3 2 lt2 XNZZ lt N N M Z Digital Design Copyright to 2mm 38 pmvtm u logic building block in additio logic gates Converts input binary numbe one high output 2input decoder four possible input binary numbers possible input binary number Internal design D gate for each output to detect input combination Decoder with enable e Outputs all 0 if e0 Regular behavior if e1 ninput decoder 2quot outputs Digital Digigii Copyright o 2on6 Frank vim Decoders and Muxes Decoder Popular com binational outputs one for each nto rto L New Year s Eve Countdown Display Microprocessor counts from 59 down to 0 in binary on 6bit output Want illuminate one of 60 lights for each binary number Use 2364 decoder 4 outputs unused Digital Digigii Copyright o 2on6 Frank vim Decoder Example 210 21 0 Happy lll U New Veal Multiplexor MuX 7 Mux Another popular combinational building block Routes one of its N data inputs to its one output based on binary uts value of select Inp 4 input mux 9 needs 2 select inputs to indicate which input to route through 8 input mux 9 3 select inputs N inputs 9 logZN selects Like a railyard switch D Digital De gn Capynght 2mm Frank de MuX Internal Design 1 i0i0 d 51 s Digital De gn Capynght 2mm Frank him no 0i0i0 42 Mux Example 2 City mayor can set four switches up or down representing hishervote on each of four proposals numbered 0 1 2 3 City manager can display any such vote on large greenred LED light by setting two switches to represent binary 0 1 or Use 4x1 mux Mayuy s witches Digital Design Capynght mm 43 pm mu Muxes Commonly Together Nbit Mux Simplilymg nutatiun Ex Two 4bit inputs A a3 a2 a1 a0 and B b3 b2 b1 b0 4 bit 2X1 mux just four 2X1 muxes sharing a select line can select between A or B Digital Design Capynght mm 44 memd 39 Nbit Mux Example l From the car39s central computer fieldsm loulul 3nOQE aul oi Four possible display items Miles remaining M each is is Wide Choose which to display using two inputs x and y Use 8bit4x1 mux Digxta Desgn Copyright a ma Frank Val39nd TemperatureT Average milespergallon A Instantaneous mpg I and Additional Considerations Schematic Capture and Simulation inputs inputs u iul i 39 Outputs W E as Schematic capture Computer tool for user to capture logic circuit graphically Simulator Outputs commonly displayed as wave orm Digxta Desgn Copyright a ma Frank Val39nd 210 Computer tool to show what circuit outputs would be for given inputs Additional Considerations er NonIdeal Gate Behavior Delay 0 T in m hh Irme Real gates have some delay Outputs don t change immediately a er inputs change Digital Deggn Copyright mm 47 pm de v Chapter Summary Combinational circuits ircuit whose outputs are function of present inputs No state Switches Basic component in digital circuits Boolean logic gates AND OR NOT Better building block than switches Enables use of Boolean algebra to design circuits Boolean algebra uses truefalse variablesoperators Representations of Boolean functions Can translate among Combinational design process Translate from equation or table to circuit through wellde ned steps More gates NAND NOR XOR XNOR also useful Muxes and decoders Additional useful combinational building blocks Digital Deggn oapyngm 2on6 Frank de 48 Digital Design Chapter 3 Sequential Logic Design Controllers Slides to accompany the textbook D1gxm1DesxgnFirstEdmon by Frank Vahid John Wiley and Sons Publishers 2007 tip www ddvahtd com Copyright ZQQ7 Fmkwm mm aqitmng mamp mrqmttrtaootrptuishtaammmm whawmhmsgwnj Manama giaasmztstmi ttuztaattwtm mm to Imapmglhiscopynght mm 2mg Mammy an soar y a 93mmmmmwwwpimroi publicbt rtzccn ssibtbwu ma wigs PowavPogn V u b mrpdj with mvmn omhm who1105204toqulicbrazcusiblamks higvmzx mammam m2 alymtvdadsmsovdismbufvddiudbtosmdambyothavyln mm Inm zmgmy ma mommantamvmtabttta sitrirnISovangm photocopjfng gt a nsu fngroyaltiq Aw own1150111111 upri itptmmnmummy maydqtainlftzwi f vacL Iciqlil p m w V519 1m macaw Wtth Introduction Sequential circuit Output depends notjust on present inputs as in combinational circuit but on past sequence of inputs Stores bits also known as having state Simple example a circuit that counts up in binary In this chapter we will Design a new building block a flipflop that stores one bit 7 Combinationa digit al Circuit Sequential digital circuit Combine that block to build multibit storage a register Describe the sequential behavior using a finite state machine know W Pw Convert a finite state machine to a controller a sequential circuit having a register and combinational logic Digtal Desigq Copynght 2006 Frank Vahid Nate slim With Ammatmn m dammed With a small red i mt tit animated items 74 Examgle Needing Bit Storage Flight attendant call button Press call light turns on Stays an alter button released Press cancel light turns off Call buttun Logic gate circuit to implement this Call Cancel Doesn t work Q1 when Call1 but doesn t stay 1 when Call returns to 0 Medsomeform of feedback in the circuit 5 Cancelbmtanprexxedrlxg mm of Digital Design cumin mm 3 pm ma v First attempt at Bit Storage We need some sort of feedback 5 o Does circuit on the right do what we want t No Once Q becomes 1 when S1 Q stays1 forever no value of S can bring Q back to 0 2 o o 0 Digital Design cumin mm 4 memd i Bit Storage Using an SR Latch 7 Does the circuit to the right with crosscoupled want NOR gates do what we ne come up with that circuit Maybe just trial and error a bit of insight Yesl How did Digital Design Copyright mm 5 pm ma v Example Using SR Latch for Bit Storage SR latch can serve as bit a mm storage In preVIous example MDquot of flightattendant call button Elli Call1 sets Q to 1 Q stays 1 even alter Call0 a Cancel1 resets Q to 0 mm til 5 But there s a problem a 531 i R Digital Design Copyright mm a pmvtm ri39 Problem with SR Latch F Problem If 81 and R1 simultaneously we don t know what value Q will take slightly longer than the other Q will eventually settle to 1 or 0 rbut we don t lmow which 0 Digital Dehgh capynght 2mm 7 pm Valud v Qmay oscillate Thehbecause onepathwill be l H n n H n 1 n Problem with SR Latch Problem notjust one of a user pressing two buttons at same time Can also occur even if SR inputs come from a circuit that supposedly never sets 81 and R1 at same 39 e The longer path from x to R than to 3 causes SR11 for short Lime 7 could be long enough to cause oscillation Digital De gn R oapyhght o 2on6 Frank Valud Solution LevelSensitive SR Latch LEVElrSEnSlthE SR latch Add enable input C as shown Only let S and R change when C0 El lLll e Cll cult ll l frol lt OfSR l leVel SetS SRM except onelly due to path delays C Change Cto1 only alter suf cient time for S antho be stabe Q When C becomes 1 the stable 3 and R W I Mn 12 t the SR latch s 31 R1 inputs LevelsensnlveSR latch 7 9h SR7 7 Wety x S n R 1 Levelrsensltlve D SR latch symbol 1 c I l 1 I l R39l E Digital oestgn cammmm S1R1 never 11 9 pmvtm r Clock Signals for a Latch change musl not x v change Clk Tlme0 U 715 0 ns 20 HS 30 HS 40 HS 50 ns 60 HS 0 l l l u t o l o How do we know when it s safe to set 01 Most common solution make C pulse updown C Safe to change X Y c ust not change x Y We ll See how to el lSLll e that later Clocksignal Pulsing signal used to enable latche C 39 Levelsensnlve sR latch s s Because lttlcks l llte a clock Sequential circuit whose storage components all use clock signals synchronous circuit Most common type Asynchronous Cll cultS e lmportal39lt toplc but lelt for advanced course Digital Design Capynght 2 6 in meam Clocks 392 safe lo x v change mus not x v change us Vans 20ns sons Aons Eons sons 0 lulll lll lll Clock period time interval between pulses Above signal period 20 ns Clock cycle one such time interval Above signal shows 35 clock cycles 1 GHZ 1 n5 Clock frequency 1period 100 MHZ 10 ns 10 MHZ 100 ns Above signal 39equency 1 20 ns 50 MHz 1s Digital Deggn Capynghl mm 11 pm vmd v LevelSensitive D Latch SR latch requires careful design to Dim ensure SR11 never occurs D D latch relieves designer of that urden Inserted inverter ensures R always opposite of l D c s D latch symbol 2 0 Digital Deggn Copynghl 2 6 12 memd o l o l o l o l o Problem with LevelSensitive D Latch D latch still has problem as does SR latch When C1 through how many latches will a signal travel Depends on for how Ion C1 ClkA signal may travel through multiple latches ClkB signal may travel through fewer latches Hard to pick C that is just the right length n we design bit storage that only stores avalue on the rising edge of a clock signal om ll atal39l39 Digital Deggn Capynght 2 6 13 pm mm D FlipFlop Flipflop Bit storage that stores on clock edge not level nsmg edges One design master n rva t Two latches output of rst goes to input ofsecond master 39 signal latch has Inverted clock N t So master loaded when co then servant when c1 Hzidredsof dmerent ip en 0 1 master disabled servant mp my loaded with value that was at Djust before C changed 39 exist a Us at D during rising edge ofC D fllpflop Digital Deggn oapynght o 2on6 Frank Vahd D FlipFlop internal design Just The triangle gt gt invert servant clock means clock ratherthan master inpul edge triggered Symbol for risingedge Symbol for fallingedge triggered D ip op triggered D ip op nslng edges fallin ed es m 1 j m DigitalDesxgn Capynght 2 6 15 pmvtm 739 D FlipFlop Solves problem ofnot knowing through how many latches a signal travels when gilkliggre below signal travels through exactly one ip op for ClkA or Why Because on rising edge of Clk all four ip ops are loaded simultaneously then all four no longer pay attention to their input until the 39 1 next rising edge Doesn t matter how long Is Two latches inside each fliprflop Digital Design Capynght 2 6 m pmvtm r D Latch vs D FlipFlop Latch is levelsensitive Stores D when C1 Flipflop is edge triggered Stores D when C changes from 0 to 1 aying levelsensitive latchquot or edgetriggered ip opquot is redundant Two types of ip ops rising or falling edge triggered Comparing behavior of latch and flipflop O Dfii Jim 9 iEI lt P FgtJ cammmm pmvm FlightAttendant Call Button Using D FlipFlop D ip op will store bit Inputs are Call Cancel and present value of D ip op Q Truth table shown below Catt 39rNiLCi i U U U H U PreSeNe vaiue V Circuit derived fromtruth tab e U n 1 l u0 m e D0 if using Chapter 2 ombinationai 39 01 make Di i r esign process i 1 O L u t l u D0 i o o I O I aurmake D4 t i 0 1 Let s give pnority 1 l i I to Caii W make 7 Di DigitalDesAgn Copynght 2 6 18 pmvma Bit Storage Summary Feature s and R unly have 2112M when 01 m 2 can design uutside six11 yield circuit 5 snm never unde ned o nappEnswnen 01 Prublern ayuiding six11 can be a burden mums mare em an rnal Eatestnan SR rum gale mum is lessuran issuetuday mu snurt may nut enable a slave We considered increasingly better bit storage until we arrived at the robust D flipflop bit storage Digital De gn Capynght 2mm Frank Vahd Basic Register Typically we store multibit items eg storing a 4bit binary number Register multiple flipflops sharing clock signal From this point we ll use registers for bit storage No need to think oflatches or ip ops But now you know what s inside a register 3 2 I1 Io reg4 03 O2 01 00 Digital De gn Capynght 2mm Frank Vahd Example Using Registers Temperature Display 7 Temperature history display Sensor outputs temperature as 5bit binary number Timer pulses C every hour each pulse 39 4 Pi s l 2nouis ago e ent noui ago Display Display Display M a4 a3 a2al a0 o4 o3 o2 pl on c4 c3 c2 cl c0 x3 x2 M TeinpeiatuieHistoiystoiage x0 in practice We would actually ayoio connecting tne tiinei output c to a clock input instead only connecting an osclllator outputto a clock input Digiiu Design Copynght 2 6 21 pm viiiiu v Example Using Registers Temperature Display Use three 5bit registers Digital DeSigii Capynglit zuuo Frank viliiu FiniteState Machines FSMs and Controllers Want sequential circuit with particular behavior over time Example Laser timer Push button x1 for 3 clock cycles How Let s try three ip ops b1 gets stored in rst D ip op Then 2nd ip op on next cycle then 3rd ip op on n OR the three ip op outputs sox should be 1 for three cycles Digital Deggn Capynght mm 23 pm him 7 Need a Better Way to Design Sequential Circuits Trial and error is not a good design method Mll we be able to guess a circuit that works for other desired 39or How about counting up 39om 1 to 9 Pulsing an output for 1 cycle every 10 cycles Detecting the sequence 1 3 5 in binary on a 3bit And a circuit built by guessing may have undesired behavior Laser timer What if press button again while x1 x then stays one another 3 cycles Is that what we wan Combinational circuit design process had two important things 1 A formal way to describe desired circuit behavior Boolean equation or truth table 2 A wellde ned process to convert that behavior to a circuit We need those things for sequence circuit design Digital Deggn Capynght mm 24 pm de 39 Describing Behavior of Sequential Circuit FSM FiniteState Machine FSM P SX Away to descri X cm X1 be desired behavior of sequential circuit a a Akin to Boolean equations for 39 39 be av39or cllC Example Make x change toggle 0 to 1 or1 to 0 every I l l clock cycle W wclel 391 warez I wcle quot yuaA Two states 0ft x0 and l i Onquot x1 List states and transitions among states state On Transition 39om Offto On or On to Off on rising clock edge 0mm 39 39 Arrow with no starting state x points to initial state when 39 39 39 circuit rst starts Digital Design Copyright mm 25 pm ma v FSM Example 0111repeat 39 WantO 1 1 1 0 1 1 1 Outputs x Each value for one clock cycle X0 CW vi CW vi CW w Can describe as FSM Four states M Transition on rising clock C edge to next state Elk sue mm 0mm m X Digital Design Copyright mm 25 pmvtm 39 Extend FSM to ThreeCycles High Laser Timer inputs b Outputs X in Four states Wait in Off state while b is 0 b When b is l and rising clock edge transition to On l Sets x1 dk On next two clock edges inputs transition to On2 then On3 b which also set x1 mmmm So x1 for three cycles after m tputs button pressed Digital Deggn cumin mm 27 pm mm v FSM Simplification Rising Clock Edges Implicit Showing rising clock on every transition cluttered Make implicit assume every edge has rising clock even if not shown inputs b Outputs x XE What ifwe wanted a transition without a rising edge We don t consider such inputs b Outputg X asynchronous FSMs less W5 common and advanced topic Only consider synchronous FSMs rising edge on every transition cumin mm 28 pm mm quot Note Transition Win no associated condition Mus mu new Iransistions to m state on m clock cycle FSM Definition FSM consists of inputs b Outputs x Set of states 0 Ex Off On1 On2 On3 Set of inputs set of outputs Ex Inputs x Outputs b er Initial state EX O sat 0ftran5iti n5 We o en draw FSM graphically Describes next states known as state diagram Ex Has 5 transitions Set of actions Sets outputs while in states Ex x0 x1 x1 and x1 Can also use table state table or textual languages Digital Deggn Copyright mm 29 pm de v FSM Example Secure Car Key Many new car keys include tiny computer chip When car rt car s computer under engine hood requests identi er 39om key Key transmits identi er mp 5 0mm 39 not computer shuts off car FSM ait until computer requests ID a1 Transmit ID in this case 1101 Digital Deggn Copyright mm m memd r FSM Example Secure Car Key cont Nice feature of FSM lnputs a Outputs r Can evaluate output behavior for different input sequen Timing diagrams show states and utput values for different input waveforms Ce Q Determine states and r value for given input waveform W MUL Elk inputs inputs 3 l a mummmnmmmm 0W State I o utput l ll V Digital Design Copyright zuuo Frank Vahld l lll39 FSM Example Code Detector Unlock door u1 only when sequence snob Also output 5 indicates that some colored button pressed Wait for start s1 in Wait Once started Start lfseered goto Pedl Them ifsee blue g a u oto Blue Then if see green go to l e l r err Then if See red go to RedZ e in that state open the door U l 3 u El uE uZl Can you tnckthis FSM to open the door Wrong button at any step return 0 Without krioWll ig the code to Wait Withouto o DigitalDeslgn penmg oer A Y Capynghtozuu pm to eS hold all buttons Simultaneously Vu Improve FSM for Code Detector Inputs srgba Outputs u u0 1 Not smallpmblamstill quotmums WI 11 4mm am New transition conditions detect ifwrong button pressed returns to Wait FSM provides formal concrete means to accurately de ne desired behavior Digital Design Copyright e mm 33 pm mu Standard Controller Architecture Howimplement FSM as sequential inputs pr Outputs x circuit Use standard architecture t t re laterquot to store tne present M 7 Mt state register can represent fuur states 7 input b uutputx Known as controller est 0 S In bl V y stale register Drgnu Desxgn N oapyngm 2mm 34 Fmvm Genera versron V 34 Controller Design Five step controller design process Step DL SCt39ipllun T Capture the FSM CrL an FSM that describes the desired behavior of the eentlvller o 7 Create the Create the standard arehiteeture by using a state register of 2 architecture appropriate width and eombiualjonal lot wtth inputs being the att register blts and the FSM inputs and outputs being the next state bits and the FSM outputs to Encoder1r miter Assign a uniuue bin 7 l number to etteh Eaeh binary number 5 repre nting a stat known 39 m mlemlingt Any eneoding will do w as lung t eath tlL39 has a unique eneoding Create the mate Create a truth table for the eombinational legie sueh that the log39 Tl table will generate the eorl39eet rrutputs l e rials Orrlering the inputs wtth state bi 39st makes this truth table tl iie the state behavior so the table is a state table 2 Impletlletlt the Implement the eombinational logie Using any method 5 emuhtnnrlnrmlingu Digital Design Copyright 2006 3 5 Frankde 7 Controller Design Laser Timer Example Step 1 Capture the FSM Inputs b Outputsx Already done xzo Step 2 Create architecture 2bit state register for 4 states Input b outputx Next state signals n1 n0 Step 3 Encode the states Any encoding with each state unique will work Digital Design Copyright 2005 35 rank Vahid Step 4 Create state table Drgml Deggn oapyngxu 2on6 Frank mm s 1 07 0 0n 8 012 i 1 Controller Design Laser Timer Example cont lnput Outputs X M Inpnls 1 T 0 0 1 o 1 1 1 1 0 o 1 0 1 1 1 o 1 0 0 1 1 1 o 1 Controller Design Laser Timer Example cont Step 5 Implement combinational logic Inputs Outpuls 51 st b x u u 0 0 0 0 07 0 o 1 o o 0quot O l 0 l 1 D sl lflelurs 0 1 1 1 1 L 0 m 51 501 sl sOb 5150 b 5150b In 1 O 0 1 1 1 lm 39 1 o 1 1 1 1 a 1 1 0 1 0 0 n0sl 50 b5150 b 5150 b 1 1 1 1 0 O 051 50 b5150 Duuuneugu Capynght 2 6 38 Fnukvmd e Controller Design Laser Timer Example cont Cumbmatiunai Lngic Step 5 Implement combinational logic cont WI m rm x5150 1th m 51 505150 n n0 si so b 5150 Digital Design Capynght 2mm Frank Vahld Understanding the Controller s Behavior ii cik st ED u gx iliiil ax input in Outputs Digital Design Capynght 2mm Frank Vahld 7quot Controller Example Button Press S nchronizer cycle2 cyde3 cycle4 39 l Want simple sequential circuit that converts button press to single cycle duration regardless of length of time that button actually pressed med such an ideal button press signal in earlier example like the button in the laser timer controller Digital Design Capynght 2 6 41 pm vim v Controller Example Button Press Synchronizer cont 5 FSM inputs bi FSM uutputs bu Step 2 Create architecture bail bui bail mum ai iagic Step i FSM FSM inputs bi FSM uutputs bu bi OJ hi I b 0 ii bu buEI bui Elk b Step 3 Encode states i i Step 4 State table Step 5 Create combinational circuit musings Capynght 2 6 42 pmwma c Circuit Controller Example Sequence Generator Want generate sequence 0001 0011 1100 1000 repeat Each value for one clock cycle Common eg to create pattern in 4 lights or control magnets of a stepper motor W Inputs none Outputs wxyz X Y 2 wxyz0001 wxyz1000 Corn binational logic I wxyz0011 wxyz1100 Step 1 Create FSM Step 2 Create architecture Inputs none Outputs wxyz wxyz0001 wxyz1000 0 1 o 0 0 wxyz0011 wxyz1100 Step 3 Encode states lupim illpllh V 39 ii rill X515W ys1 s0 zs1 n1 s1 xors0 n0 W w s1 jD gtX Create state table eate com inationa circuit 43 Controller Example Secure s 2 a r Wait 8 gt gt N Combinational 0 Q logic K1 0 13 I K2 8 K3 8 K4 1 l Unrrtml l 1 Digital Degign Well omit Step 5 Copyright 2006 Frank Vahid Car Key from earlier example Inputs Outputs 51 50 n2 n1 3 o gt oogt gt co l l co l l l o oooooo gt gt oo gt gt gt gt co 1 gt gt gt gt oo oo gt gt gt gt oo oo gtgt ogt ogt Ao gt o gt o gt o gt o How 000000 00 gt Agt A oo oo 00 000000 00 0c gt Agt gt w A 00 000000 00 oo gt gt oo gt o Step 22 Example Seq Circuit to FSM Reverse Engineering Whatdoes this ys1 1 0 CD 39 39td 25 5 sn cm 0 n 1xors0x 5 Xgt V n0s1quots0 x 2 mum v x Q states V w 1th mu outputs 92 3 i u w inputs gtlt mm V n n l X r l J n l l l n i i t it n X 0 Wm i n l l w i l l U 3 U l Work backwards n L y 1 d H A U 0 Wm if V 1Pickan statenames ou want y y 5 VIth outputs and Digital Dtstgn transitions Capynght 2 6 45 pm mu 39 Common Pitfalls Regarding Transition Properties a On one condition should b b ty ab11 e we next stae For all transitions leaving a state 39 a Else which one a One condition must be true ab ab What if For all transitions leaving a 4307 state b a Else where go a at Digxtal Design Copyright mm 45 pmvtuu Verifying Correct Transition Properties Can verify using Boolean algebra Answer Only 0 condition true AND of each condition pair for aiba b transitions leaving a state should equal 0 9 proves pair o t b can never simultaneously be true 0 One condition true OR of all conditions of transitions t a a b leaving a state should equal 1 9 proves at leas one 8mm a b condition must be true a ab a Example a aa b a a b Fallsl Mlghtl iot be t l e 50 a b Q For shown transitions prove whether Only one condition true AND of each pair is always 0 One condition true OR of all transitions is always 1 Digital Deggn oapyngm 2mm Frank de r Evidence that Pitfall is Common a Recall code detector FSM xed a problem with the transition conditions 0 Do the transitions obey the two required transition properties u Consider transitions of sta Start and the only onetruequot ar a a arbg ararb H I W was a r 0V 8 6 r bg O Wtbtg buttons at same time E dltl s a arrbg a r r bg an and arb Wlll bath b o 0 true Which one should be taken Q How to solve arlbt A ar should be arb g Falls Means that two of Start s likewise for ab 39 El transmons comd be true Note As evidence thE pi all iscummun Weadmitthemi akewasnutmtentiunal 48 Digital Deggn Capynght 2 6 A releWEY ulthe bunkeau ht n mema 9 Simplifying Notations aE aE FSMS w FD sume unassigned output n 51 W a implicitly assigned 0 39 Sequential circuits Assume unconnected clock bl t inputs connected to same 39 external clock Digital Deggn oapyngm to 2mm Frank de More on FlipFlops and Controllers Other flipflop types SR ip op like SR latch but edge triggered JK ip op like sR seJ R But when JK11 toggles 190 091 T ip op JK with inputs tied together Toggles on every rising clock edge Previously utilized to minimize logic outside ip op minimizing logic to such extent is not as important D ip ops are thus by far the most common Digital Deggn oapyngm to 2mm Frank de su edge lSe l le and Stablllze ll l ll ltel l lal la 0 clam Digital Design Capyngm 2mm Frank Vahld Can t change ip op input too close to clock edge W value doesn t have tlme to loop around t h NonIdeal FlipFlop Behavior ck Setup time time that D must be stable before edge DJ QL 39 Elsei stable value not present at ll ltel l lal latch Hold time time that D must be held stable after lupt me i ck DJ ll H hold tlme Leadstu DSElllatanl Violating setuphold time can lead to bad situation known as metastable state Metastable state Any ip op state other than stable 1 or 0 Eventually Settles to Ol le or other but We don t know Whlch For internal circuits we can make sure observe se up time But what ifinput comes 39om external asynchronous source eg button ress7 Partial solution Insert synchronizer ip op for asynchronous input Speclal lllprllop With very small setuphold tlme Doesn t completely prevent metastability Digital Design Capyngm 2mm Frank Vahld Metastability Setuptlme VlOlaIlOl l meta table State mmmi F Can t May L g ue m between failure MTBF a Probability arrMap 79mg metastable is lOW Digital De gn oapyngm 2on6 Frank de Metastability One ip op doesn t completely solve problem How about adding more synchronizer ip op Helps butjust decreases probability of metastability So how solve completely eta la e very lOW synchronizers de i5 u l I number o en given along with a circuit s incredibly low FlipFlop Set and Reset Inputs Some flipflops have additional inputs Synchronous reset clears Q to 0 ge on next clock ed nextco k Synchronous set sets Q to 1 on c edge Asynchronous reset clear Q to 0 immediately not dependent on dQE clock e Example timing diagram shown Asynchronous set set Q to 1 immediately Digital De gn oapyngm 2on6 Frank de cydeZ yde yd24 l 39 Initial State of a Controller All our FSMs had initial state But our sequential circuit designs did not lnputs x Outputs b x0 Can omplish using ip ops acc with resetset Inputs Shown circuit initializes ip ops to 1 Designer must ensure reset input is 1 during power up of circuit By electronic circuit design Digital Deggn oapyngm to zone Frank vma Glitching 39 u input changes before stable new output values Designer must determine whether glitching outputs may pose a problem If so may consider adding ip ops to outputs Delays output by one clock cycle but may be OK Digital Deggn oapyngm to zone Frank vma Glitch Temporary values on outputs that appear soon after 56 Active Low Inputs We ve assumed input action occur when input is l Some inputs are instead active when input is 0 active lowquot Shown with inversion bubble So to reset the shown ip op set R0 Else keep R1 Digital Deggn Capynght mm 57 pm de v Chapter Summary Sequential circuits Have state Created robust bitstorage device D flipflop Put several together to build register which we used to hold state Defined FSM formal model to describe sequential behavior Using solid mathematical models Boolean equations for combinational circuit and FSMs for sequential circuits is very impo ant Defined 5step process to convert FSM to sequential circuit Controller So now we know how to build the class of sequential circuits known as controllers Digital Deggn Capynght mm 58 pmvma

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