Computer Hardware Design
Computer Hardware Design ECE 4623
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This 2 page Class Notes was uploaded by Dr. Lorine Dicki on Monday October 26, 2015. The Class Notes belongs to ECE 4623 at University of Oklahoma taught by Staff in Fall. Since its upload, it has received 27 views. For similar materials see /class/229327/ece-4623-university-of-oklahoma in ELECTRICAL AND COMPUTER ENGINEERING at University of Oklahoma.
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Date Created: 10/26/15
ECE46235623 Computer Hardware Design L Help Sheet Language Templates Comment Comments begin With Operators VHDL oparators logical and or nand nor xor xnor not relational arithmetic 7 lt7 ltv gt7 gt rem mod abs concatenation amp LibraryUse The IEEE standard 1164 package declares stdilogic risingiedgeO etc library IEEE use IEEEstdilogic71164all use IEEEstdilogic arith al use IEEEstdilogiciunsigneidall Entity entity ENTI TYiNAME is P ltp ortideclarationsgt end ENTITI QNAME Port Declaration PORTiNAME ltmodegt lttypeispecgt example PORTiNAME in BOOLEAN n INTEGER range 0 to 31 PORTiNAME inout BIT PORTiNAME buffer BIT7VECTOR 3 downto 0 PORTiNAM m STDiLO c PORTiNAME out STDiLOGIC7VECTOR 0 to 3 Architecture architecture ARCHiNAME of ENTITYiNAME is egin ltstatementsgt nd ARCHiN Signal Declaration signal SIGiNAME lttypeispecgt example signal SIGiNAME BOOLEAN signal SIGiN NTEGER range 0 to 31 T signal SIG NAME BIT7VECTOR 3 downto 0 signal SIG NAME S39I39DiLOGIC signal SIGiNAME STDiLOGIC7VECTOR 0 to 3 Variable Declaration variable VARiNAME lttype7specgt exarnp e variable VARiNAME BOOLEAN variable VARiNAME INTEGER range 0 to 31 variable VARiNAME B variable VARiNAME BIT7VECTOR 3 downto 0 variable VARiNAME S39I39DiLOGIC variable VARiNAME STDiLOGIC7VECTOR 0 to 3 Constant Declaration constant CONSTiNAME lttypeispecgt ltvaluegt Exam les constant CONSTiNAME BOOLEAN TRUE constant CONSTiNAME INTEGER 31 constant CONSTiNAME BIT7VECTOR 3 downto 0 quot0000quot constant CONSTiNAME STDiLOGIC 39Z39 constant CONSTiNAME STDiLOGIC7VECTOR 3 downto 0 quot00quot
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