New User Special Price Expires in

Let's log you in.

Sign in with Facebook


Don't have a StudySoup account? Create one here!


Create a StudySoup account

Be part of our community, it's free to join!

Sign up with Facebook


Create your account
By creating an account you agree to StudySoup's terms and conditions and privacy policy

Already have a StudySoup account? Login here


by: Liliane Borer


Liliane Borer
GPA 3.56


Almost Ready


These notes were just uploaded, and will be ready to view shortly.

Purchase these notes here, or revisit this page.

Either way, we'll remind you when they're ready :)

Preview These Notes for FREE

Get a free preview of these Notes, just enter your email below.

Unlock Preview
Unlock Preview

Preview these materials now for free

Why put in your email? Get access to more of this material and other relevant free materials for your school

View Preview

About this Document

Class Notes
25 ?




Popular in Course

Popular in Computer Engineering

This 17 page Class Notes was uploaded by Liliane Borer on Monday October 26, 2015. The Class Notes belongs to COE1502 at University of Pittsburgh taught by DonaldChiarulli in Fall. Since its upload, it has received 39 views. For similar materials see /class/229353/coe1502-university-of-pittsburgh in Computer Engineering at University of Pittsburgh.

Popular in Computer Engineering




Report this Material


What is Karma?


Karma is the currency of StudySoup.

You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!

Date Created: 10/26/15
COE 1502 MIPS Generic RISC Instruction Set Architecture MIPS Instruction Set Architecture Instruction Set Architecture ISA 0 ISA Interface between compilerprogrammer and the hardware Instruction set Programmer accessible registers Instruction encodingrepresentation o The taxonomy ISA design space includes multiple unique design styles Driven by hardware platform and resource constraints 0 Historically significant issues instruction length vs memory size Register resources vs chiplevel interconnect o Considerations for modern architectures Instruction level parallelism Power consumption chip multiprocessor support Instruction Set Architecture Classification by operand encoding 0 One address architecture common in embedded controllers Instructions specify one address accumulator based o Two address architecture i86 One operand is both source and destination o Three address architecture lPs all RISC Instructions specify three addresses 2 operands and 1 destination What are the resource issues that drive each style Instruction Set Architecture Classification by memory access mode 0 loadstore ISA MlPs all RISC All ALUbased operations performed using registers o Operands and results Data is loaded into registers from memory with explicit LOAD instruction Data is stored from registers into memory with explicit STORE instruction typically includes very limited set of addressing modes 0 memory addressing ISA i86 many others Memory access is allowed as operand to most instructions e i86 add AXBaseAddressBX What are the tradeoffs here MIPS generic RISC Instruction Set Architecture 0 MIPS is a loadstore ISA All operations performed using registers o Operands and results Data is loaded into registers from memory Data is stored from registers into memory o MIPS has one addressing mode for loadstores baseoffset 32bit indirect pointer addresses set 16bit offset to O Byteaddressed memory set base register to 0 use offset o 32 general purpose integer registers MIPS Instruction Set Architecture Some have special purposes These are the only registers the programmer can directly use 0 gt constant 0 1 gt at reserved for assembler 23 gt v0v1 expression evaluation and results of a function 4 7 gt aOa3 arguments 14 8 15 gt tOt7 temporary values Used when evaluating expressions that contain more than two operands partial solutions Not preserved across function calls 1623 gt sOgt s7 for local variables preserved across function calls 24 25 gt t8 t9 more temps 2627 gt k0 k1 reserved for OS kernel 28 gt gp pointer to global area 29 gt sp stack pointer 30 gt fp frame pointer 31 gt ra return address for branchandlinks 0 Program counter PC contains address of next instruction to be executed MIPS Instruction Set Architecture 0 There are several distinct classes of instructions Arithmeticlogicalshiftcomparison Loadstore Branch Jump 0 There are three instruction formats encoding Rtype 6bit opcode 5bit rs 5bit it 5bit rd 5bit shamt 6bit function code 31726 i25721 20716 15711 i 1076 i 570 H upcade rs a rd shamt H function I type 6 bit opcode 5 bit rs 5 bit it 16bit immediate 1 31726 25721 20715 i 1570 i L Jtype 6bit opcode 26bit pseudodirect address 31726 i 2570 i upcade upcadei r5 a 1mm i Multicycle CPU Design a You are to design a multicycle CPU that implements the instruction set listed on the webpage 0 Refer to chapter 5 in the HampP text for design hints Note HampP design only includes a subset of the required instructions 0 Branch and jump types including andlink types 0 Shift instructions static and variable 0 Halfword and byte load and store Multicycle MIPS Platform Datapaths Multicycle MIPS Platfrom Overview A multicycle CPU splits the execution of each instruction into multiple clock cycles 0 Control unit is FSM Establishes datapaths for each instruction 0 A datapath is combinational logic where Input comes from memory element Output is latched into a memory element Data may have to be routed through a multiplexor May be represented with register transfer language 0 Components needed from COELib 32x32 registerfile Multicycle MIPS Platform Instruction Phases 0 Each instruction is separated into 45 phases 0 One phase per clock cycle 0 Overall clock period longest phase latency Balance the workload Instruction fetch o Fetch new instruction from memory compute next PC value 0 Performed for all instructions Decode o Fetch register values from register le compute branch address 0 Performed for all instructions Execute Perform ALS operation for ALS R and ltype instructions Compute address for load and store instructiQns Determine if branch is taken for branch instructions Jump forjump instructions 0 Link for branchandlink and jumpandlink instructions Memory 0 Access memory for load and store instructions skip for all others Write back 0 Write register result back to register file for ALSload instructions skip for all others Register Transfer Language Description 0 Consider execution for Rtype ALS instruction 0 Cycle one FETCH IR lt MemoryPC PC lt PC4 0 Cycle two DECODE ALUOUT lt PC SignExtendR15O4 Alt RegFileR2521 A B lt RegFIIeR2016 RTL cont 0 Cycle three EXECUTE ALUOUT lt ALUOpA B R106 R3126 IR5O 0 Perform ALU operation 0 Cycle four WB RegFiIeR1511lt ALUOUT 0 Write back result 0 Consider execution for load instruction 0 Cycle one FETCH IR lt MemoryPC o Fetch instruction PC lt PC4 0 Update PC 0 Cycle two DECODE ALUOUT lt PC SignExtendlR1504 0 Compute branch target in case this is a box branch instruction m J i A lt RegFilelR2521 39 m B lt RegFilelR2016 o Decode registervalues m H msumnmlwl even more RTL 0 Cycle three EXECUTE ALUOUT lt A SignExtendR150 o Baseoffset computation Cycle four MEMORY MDR lt MemoryALUOUT 0 Load data from memory this is the last one 0 Cycle five WB RegFieIR2521 lt MDR 0 Write back memory data to register file Memory Interface For this design assume that there is an external memory for instructions and data Memory interface Outputs 0 MemoryAddress MemoryDataOut MemRead MemWrite Inputs 0 MemDataln MemWait protocol CPUm2magmter acwR2adM2maQ Data Clock MemoryAddres s MemRead MEmWaxt MemoryDataIn CPU initiates the


Buy Material

Are you sure you want to buy this material for

25 Karma

Buy Material

BOOM! Enjoy Your Free Notes!

We've added these Notes to your profile, click here to view them now.


You're already Subscribed!

Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'

Why people love StudySoup

Bentley McCaw University of Florida

"I was shooting for a perfect 4.0 GPA this semester. Having StudySoup as a study aid was critical to helping me achieve my goal...and I nailed it!"

Jennifer McGill UCSF Med School

"Selling my MCAT study guides and notes has been a great source of side revenue while I'm in school. Some months I'm making over $500! Plus, it makes me happy knowing that I'm helping future med students with their MCAT."

Steve Martinelli UC Los Angeles

"There's no way I would have passed my Organic Chemistry class this semester without the notes and study guides I got from StudySoup."

Parker Thompson 500 Startups

"It's a great way for students to improve their educational experience and it seemed like a product that everybody wants, so all the people participating are winning."

Become an Elite Notetaker and start selling your notes online!

Refund Policy


All subscriptions to StudySoup are paid in full at the time of subscribing. To change your credit card information or to cancel your subscription, go to "Edit Settings". All credit card information will be available there. If you should decide to cancel your subscription, it will continue to be valid until the next payment period, as all payments for the current period were made in advance. For special circumstances, please email


StudySoup has more than 1 million course-specific study resources to help students study smarter. If you’re having trouble finding what you’re looking for, our customer support team can help you find what you need! Feel free to contact them here:

Recurring Subscriptions: If you have canceled your recurring subscription on the day of renewal and have not downloaded any documents, you may request a refund by submitting an email to

Satisfaction Guarantee: If you’re not satisfied with your subscription, you can contact us for further help. Contact must be made within 3 business days of your subscription purchase and your refund request will be subject for review.

Please Note: Refunds can never be provided more than 30 days after the initial purchase date regardless of your activity on the site.