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by: Mr. Reyna Wunsch


Mr. Reyna Wunsch
GPA 3.61


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Class Notes
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This 51 page Class Notes was uploaded by Mr. Reyna Wunsch on Monday October 26, 2015. The Class Notes belongs to COE1502 at University of Pittsburgh taught by Staff in Fall. Since its upload, it has received 50 views. For similar materials see /class/229355/coe1502-university-of-pittsburgh in Computer Engineering at University of Pittsburgh.

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Date Created: 10/26/15
Introduction to Design Tools COE 1502 Review Tools functions design flow 0 Four tools we will use in this course HDL Designer Suite 0 FPGA Advantage aka Renoir IDE to create hierarchical designs and generate HDL o ModeSim Robust logic simulator Xilinx o XST synthesis 0 PIace androute netlists onto FPGAs Review Tools functions design flow Generate Compile Synthesize using XST Placeand route Libraries in FPGA Advantage o A library is a collection of components Components have one or more views implementations 0 Block diagram truth table flow chart state machine VHDL architecture Each view has representations 0 Graphics VHDL simulator netlist synthesis netlist library CPUIib component view representation Components 0 Library components can be instantiated in other designs Shown as green blocks 0 For bottomup design Libraries also contain blocks 0 Attached to the design they were created in 0 Shown as blue blocks 0 For topdown design Embedded blocks embedded into block diagram 0 Shown as yellow blocks 0 Embeds behavior into structure LHECC lockup m mam vm gap Libraries in FPGA Advantage 0 Libraries are stored in four subdirectories in your group directory eg apha source directory HDL directory CPU b Simulation directory synthesis directory For each library you use or create libraiy mappings to these directories must be specified The mappings for your set of libraries are stored in your project file 0 Lives in your group directory o A project in FPGA Advantage is a set of library mappings o Create a new project in your user workspace tutorial Projects Libraries Components Views Library Component Projects Libraries Components Views 39 a Design Mang HE E Example Design ALU Open HDL Designer and create your project rwmtw 7 7 Page Setup ed Libvalie Em lg m jMH mean Duly lelalie Em 39 g Creating a New ijecl Hesse spec wm a nan gnaw new we Namemew Wm mm Ubhana WA aeseupm Dayecmw with my pmiecl Maw w Lbe ealed cam 5n2 Blame V Name my the delauhwmkmghhravy ALU I Advanced Adduianal nhralhs can he maxed via w New may Wm am lewd Huh EXR id 7 V7 39 Lijm Summary 39 aijui Cnnlenl E Can22 He u Praia2t madam EXEUEIEUZ Mm m Ema 0 cxm new man lids Heine dealvale 4quot mm mm may as Aw F Shared PmlectFk EDSJEAMiH MBshmed hth lt am am Lana HA1 Example Design ALU 0 Library and project views in Design Manager I Design Manager Pruject examples File Edit View HDL Tasks Tank Obtians Wlndnw 7 New Library Library Type Example Design ALU 3 New ary 7 A Library that can be compiled and generated From This library can also have mappings lot Versrnn Management A reusable HDS library that cannot be compiled or narated hhraryquot Specified a 5 R It 0 P FII Gram as 39 0MP e t VHDL view gt pen rule Ver ogView Explore Library r 1m mm Registered View b r P l lad P 5 Text le 39 Import Gate Level Test Bench PagaSstup A Print CtrlP Project r Print Hierarchy H L HTML Exportquot Sequencervhd c r en Innaer u n m J wk L J r and library name alternatively you may explicitly specify themlie Uncheck39Auio Library Name IEUELib v F Auto Huotdireatow M1502 Browse Hnstlrnsozxcozubxhds 11 Back I Finish Cancel I Help A CMsjmlaclsALLiAL HDSYEAMHEIMEsharer5 m maxim HDL Ewdrjrniecl ALUWthwdi HDS Dstjmiul ALmALLLhMMs gem EDEirh v HDL mauzwumm HDS m nmnzinws ear q 1 0 Fr mud r a 9 chniervhth 98 see 9 mudulawam 9H m 9h 34ddvzlanersk ii WWW a quQE ErL Sh wing nwmlmana Dnlllihlalles Emem a FPELPackage Tasks Viewvuinls w Memainadel m gt3 MemmyMadellslmcl E g RegFileSZxSZ a RegFileSZxSZ gaggrreazxazrsrmu A Design JALLiHAW inc saved successlvlly Example design ALU 0 Specifications for ALU GOAL implement all logical arithmetic shift and comparison operations in MIPS instruction set 390 Operations Bitwise AND OR XOR and NOR Signed and unsigned addition subtraction o Overflow detection zeroresult detection Signed and unsigned setonIessthan comparison Logical shift left and right arithmetic shift right Must accept 2 x 64bit operands and produce a 64bit result Example design ALU o Inputs A B 64 bits SHAMT how many bits ALUOP how many bits 0 13 total operations Outputs C 64 bits Overflow Zero Example design ALU 0 We will work topdown to design the ALU First step is to create toplevel design Need to choose a view which will implement a VHDL architecture View type block diagram 0 Implements structural VHDL From design browser 0 File New Graphical View Block Diagram Example Design ALU mm 1 5E WNW H 5E WWW u mg I mang S gna s Example design ALU 0 First let s discuss the block diagram toolbars Add Signalbus Generate VHDL and simulate Add embedded block Add blockcompo nent Add Poms One level upSave Example design ALU 0 First add interface signals with ports using the toolbar tool wire with port ALUOp Or O Zem vA Ov vvvO Ov2r ow tsHm Ore r 7 777 if 39 39 39 39 39 39 39 39 39 39 39 39 39 39 1mm wearingxemm mmIMww mailer Mama IA l39 mm tilesmag o Note signal widths in wire properties it fries 3i DEIWNTEI 39y enigma l1quot 13f quot 0 Save the block diagram into the ALU library Example design ALU The component name will be ALU Let s look at the ALU symbol Click up in BD or Use the design browser Drjinn Manager 7 Pmth example 41 my Task ShawHide 7 may a Expand At 339 U Suurce mg Symbut mg V Savz A5 015an u u I new gar ALU exempts hdsjackagejrbvavy tenarvjackagejhvaty Example design ALU o The symbol looks something like this We can change the shape and pin locations here 0 Right click then Autoshapes 0 Make the symbol look like an ALU symbol Example design Go back to the block diagram window and let s generate VHDL for our design 0 Next let s take a look at th e D L 0 Ge gemamammgcwe axphaxALuwnaowmma g e n e rate d E71 Vii58km Example d VHDL Entity ALUALUsymbol Bui Created by ajnoyolaUNKNOWN TWEE39I39Y at 234641 03102005 Generated by Mentor Graphics 1d 83 15 Y ieee USE ieee stdlogic1154all USE ieee stdlogicarithall ENTITY ALU I S PORT A IN ALUOp IN B IN 2 IN SHAMTHIGH IN Overflow 39 OUT R OUT Zero OUT Declarations END ALU std logic vector s tdlogicvec tor std logic vector stdlogicvector s tdlogic std logic stdlogicvector s tdlogic HDL Designer TM 20051 VHDL Architecture ALUALUstruct Created by ajnoyolaUNKNOWN TWEETY at 234542 03102005 Generated by Mentor Graphics39 HDL Designer I M 20051 Build 83 LIBRARY ieee USE ieee stdlogic1154 all USE ieee stdlogicari th all ARCHITECTURE struct OF ALU IS Architecture declarations Internal signal declarations BEGIN Instance port mappings END struct COE 1502 Design Synthesis Synthesis Background 0 Idea Compile VHDL into a cell level netlist o A netlist is a graph Vertices represent cells such as gates latches etc Edges represent interconnection wires 0 To do this we need VHDL A technology cell library Place androute netlist onto FPGAASIC To do this we need Netlist CLB specification and routing matrix FPGA 0 Output is FPGA routing bitmap Synthesis Flow Netlists 0 Synthesis tool output format is a text EDIF netlist 0 Example 4 1nstance O as 1x Note that AND2 instance ANDZ as 1x3 and 0R2 are 1x1 A B D technology cells 1X3 D C E Netlists 0 Actual EDIF output edifLeVel 0 technology numberDefinition cell example cellType GENERIC View struct edif example edifVersion 2 O O ViewType NETLIST interrace edifLe e port A direction INPUT keywordMap keywordLevel 0 port B Lrec LOH INPUTH status port C direction INPUTH writte port E direction OUTPUT timestamp 2003 01 23 l7 13 48 CODtentS p am quotLeonardoSpectrum Level 3quot version quot2002b21quot instance ixl ViewRef INTERFACE libraryRef PRIMITIVES author quotExemplar Logic IDCHH instance 1x3 ViewRef INTERFACE external PRIMITIVES edifLevel O CellRef 0R2 cellRef ANDZ libraryRef PRIMITIVES H k M 1 Hum in limit mn Mined cell O39RZ cellType GE RIC portRefA I I View INTERFACE VlewType NETLIST portREf p0 InstaDCERef 1xl interface net B port rename p0 quotin0quot direction INPUT Um Dal port rename pl quotinlquot direction INPUT portRef B port out direction OUTPUT m portRef p1 instanceRef 1x1 HM cell ANDZ cellType G IC net c View INTERFACE ViewType NETLIST 349mm interface portRef C Port IEname p2 quotin0quot direction INPUTH portRef p3 lDStaUceREf 1X3 H39H port rename p3 quotinlquot direction INPUTH n t E r o 1 w nmnnm joined portRef E portRef out instanceRef ix3 jOin39ed portRef out instanceRef ixl portRef p2 instanceRef 1x3 33 design example cellRef example H libraryRef alu Design Wrappers Your ALU design must be placed into a wrapper before you perform synthesis The ALU wrapper is located in the COELib library 0 Wrapper shares a signal namespace with its wrapper and the signals on the WildOne card 0 Copy the wrapper to your ALU library Your ALU is already instantiated inside 0 Yourjob Wire up desired signals to 32 output buffers which will be visible on the logic analyzer for testing Topmost buffer corresponds to LSB on LA wire downward Suggestion bring out ALUOp 8 bits of A B and R and Overflow Zero RST and PCLK 0 One you do this generate a netlist for the wrapper using Leonardo Use the tutorial on the website ALU Wrapper Structure FPGA Pinout wrapper ALU design wrapper Design Wrapper Included as VDHL code and synthesized wyour design Pinout Wrapper pre synthesized and included during place and route Host app registers YourALU AL A m w anmlennadasnamum wahmugw nmmnants quotnunuuuuuu Pinout Wrapper WildStar card Daughter card Your ALU in peO connectors f E 239 s 4 v w w I 39 r 3 5quot quot 397 39 V 39 39 f I T V xquot m a 739 7 r 39 I Memory PCI interface p61 Preparing for Synthesis 0 Copy the wrapper design from COEIib to your project lib a Make sure that the ALU instance in the wrapper maps to your design Running syntheSIs v 625an HavavchY gas new Qawnstv ahv r m gtltmnx Helium sum 43 a Minx synlhesanm x m L Fl y Haw mmgh Cnmpnnanls Gansrata and inns mu anhra 5mm Synh uams m Haw came a XVIrvx 5ynH ves s m1 COE 1502 Sequential Logic amp FSM Control Add control to your processor You need a way to assign control states for each cycle of instruction execution Define data path level RTL for each cycle of each instruction in some cases for instruction groups The control state sequence is different for each instruction Each control state sets the control signals that implement the data path level operation Build a Finite State Machine FSM that generates the sequences of control signals Finite State Machines FSM Combinational vs Sequential Logic 0 Combinational logic Outputfinput o Sequential logic Output f input input history requires memory elements Finite State Machines No missile detected a FSMs are made up of input symbol alphabet output symbol alphabet set of states one is start state Set of transitions No locked missile hit Input alphabet missile detected locked on hit miss Output alphabet re FSMs and hardware Registers Hold encoded value of current s a e Output logic Encodes output of state machine I Moore le 7 Outputfcurrentstate 0 Output values associated with states I Mealystyle 7 Output fcurrent state input 0 Output values associated with state transitions 0 Outputs asynchronous Nextstate logic Encodes transitions from each state Next state fcurrent state input Synchronous state machines transition on clock edge RESET signal to return to start state Example 0 Design a coke machine controller 7 Releases a coke after 35 cents entered 7 Accepts nickels dimes and quarters returns change 7 Input Alphabet and encoding 0 Driven for 1 clock cycle while coin is entered o COIN 00 for none 01 for nickel 10 for dime 11 for quarter 7 Output alphabet and encoding 0 Driven for 1 clock cycle 0 RELEASE 1 for release coke o CHANGE releases change encoded as COIN input Create a new state machine view w HUL magram tasks ADD mytam Ammanun Upnnns wmaw HEW Fl 5 Q maymeme n gt Concurrent Statements mmgme ammo S gnat Status Frucess mama s mocked 7mg mm 7mg Other globa VHDL Clockreset and stalt state de nition magmaquot W pe d lt nk 39ca 7mg hm mew vumt MwE z r Add States and Transitions o We ll design this controller as a state diagram View in FPGA Advantage d39mah n39lnl2 5tatzmaqram n g Mew H Dial a m swam Emmetan Ojtmns wnaaw OLE delD lm m v FlWi Add new state Add new hierarchical state Note transitions into and out ofa hierarchical state are implicitly ANDed with the internal entrance and exit conditions Add new transition Define Click on a state and get this dialog to specify the output values for each state in the state properties Numhev ar setectedstates t Name State Type vate State v r F r msE mphcu aavhack EntvyActmns StateActmns EMEW erhte Define Click on a transition to get this dialog to r 7 WW F We specify the transition conditions and priority in the transition properties Hierarchical States hstatel A nm and E nm A um and 3 mn A A mn and E nm Example change m re ease lt u ange lt m u lt D Example tmkecurrenl lcmkey nex 0 Let s take a look at the VHDL for the FSM Enumerated type STATETYPE for states Internal signals currentstate and nextstate clocked process handles reset and state changes nextstate process assigns nextstate from currentstate and inputs 0 Implements next state logic 0 Syntax is case statement output process assigns output signals from currents tate o Might also use inputs here Code FSM Architecture ARCHITECTURE fsm OF coke IS Architecture Declarations TYPE STATE TYPE IS I gene ass1gnment problem to the 23 synthesis engine e30 e15 Wlth user 1nput on style e20 33 such as one hot etc 3 e45 Declare current and next state signals SIGNAL current state STATEiTYPE SIGNAL nextistate STATE TYPE Clocked Process The process models the memory component clocked PROCESS clk rst BEGIN IF rst 39139 THEN currentstate lt standby Reset Values ELSIF clk39EVENT AND clk 39139 THEN currentstate lt nextstate Default Assignment To Internals END IF END PROCESS clocked Next state Process This process implements the combinational logic for the next state output nextstate PROCESS coin currentstate BEGIN CASE currentstate IS WHEN standby gt IF coin quot01quot THEN WHEN e10 gt nextstate lt e5 ELSIE coin quot10quot THEN nextstate lt e10 ELSIF coin quot11quot THEN nextstate lt e25 ELSE nextstate lt standby END IF WHEN e5 gt IF coin quot10quot THEN nextstate lt e15 ELSIF coin quot11quot THEN nextstate lt e30 ELSIE coin quot01quot THEN nextstate lt e10 ELSE nextstate lt e5 END IF Output Process This process implements the combinational logic for the next state output PROCESS currentstate BEGIN Default Assignment change lt quot00quot release lt 39039 Default Assignment To Internals Combined Actions CASE currentstate IS WHEN standby gt change lt quot00quot release lt 39039 WHEN e5 gt change lt quot00quot release lt 39039 WHEN elO gt change lt quot00quot release lt 39039 WHEN e25 gt change lt quot00quot release lt 39039 WHEN e30 gt change lt quot00quot release lt 39039 WHEN e15 gt change lt quot00quot release lt 39039


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