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## DIGITAL LOGIC DESIGN

by: Trace Mante MD

20

0

3

# DIGITAL LOGIC DESIGN CSCE 211

Trace Mante MD

GPA 3.61

T. Mintz

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COURSE
PROF.
T. Mintz
TYPE
Class Notes
PAGES
3
WORDS
KARMA
25 ?

## Popular in Computer Science and Engineering

This 3 page Class Notes was uploaded by Trace Mante MD on Monday October 26, 2015. The Class Notes belongs to CSCE 211 at University of South Carolina - Columbia taught by T. Mintz in Fall. Since its upload, it has received 20 views. For similar materials see /class/229572/csce-211-university-of-south-carolina-columbia in Computer Science and Engineering at University of South Carolina - Columbia.

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Date Created: 10/26/15
Chapter 13 amp 14 Review Assume none of the state graphs reset after a 1 output 1 What is the difference between a Mealy sequential circuit and a Moore sequential circuit 2 Is this circuit a Mealy or Moore circuit A L131 3 Construct a timing chart for the input sequence X 011010 Each ip op is risingedge triggered and has an initial state of 0 Assume a small delay for state changes on each ip op 4 Construct the state table for this circuit 5 Construct the state graph for this circuit 6 Is this circuit a Mealy or Moore circuit 7 Construct a timing chart for the input sequence X 001110 Each ip op is fallingedge triggered and has an initial state of 0 Assume a small delay for state changes on each ip op 8 Construct the state table for this circuit 9 Construct the state graph for this circuit 10 Design a Moore sequential circuit that detects the sequence 1101 11 Design a Mealy sequential circuit that detects the sequence 001 12 Design a Mealy sequential circuit that detects an input sequence that has at least 2 zeroes 13 Design a Moore sequential circuit that detects an input sequence that has at most 3 ones Chapter 11 Review 1 Draw the circuit for an SR Latch 2 Construct the truth table for the SR Latch 3 Complete this timing diagram tp lns 5 What is the setup and hold time of an input 6 Circle the active edges of this clock for an active falling edge circuit clk 7 Complete the timing diagram for this rising edge triggered D ip op tsu 2ns th 2ns and tp lns 9 Construct an active rising edge JK ip op using SR latches 10 Complete the timing diagram for this active falling edge JK ip op tp lns

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