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by: Trace Mante MD


Trace Mante MD

GPA 3.61

C. Huang

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C. Huang
Class Notes
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This 29 page Class Notes was uploaded by Trace Mante MD on Monday October 26, 2015. The Class Notes belongs to CSCE 210 at University of South Carolina - Columbia taught by C. Huang in Fall. Since its upload, it has received 47 views. For similar materials see /class/229583/csce-210-university-of-south-carolina-columbia in Computer Science and Engineering at University of South Carolina - Columbia.

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Date Created: 10/26/15
CSCE 210 iComputer Hardware Foundations ChinTser Huang huanclctcsescedu University of South Carolina i Chapter 9 InputOutput Basic Model Processing speed or program execution determined primarily by ability of IO operations to stay ahead of processor Input 10272009 Process Output i IO Requirements Means for addressing different peripheral devices A way for peripheral devices to initiate communication with the CPU An efficient means of transferring data directly between IO and memory for large data transfers since programmed IO is suitable only for slow devices and individual word transfers Buses that interconnect highspeed IO devices with the computer must support high data transfer rates Means for handling devices with extremely different control requirements 10272009 IO Interfaces Are necessary because of Different formats required by the devices Incompatibilities in speed between the devices and the CPU make synchronization difficult Bursts of data vs streaming data Device control requirements that would tie up too much CPU time 10272009 Examples of IO Devices Device InputOutput Data rate Type Keyboard Input 100 bps char Mouse Input 3800 bps char Voice inputoutput InputOutput 264 Kbps block burst Sound input Input 3 Mbps block burst or steady Scanner Input 32 Mbps block burst Laser printer Output 32 Mbps block burst Sound output Output 8 Mbps block burst or steady Flash drive Storage 480800 Mbps read block burst 80 Mbps write USB Input or output 16 480 Mbps block burst NetworkWireless LAN Input or output 11 100 Mbps block burst NetworkLAN Input or output 1001000 Mbps block burst Graphics display Output 8008000 Mbps block burst or steady Optical disk Storage 4 400 Mbps block burst or steady Magnetic tape Storage 3290 Mbps block burst or steady Magnetic disk Storage 2403000 Mbps block burst 10272009 Simple IO Configuration IO IO module device CPU 10272009 V More Complex IO Module 10272009 IO Techniques Programmed IO CPU controlled IO Interrupt Driven IO External input controls Direct Memory Access Controllers Method for transferring data between main memory and a device that bypasses the CPU 10272009 9 Programmed IO Use IO address register and IO data register in CPU One word transfer per IO instruction Address information for each IO device LMC IO capability for 100 devices Full instruction fetchexecute cycle Primary use keyboards communication with IO modules see DMA 10272009 10 Programmed IO Example CPU 10272009 irwri keyboard li O module 1 CPU executes INPUT 2e instruction Address 24 is copied to the HO address register 2 Address 24 is recognized by the keyboard U0 module A readfwrite controi line indicates that the instruction is an INPUT Figure continues on next slide 11 Programmed IO Example U0 data register buffer 3 3 A buffer in the HO module r holds a keystroke in this case I I l 39 ASCII 68 the letter Dquot The data is transferred to the llD data register i l I i 4 From there it is copied to the appropriate accumulator or I 39 generalpurpose register i completing the operation accumulator 10272009 12 Interrupts Signal that causes the CPU to alter its normal flow of instruction execution frees CPU from waiting for events provides control for external IO initiation Examples unexpected input abnormal situation illegal instructions multitasking multiprocessing 10272009 13 Interrupt Terminology Interrupt lines hardware One or more special control lines to the CPU Interrupt request Interrupt handlers Program that services the interrupt Also known as an interrupt routine or device driver Context Saved registers of a program before control is transferred to the interrupt handler Allows program to resume exactly where it left off when control returns to interrupted program 10272009 14 The CPU The Interrupt Cycle Fetch l Execute cycle Interrupt cycle Fetch Next Instruction l Execute Instruction Interrupts Disabled 1 Process Check for Interrupt Interrupt 10272009 Servicing the Interrupt 1 Lower priority interrupts are held until higher priority interrupts are complete 2 Suspend program in progress 3 Save context including last instruction executed and data values in registers in the PCB or the stack area in memory 4 Branch to interrupt handler program 10272009 16 Servicing an Interrupt memory stack area registers A PC registers A PC 10272009 PC 1 Before interrupt arrives program A is executing The program counter points to the current instruction 2 When the interrupt is received by the CPU the current instruction is completed all the registers are saved in the stack area or in a special area known as a process control block The PC is loaded with the starting location of program B the interrupt handler program This causes a jump to program B which becomes the executing program registers A 3 When the interrupt routine is complete the registers are restored including the PC program counter and the original program resumes exactly where it left off 17 Use of Interrupts Notify that an external event has occurred realtime or timesensitive Signal completion printer ready or buffer full Allocate CPU time time sharing Indicate abnormal event CPU originates for notification and recovery illegal operation hardware error Software interrupts 10272009 18 Print Handler Interrupt Original program executing print interrupt handler Software interrupt to print handler gt Suspended Fill printer buffer l Resume other work Printer ready interrupt Continue 10272009 19 Using an Interrupt for Time Sharing Program 1 Program 2 Operating system dispatcher program Executing Time Clock 4 interrupt 9 Suepenueu Select next program One quantum Resume executing program 2 Clock interrupt gt suspended quot Select next program 10272009 20 Interrupt Processing Methods Vectored interrupt Address of interrupting device is included in the interrupt Requires additional hardware to implement Polling Identifies interrupting device by polling each device General interrupt is shared by all devices 10272009 21 Vectored Interrupts Interrupt K Memory occurs Address of interrupt A Address of interrupt B Address of interrupt K Interrupt A Jump to K service routine service routine Interrupt K service routine 10272009 22 Polled Interrupts Interrupt K Memory occurs gt General interrupt I polling routine Polls devrces to determine which device then Interrupt A Jump to K service routine servrce routine Interrupt K service routine 10272009 23 Multiple Interrupts Example Time Interrupt A occurs Interrupt B occurs lnterru pt C occurs 10272009 Original interrupt rite n 5 program service A service Executing Suspended gtExecuting Suspended l Executing i39GLij il t Suspended 39 Executing Executing lt Completed 24 Direct Memory Access Transferring large blocks of data Direct transfer to and from memory CPU not actively involved in transfer itself Three required conditions for DMA The IO interface and memory must be connected The IO module must be capable of reading and writing to memory Conflicts between the CPU and the IO module must be avoided 10272009 25 DMA Instructions Application program requests IO service from operating system privileged programmed IO instructions To initiate DMA programmed IO is used to send the following information 1 location of data on IO device 2 the starting location in memory 3 the size of the block 4 readwrite Interrupt to CPU upon completion of DMA 10272009 26 DMA Initiation and Control iO instructions lO module CPU Memory address 39 disk controller Disk address Size of block Read or write Initiate transfer 2 Memory MA D39Sk controller I 3 nterrupt Disk CPU controller 10272009 1 Programmed lO used to prepare IO module for transfer by providing required information and initiating transfer DMA transfer In this case data is transferred from disk to memory Upon completion disk controller sends completion interrupt to CPU 27 g IO Module Interfaces CPU A 0 1 CPU mOdU39eS Device interface interface lO device 10272009 28 IO Module Functions Recognizes messages from devices addressed to it and accepts commands from the CPU Provides a buffer where the data from memory can be held until it can be transferred to the device Provides the necessary registers and controls to perform a direct memory transfer Physically controls the device Copies data from its buffer to the devicefrom the CPU to its buffer Communicates with CPU 10272009 29


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