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by: Trace Mante MD


Trace Mante MD

GPA 3.61

C. Huang

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C. Huang
Class Notes
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This 32 page Class Notes was uploaded by Trace Mante MD on Monday October 26, 2015. The Class Notes belongs to CSCE 210 at University of South Carolina - Columbia taught by C. Huang in Fall. Since its upload, it has received 67 views. For similar materials see /class/229583/csce-210-university-of-south-carolina-columbia in Computer Science and Engineering at University of South Carolina - Columbia.

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Date Created: 10/26/15
CSCE 210 iComputer Hardware Foundations ChinTser Huang huanclctcsescedu University of South Carolina Chapter 8 CPU and Memory Design Implementation and Enhancement Current CPU Architectures Current CPU Architecture Designs Traditional modern architectures VLIW Transmeta Very Long Instruction Word EPIC Intel Explicitly Parallel Instruction Computer Current CPU Architectures IBM Mainframe series Intel X86 family IBM POWERPowerPC family Sun SPARC family 10202009 Traditional Modern Architectures Problems with early CPU Architectures and solutions Large number of specialized instructions were rarely used but added hardware complexity and slowed down other instructions Slow data memory accesses could be reduced by increasing the number of general purpose registers Using general registers to hold addresses could reduce the number of addressing modes and simplify architecture design Fixedlength fixed format instruction words would allow instructions to be fetched and decoded independently and in parallel 10202009 VLIW Architecture Transmeta Crusoe CPU 128bit instruction bundle molecule Four 32bit atoms atom instruction Parallel processing of 4 instructions 64 general purpose registers Code morphing layer Translates instructions written for other CPUs into molecules Instructions are not written directly for the Crusoe CPU 10202009 5 VLIW Instruction Format F aDEl ADI LEM EH Dr Elixir1151quot ummt km IIMraliclr EIJI IEIi lii 39l Emma I E Atoms Flaming Integer Lunadrama Branch Parallel mim ALL unl1 unit Instfl rlnfrlt39ln executlm autumn unit uni15 10202009 EPIC Architecture 128bit instruction bundle 3 41bit instructions 5 bits to identify type of instructions in bundle 128 64bit general purpose registers 128 82bit floating point registers Intel X86 instruction set included Programmers and compilers follow guidelines to ensure parallel execution of instructions 10202009 FetchExecute Cycle Timing Issues 10202009 Computer clock is used for timing purposes for each step of the instruction cycle GHz gigahertz billion steps per second Instructions can and often take more than one step Data word width can require multiple steps Fetchexecute timing diagram PC1 gtPC MDR gtR Radd gtMAR llli MDRA A Next instruction Pc gt MAR Time CPU Features and Enhancements Separate Fetch Execute Units Pipelining Multiple Parallel Execution Units Scalar Processing Superscalar Processing Branch Instruction Processing 10202009 Separate FetchExecute Units Fetch Unit Instruction fetch unit Instruction decode unit Determine opcode Identify type of instruction and operands Several instructions are fetched in parallel and held in a buffer until decoded and executed IP Instruction Pointer register holds instruction location of current being processed Execute Unit Receives instructions from the decode unit 1020720 9lpproprlate execution unIt serVIces the Instruction10 Alternative CPU Organization Execution unit 10202009 Bus to memory Fetch unit E Instruction BUS I fetch unit Mariam I unit I I I I Instruction decode unit Addre smg I I d Arithmetic Execution logic unit 39 control unit x 11 Instruction Pipelining Assemblyline technique to allow overlapping between fetchexecute cycles of sequences of instructions Scalar processing Average instruction execution is approximately equal to the clock speed of the CPU Problems from stalling Instructions have different numbers of steps Problems from branching 10202009 12 Pipelining Example step step step Instruction 3 1 2 3 2 step step step a step Instruction 2 1 2 3 4 E step step step step Instructlonl 1 2 3 4 m rm 1 h h h 1 2 3 4 5 6 Time 10202009 13 i Branch Problem Solutions Separate pipelines for both possibilities Probabilistic approach Requiring the following instruction to not be dependent on the branch Instruction Reordering superscalar processing 10202009 14 Multiple Parallel Execution Units Different instructions have different numbers of steps in their cycle Differences in each step Each execution unit is optimized for one general type of instruction Multiple execution units permit simultaneous execution of several instructions 10202009 15 Superscalar Processing Process more than one instruction per clock cycle Separate fetch and execute cycles as much as possible Buffers for fetch and decode phases Parallel execution units 10202009 16 Superscalar CPU Block Diagram Bus interface unit memory management unit K I Instruction 39 unit Cache memory and l Integer processing units General purpose 10202009 registers E Load Floating store poinr unit F39Oating processrng point unts l registers Completion or retire unit 17 Scalar vs Superscalar Processing Instruction 1 fetch decode execute Write back Instruction 2 fetch decode execute WHtE back Instruction3 fetch decode execute Wr39te39 back Instruction4 fetch decode execute Wr39te39 back aScalar write Instruchon 1 fetch decode execute back ere Instruchon 2 fetch decode execute back write Instrucbon 3 fetch decode execute back whte Instruchon 4 fetch decode execute back b8uperscalar Clockpulsesf 1 1 1 1 T T T 10202009 18 Superscalar Issues Outof order processing dependencies hazards Data dependencies Branch flow dependencies and speculative execution Parallel speculative execution or branch prediction Branch History Table Register access conflicts Rename or logical registers 10202009 19 Memory Enhancements Memory is slow compared to CPU processing speeds 2Ghz CPU 1 cycle in 12 of a billionth of a second 70ns DRAM 1 access in 70 millionth of a second Methods to improvement memory accesses Wide Path Memory Access Retrieve multiple bytes instead of 1 byte at a time Memory Interleaving Partition memory into subsections each with its own address register and data register Cache Memory 10202009 20 Memory Interleaving O 1 2 3 g 4 5 6 7 gt 8 E 9 E 10 I E 11 ma m address bus I data bus I I 10202009 21 CPU Cache memow Cache Memory Blocks 8 or 16 bytes Bus Memow Tags pointer to location in main memory Cache controller hardware that checks tags Cache Line Unit of transfer between storage and cache memory Hit Ratio ratio of hits out of total requests Synchronizing cache and memory Write through Write back 10202009 22 StepbyStep Use of Cache CPU 1 Every memory request goes to the cache controller 10202009 cache 2334 controller J 4 2 which checks the request against each 1032 tag In this illustration each line contains 4 bytes starting with the 2332 tag address tags data 3 If there is a hit the cache looation is used instead of memory 23 StepbyStep Use of Cache CPU 1 m cache quot7 Controller I 4 tin this case a miss requires the cache controller to 032 select a line for repiacement from memory 2332 5 after which the new line in A p memory cache is as treated befcre 4m 1 3700 3 V tags data 10202009 24 Performance Advantages Hit ratios of 90 common 50 improved execution speed Locality of reference is why caching works Most memory references confined to small region of memory at any given time Wellwritten program in small loop procedure or function Data likely in array Variables stored together 10202009 25 Twolevel Caches Why do the sizes of the caches have to be different CPU 10202009 Level 39 cache L1 Level 39 cache L2 V Memow 26 Modern CPU Block Diagram Cache memory and l memory management unit A u l J Branch Instruction 39 u Processmg unit Floating unit nteger Load point 39 store Dr fzss39 g General unit Floating processmg purpose point units registers l registers Completion or retire unit 27 10202009 Multiprocessing Reasons Increase the processing power of a system Parallel processing Multiprocessor system Tightly coupled Multicore processors when CPUs are on a single integrated circuit 10202009 28 Multiprocessor Systems Identical access to programs data shared memory IO etc Easily extends multitasking and redundant program execution Two ways to configure Masterslave multiprocessing Symmetrical multiprocessing SMP 10202009 29 Typical Multiprocessing System V Configuration CPU CPU 1 2 3 I I I System bus HostPCI Memory bridge I PCI bus lO Other lO controller controllers Disks 10202009 30 MasterSlave Multiprocessing Master CPU Manages the system Controls all resources and scheduling Assigns tasks to slave CPUs Advantages Simplicity Protection of system and data Disadvantages Master CPU becomes a bottleneck Reliability issues if master CPU fails entire system fails 10202009 31 Symmetrical Multiprocessing Each CPU has equal access to resources Each CPU determines what to run using a standard algorithm Disadvantages Resource conflicts memory io etc Complex implementation Advantages High reliability Fault tolerant support is straightforward Balanced workload 10202009 32


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