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# FUNDAMNTL VLSI CHIP DESI CSCE 613

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This 30 page Class Notes was uploaded by Trace Mante MD on Monday October 26, 2015. The Class Notes belongs to CSCE 613 at University of South Carolina - Columbia taught by Staff in Fall. Since its upload, it has received 38 views. For similar materials see /class/229594/csce-613-university-of-south-carolina-columbia in Computer Science and Engineering at University of South Carolina - Columbia.

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5 UNIVERSITY 1F SOUTH OLINA CSCE 613 Week 6 Fall 2005 CMOS VLSI Design Introduction to CMOS Wire Adaptedextended by James P Davis PhD Dept of Computer Science amp Engineering University of South Carolina Jan M Rabaey Anantha Chandrakasan Borivoje Nikolic Topics Week 6 El Interconnect between MOS transistor structures the wire in terms of behavior function and structure materials from Rabaey et al Coverage from Rabaey et al Chapter 4 41 432 pp 136 148 433 441 445 pp 148 169 Examples from GM text the progression of modeling results for the 25 micron CMOS process D Capacitance revisited modeling and assumptions for the wire this is a review reformulation and extension of notes presented earlier from Weste et al D Resistance revisited modeling and assumptions for the wire this is a review reformulation and extension of notes presented earlier from Weste et al We also consider effects of switching frequency D Inductance on the wire which we consider at large wire sizes with low resistance and high switching frequencies 2 Digilaklnlegrat Introduction to The Wire D Scaling ofinterconnect versus devices a As wa scala cMos oawcas and man a ans Mpalasmcs on ma wuras oacomas mora pronouncao pamcularly mscalao mums runmno at l monarspaaos u Wuras scalmo allams nmlnata m araas ol spaan powar consumpuon rallaolmy lnolsa Immnnl u Laroarolaslzas axacarhatama proolam as schematlcs lma lanoms gal lonoar B Effect of parasitics on CMDS circuits u lucraasa opaoauon oalaysano oacraasa translstl lr panormanca u Allan on anaroy olsslpauon x powar olsmomlonmrouonounna clrcn u craata aoomonalsou as lnolsa D Basic wire modeling abstraction only usa a law oommam paramalals a Each wlra m ous natwork connacls trans mmarlslquot to racawarlsj ma a sham olwua saomams w lanom ano oaomalry transmmevs mews physical lama me reel 1 3 l Haw Interconnect Impact on Chip Comma may versus 0 lo owes processes mm D Geometry Layerlng Mel dl elemee lrl geomevy SOBCeraWPE RalMu lo a MnoeloYaelsoflmemonnecl WE a so an We sllll have slngle olmslon ano poly layers m Wehavemarly more layersof all sanoyyle n een mm layers of lnsolalor ll mm more aggresslve am at slructurlrl 5 ll length that makeswlre mooellng a challenge materlals are part of me solollon z a moral lmegrated rmlls quot new l Nature of Interconnect Real Data Here we are comparing the relative number of nets required for local versus global interconnect for Pentium class of CMOS devices with 30 40M transistors as a function of actual line length Technology scaling is facilitating smaller wire size while increases in die size facilitate longer line lengths the source of greater parasitic impact Local Interconnect chnology No of nets Log Scale Source Intel 1000 Length u 5 100000 Digital Integrated Circuits Devices Wire Modeling1 I El Parasitic wire models The lumped parameter modeling of resistive capacitive and inductive effects on interconnect are distributed over entire wire length This is necessary when wire length becomes much greater than its line Lwire gtgt Wwire39 We have effects due to the relationship of the wire to ground and also between wires at different layers in the circuit geometry We end up with coupling effects in the layout that must be managed that are not present in schematic model These are complex models that fortunately we can simplify under certain conditions see next slide j Capacitanceonly model Digital Integrated Circuits DeVICes l Wire Modeling2 T l lI39 l Allinclusive RLC model i l l l 4 Capacitanceonly model Digital Integrated Circuits2nd El Parasitic wire model simplification Induction can be ignored if the wire resistance is large Rwire gtgt L for longeanes A capacitance only model can be used IF 1 wires are relatively short 2 wire cross section Wwire x H is large OR 3 we use a low resistivity interconnect material A simplified capacitance model consisting only of wiretoground capacitance ignoring interwire effects can be used IF 1 inter wire separation is large OR 2 wires run together in material for short distance The specific values for when we use these model assumptions are to be derived by authors in the text wue wue Devices Capacitance of Wire Interconnect El Capacitance wire model Fanout Shnp ed Modd Digital Integrated Circuits2nd simplification redux In the figure we see how we incorporate the capacitance wire assumption into the schematic view We have a transmitter an inverter with its device capacitances identified connected to an output line that drives a fanout receiver load consisting of the transistors of another inverter We can model this as the inverter transmitter or driver coupled to a load consisting of a capacitance CL with voltages Vin and Vout There is a relationship between CL Cwire and the load values on the fanout that is to be developed Devices Capacitance the Parallel Plate Model a Rectangular wire geometry We can adopt a parallelplate capacitor odel IF wire width is much greaterthan dielectric thickness WWe gtgt td ii Electiica Hield lines To minimize the effect of resistance as i K we scale the wire we must keep cross I I pieieciuc seetion WWlfe X Hwire large quotwvw Smaller line widths WWW allow more dense packing of circuits onto geometry 8 at crosspurposes cw AWL The WMe HW ratio as it drops tdi below unity we must incorporate the fringing component of the capacitance model along with the parallelplate component to obtain parameter Owe S S Capacitance is proportional to overlap CW S SE SL between conductors inversely proportional to their separation Miniw mm m rm lM ll I l ll i ll y iii ll ll Dig l lfieiglal ed Wilts Dgl PES Capacitance Fringing Field Model in Cylindrical wire geometry We simplify the fringing field geometry by assuming we have a cylindrical wire of diameter equal to wire thickness HMe compare with figure for parallel plate geometry 2 We assume parameter w the per unit length wire width as follows w W H2 The perunitIength parameter here is given as a function of total lumpedwire width and height See footnote p 139 b ERRA TA Note the revised formula equ 42 p 141 amp modify in teth Wedx ed ware Cppcfrmge 1 2 H1 m 0g Id Digital integrated Circuits d 10 DeVLCES Typical Permittiwty Values The values shown here are normalized relative to permittivity of free space which is 80 8854 X 1072 Fm Material gr Free space 1 gust wad H Aerogels N15 PillZingndmus Polyimides organic 34 39 Insulator most prominently in use today Digital Integrated 3 le Silicon dioxide SiO Glassepoxy PC board 5 Silicon Nitride Si3N4 75 Alumina package 95 Silicon 117 11 Devipes Capacitance Fringing versus Parallel Plate CI The Modeling Continuum Plotting capacitance against the WH ratio with Ifferent values for the ratio between HAW 2 I Capacitance pFcm 0 9 x m l l l llll 0 1 l 39om Bakoglu89 Digitallritegraled irclmsm 3901 02 04 06 Looking at cwire as a function of Witt derived from Wmre Hm ratio For larger values of Wwire Hwire the cwire approaches that of Opp For smaller Wwire Hwire values less than 15 closerto unity C becomes more dominant component Fringing capacitance can increase overall cwire by gt 10X for small Wwire values fringe converges to a constant value 2 1 pFcm if Wwire lt tdi ie capacitance is no longer a function of interconnect line width Devices The Interwire Capacitance Model Digilal lrlegralsd angursw D The V re microstripeline versus the wire interconnect hierarchy With only 12 layers of metal interconnect on top of the poly and diffusion we can assume the additive capacitance model for parallel plate and fringe relative to ground Actual CMOS processes have many more layers densely packed Each wire is coupled to ground substrate and to neighboring wires on same and adjacent layers These floating capacitances have parallel plate and fringe aspects relative to time varying voltage levels of these other wire signal paths a source of crosstalk noise Dgyipes Impact of Interwire Capacitance l l l 1 pm field oxide 1 m metal 4 1pm sin cap layer DIIIIIIEI w l Capacitance pFcm n l l Design rule pm 39om Bakoglu 89 DlJllal lnledialed Circuits2nd Cfnnge VS pp39 14 i The bottom line Interwire capacitances become dominant in multilayer interconnect structures Effect is more pronounced at higher layers further away from the substrate Contribution of CWewe for parallel wires routed above a ground plane with constant dielectric tm and wire thickness H while other dimensions W wire erev Tme scaled As Wwe Hme lt 175 interwire effect dominates as seen in the plot 0 Capacitance vs Line width The figure in the plot legend shows the configuration assumption for this conclusion Compare this result with slide 12 for Devices Wiring Capacitances 025 pm for examples Table rows are capacitor s top plate fif zrggtllggf 3 6 its Use the Field values for C terms 39 J when placing wires over thick field opp valufs quot7 Wiper OW39 mum u on Chme shaded row transistors l I Tlteld39 Active Poly l l A12 A13 A14 l39 88 39 Process supports 1 layer Poly and 5 layers Metal First 4 metal layers me H and t But 5 quot layer has H 6 Hquot and Ems gt 5m Digital lnte grated Circuits2m 15 Devices Wire Resistance Model CI The bottom line Resistance of a wire 0 wire length and 1 cc to cross section area H x W Assume same rectangular geometry as for capacitance model The resistivity p ofthe wire material expressed in Ohmm is a constant The wire thickness H is also a constant for a given technology and can be expressed in terms of sheet resistancequot expressed in Ohmsper squarequot Result is that R of a square wire segment is independent of its absolute size R L 39 f Crosssection area L Sheet Resistance H I R0 4 This should be R17 4 R1 E R2 w 16 Digital Integrated Circuitsquotd Devices Interconnect Resistance El Mm 39 I copper Cu I Gold mu umlnum Al Tungstcn W El Dlgltel lhleael t lmt iw Resistivity p Aluminum most often used for Metal interconnect material low cost and process compatibility Copper has better resistivity constant however and is finding its way into more prominent use in newer processes Sheet resistance RD For the 025 micron process we have avg values for interconnect materials This shows use of Diffusion Poly and Metal lines as wires Note use of a Silicide compound enables processing of Diff and Poly layers at high temp to increase region s conductivity Devices Digllell Murat Interconnect the Polycide Gate Gale conducting region Silicide PolySilicon Sioz Silicides WSi 2TiSi2 PtSiz and TaSi El Design Objective Want to be able to use Poly and Diffusion materials as better conductors of current Reduce resistance of conducting materials Poly and Diffusion layers Add a silicon compound layer on the gate Poly source and drain Diffusion regions Conductivity 810 times better than Poly alone Increases conductivity by reducing RU Devices l Digital Integrated Circuits d Resistance Skin Effect El Resistance at veryhigh switching frequencies in wider wires R is no longer linear but is frequency dependent GHz range eg Pentium clock frequency Current flows nearer to surface of conducting wire drops off beyond depth 6 Equ 46 Skin depth 6 depth at which current falls off to a value of e397 of its nominal value Al at 1 GHz frequency 6 26 microns El Skin effect approximation Assume uniform current flow in outer shellquot of rectangular wire with thickness of 6 V re cross section HxVV is 2Wx H x 6 Calculating rie R per unit length Equ 47 CI Implications Find the frequency fs where 539 12 max W H If fgt fs then we ll have increased resistance Eq 48 Clockiqg wide wires amp high freq gt skin r Device Digitallntegrated Circuitszquotd Minimizing Resistance El Employ selective Technology ScaHng Scale L and W leave H and tdi alone as with capacitance Use Better Interconnect Materials D Reduces average wirelength eg Copper Silicides U More Interconnect Layers Reduces average wirelength But add more wiring layers which increases capacitance effects design tradeoff here However to minimize contact resistance we want to keep signal wires on a single layer and avoid excessive contacts and vias Devices Example Intel 025 micron Process 5 metal layers TiAl CuTiTiN Polysilicon dielectric WWWL isolation Polysilicon Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 lLaycr pitch thickness and aspect ratio 067 064 064 093 093 160 256 K lit in DigitalIntegrated imuitsm As we get to higher layers of metalzation we see Wand H get much larger This starts to change the model for resistance and introduces inductance in designs operating at higher switching frequencies GHz range 040 025 048 15 090 19 090 19 1 3 17 390 1539 117nm 21 Devices Wire Inductance Model M6 M5 M4 M3 M2 M1 poly 1Dl gital Integratedteincult mr Inductance effects when Low resistive materials and wider wires at higher metal layers Very high frequency switching El Analysis method Rather than compute wire inductance from geometry use a perunitIength relation between capacitance c amp inductance 1 Eq 410 Assume approximate uniformity in surrounding insulator material Insulator material properties define the relationship permittivity permeability El Line impedance Z Inductance and resistance components Want the frequency at which inductance component of Z becomes equal in value to resistive component perunitIength 22 CI Global intermodule Intercell Intracell Devices Continuum of Wire Models 1 Ideal Wire Wire Model 2 Lumped C 3 Lumped 4 Distributed 5 Losslylless Type Dominant RC rc ne per Transmission Line unI ength Model rSirnpieiineWitn rCirCuitparaSitiCS rCirCuitparaSitiCS rDistroutedm Digmbntedyig properties noparasitics iurnpedatnode Wire modei memodei distriouted aiong Same wire 9 Wire iengtn are aiong Wire iengtn 759 moves 59 moves present at aii Wire lumped Wne C Reduce transien through Wire Via tnrougn Wire a W595i r wire benavi diffusioanci 4 i8 wave 5 to 1 to 5 333635095 PC net VVOitage at node i Lossiess no Us Eirnore soived via paniai Loggy effects Lump as Singie C deiay ror RC tree din eqn Use is order FX eDifftJSion eou when Model rEariy in the wn vaiues Use in made Wnen goai is to a When Switching 39 are Srnaii Wrt C Is Used esign process interconnect minimize iong iine speeds oecorne Wnen rocusing o h We mg nen slutan deiav and signai r t Wire rnateriai properties and a We Witching tne i degradation Witn ioW R but behavior or tne new reg distrioution Appmmated W inductance starts transistors U59 m Wag network nging poredde to do inate deiay rModei gate Wires no inane Den rWire stiii iias r Lurn ed RC eDiStr outed rc is VLOSsiess userui Mode reai properties or eduai voitage assurnption compieX and nag or CB Wires interconnect into present aiong aii inaccurate for no ciogedrorm eq account Wire segrnents iong Wires Scintion 0W 0 ommp meg rWire doesn t number of N approximations a Simpiines down introduce deiav 599mm 9W5 Generaii use o distriouted rc rNot usefui for 99 tne R Ciadder iine mode4 anaiyzing vXX con guration L Diggiai integrated Circuits Devices The Lumped Model Dominant C in Model axioms Vout Single parasitic component is dominant in that R is small relative to C iaige aieabetteimateiiais Lump capacitance into a single circuit element in Model topology Driver is modeled as voltage source with source resistance Load is modeled as capacitor at the end of the wire in Differential equation Kirchoff s current equation replacing for capacitance and Ohm s law components Assuming step input we know form of transient LeiRC for the network time constant use Kircnufi s Curr ni equation at tne node to form tne differential equation Var VtJPdnwr cimwed Wood 0 Rioer Annyingaquotsiep innui Iiiit iiuiii iii ii iiii V 11311111111111 mped Reducing source Rm resistance is a maior design concern See exampie 4 5 p752 24 Diqiiai integrated Circuits2nd Devices The Lumped RC Model El Model axioms Lump total wire resistance of Appyin Stewhmquot R2 each wire segment into single R 1 3 R1 1 C2 4 between nodes in network 0 quotquotquotquotquotquotquotquotquotquotquot 39 W L 34 I Lump total capacitance into 1 R3 1 smgle node capaCItor to GND C Single differential equ single RC 3 T w i time constant for solution C Shared path resistance I l D MOdel top0ogy l T RC tree 1 single input node 2 Ci between node i and GND 3 it Zigzag e pathv gt n mpamrs 4m no resistive IOOPS Unique resistive path from source node s to any node i N El Elmore delay calculation TD Z CkRzk Path resistance R k 1 Shared path resistance s to k i Elmore delay at node i Equ 413 Digital Integrated Circuits2nd 25 Devices Lumped RC Model Elmore Delay Consider the simple nonbranched RC ladder network a good approximation of an RC wire Using 413 we reach a simpli cation where the sharedpath resistance is replaced by the path resistance This is summed with capacitance at each node over the wire segments A wire of length L is partitioned into N identical segments each with length LN Capacitance cLN Resistance rLN these are perunitlength for each segment Using Elmore we compute the dominant time constant of the wire N rm Z CARik Vin R1 1 R2 2 Ri1 R RN N k l VN C1 C2 Ci II CiI CN IIH This reformulation of Equ 413 into 414 p 154 allows the RC tree to be represented approximatey by the RC ladder network N i N Time constant 239 can be derived for any node i in the network TDN 2 C52 Rj ZCiRli ID C1R1 C2R1R2 CRR2R i1 i1 i1 tiltsnd 26 Devices Digital Integrated The Elmore Delay Model RC Chain V Vi r L Vii 1 W31 wmxi w WWW MAT i i i i W out Consider the simple nonbranched RC ladder network a good approximation of an RC wire Using 413 we reach A simpli cation where the sharedpath resistance is replaced by the path resistance A wire of length L is partitioned into N identical segments each with length LN Capacitance cLN Resistance rLN these are perunitlength for each segment Using Elmore we compute the dominant time constant of the wire X Vin R1 1 R2 2 Ri 1 i 1 Ri RN N TD 2 111 VN A C11 C21 C1511 Ci CNl TDN ciiRj CiR i1 jl i1 9 Digital Integrated Ci rcuitszm Devices Lumped RC Model Dominant Time Constant Assumei Wire modeled by N equallength segments quota 2 N N 1 i N 1 E 2 TDN rc2rc Nrc rel We can compute the dominant time constant 7 RC of the wire by summing over N segments extracting the Length components UN for both r and c perunit length multiplied by the series expansion Reformuating terms and inserting R rL and C 0L as total lumged R and C of the wire For large values of N the N12N goes to 12 RCrcL2 CW 7 7 As N grows large the lumped RC model approaches that of the distributed rc line model with conclusions 1 Delay of a wire is quadratic function of wire length L 80 doubling wire length quadruples line delay 2 Delay predicted using lumped RC model is approximately half as accurate in terms of delay calculation as the distributed rc line model 3 The Elmore delay calculation only considers the dominant time constant ignoring the others that would be associated with other RC terms so the delay associated with the dominant RC is crude depending on wire length o Digital integrated Qireuitszm 28 Devices Lumped RC Model Plugging It In We can now relate the wire model to the transistor model as follows I 7ver m R 1 R2 2 Ri1 i l Ki 1 1 RN N I I 39 quotquotquot39quotllnt39mlliiiquothint quotquot quot i39 VN 1 39 I i 011 C21 I x I i 1 Model the transistors as linearmode switch 2 ie voltage source in series with its onresistance Determining the propagation delay of the wire then involves the analysis of the RC ladder network 2003 James P Davis Univ of 50 Digital Integrated QifCLiiiSzn 29 Devices Distributed rc Model Lumped RC model is pessimistic in its assumption so we increase the accuracy by distributing the resistance and capacitance throughout wire segments r and c de ned perunitlength A wire of length L is partitioned into N identical segments each with length LN Capacitance cLN Resistance rLN these are perunitlength for each segment Using Elmore we compute the dominant time constant of the wire The voltage at a given node can be solved using partial differential equations Equ 417gt Equ 418 Digital integrated CircuitsZHd 30 Devices By reducing length A L asymptotically to zero we get DWUSIOU equation Qigtai integrated Quotaser The Distributed RCIine 7 is voitage at a panmuiarbmnmmgmewm and x is distance mm the signai source mm mm n Wayne R Vin W an 1 line Netw 3575 represents the distributed in Consisting of me RC iedde om DeON rAL We end up making approximation and return to Lumped c ll Devices Stepresponse of RC Wire Model B Behaviorassumption w d t u Wmva Single differentia time constant for Plot meaning Response of the input step functio 15 Basic 0 l0 reach the driven lave Did ai inteqmtedmcunsm 2 25 3 we may point from the graph shorter lines have better ones Longer lines lake longer 9 1r van a W me the line affects low lung ill k s l r 1 AL asymptotically to zero Lump total capacitance into single node capacitor to GND equ single RC solution rcwire to an n o gt 1 V is voltage at a particular point along the wire and X is distance point on the wire We see the signa the unit step resp a delay of or he signastrength lh re transitioning logic 0 lo 1 from the signal source to this Irise times of onse in the distributed rc network given different line lengths L Reduction in Distributed rc Model quot Formulate this x El Behavior assumption 1 A A x V0 We have rcIine of length L not inductance L driven by voltage source with series resistance R5 representing the driving gate Like thisquot Apply Elmore s formula to obtain N approximation of tP the total 39 propagation delay from the time 5 39 WV 7 constant terms for the network As before RW fl and CW 0L I g 39 again L is wire length quotquotquotquotquotquotquotquotquotquotquotquotquotquot 39 El Delay calculation To get this R ti Ti RSCW 12quot1lii H 3 Solve for time constant CD in terms we of Elmore tree derivation of resistivecapacitive wire p 155 The delay introduced by wire resistance becomes dominant when RWCW2 2 RSCW or when L 2 ZRSr ii 369R5CW038wa 33 Digita Integrated Circuitst Devices i Distributed rc Line Heuristics El rc delays should only be considered when t gtgt t of the drivin ate Under different conditions we can pRC pgate g 9 reduce the complexity of the distributed rc model to either the Lumped C or gtgt t 038rc Lumped RC modes cm pgate The factor that governs this model selection RC delay becomes dominant for interconnect is the relationship between propagation wires longer than Lcrit Therefore we use delays of the driving gates and that of the the Lumped RC model quotne tse f39 El rc delays should only be considered However we can look at the line length to Whenthe 39 fall tlme at thellne give us some guidance de ned bye input is smaller than RC the rise fall critical length Lem time of the ne trise lt RC El when not met the change in the signal is slower than the propagation delay of the wire Therefore we use Lumped C model in this case 2003 James P Davis Univ of 80 MJ39rWi PSU 2000 34 igital Integrated Circuitst Devices Analysis Examples Rabaey text El Example 41 p 144 Capacitance of metal wire Factor of 2x for Cfringe calculation due to both sides of wire cylinder fringing Uses Table 42 p 143 and Table 4 3 p 144 El Example 42 pp 146147 Computing total resistance from Rn Comparing resistance of metal vs Poly lines El Examples 43 p 148 Resistive skin effect analysis Plotting skin effect to determine at what line widths it becomes noticeable El Example 44 p 150 Inductance of metal wires of different widths Calculate cpp cm ge also using 2x factor for cmnge from Ex 41 Identifying at what operating frequency and given wire widths we start to see inductance El Example 45 p 152 Lumped capacitance of wire using Kirchoff s law Ohm s law RC time constant El Examples 46 p 154 amp 47 p 155 Elmore calculation of RCinduced wire delay of treestructured network El Examples 48 49 Distributed rc line calculations that reduce to Lumped RC Elmore and Lumped C Digital Integrated Circuits d 35 Device l Summary CI The continuum of wire modeling We looked at different models and how they address the issue of propagation delay through the interconnect network We used various techniques based on formulatin the RC time constant given a step input transition from logic to logic 1 from the gate driver of the line and load on the other end El Modeling continuum 1 wire model 2 lumped parameter models Calone RC 3 distributed rc line model 4 transmission line model lossless lossy These models progress from simple to complex their use depending on the effects being studied and the accuracy required Different automated tools may support some set of these assumptions in the analysis capabilities provided to the designer El Examples from GM text the progression of modeling results for the 25 micron CMOS process 1 Digitallntegrated Circuits2quot D vices CSCE 613 Week 6 Fall 2005 CMOS VLSI Design Introduction to CMOS Wire AdaptedExtended by James F39 Davis Ph D Dept of Cumputer Sclence amp Engineering University of South Caruilrla Jan M Rabaey Anantha Chandraxasan Eunyuie Nikuil lime D Interconnect between MOS transistor sthctures the wire in terms of behavior function and structure materials from Rabaey et a covera efrom Raba etalchaptier4 4l 452Pp1361AE453 441 45pp14amp as Examples from cm text the progression of modeling results for the 5 micron cMos process a pacltance revisited modeling and assumptions forthe wire this is a review reformulation and extension of notes presented earlierfrom Weste et al a Resistance revisited modeling and assumptions forthe wire this is a review reformulation and extension of notes presented earlierfrom Weste e al We also considereffects of switching frequency a inductance on thewlre whichwe considerat largewlre sizes with low resistance and high switching frequencies 2 Introduction to The Wire D Scaling of interconnect versus devices u interconnect the dfects ofparasmcs on the Wires ecomes more pronounced particularly in scaled circuits ninning at higher speeds u Wires sc cts dominate in areas of I 3 aling efte M speed power consumption rellablll lnoise immunityl WW quotWquot a Larger die sizes exacerbatethe problem as schematics line len s get longer B Effect of parasitics on CM OS circuits a increase propagation delays and decrease transistorpertormance u Affect on energy dissipation a power l i distribution tiiroughoutthe circuit ii u c eatie addi nalsourc ofnoise I bstractlon J 1 a Basic wire mode 39ng a 39 l t n We only use a few dominant parameters 39 D Each Wll39e In bus network connects transmitterlsl to receiverlsl viaa chain ph39ysic al ofWire segments w length and geometry 3 PW Interconnect Impact on Chip Comparing 035 versus 01 CMOS processes noting geometry specifically pertaining to their differences in number of layers of interconnect Geometry Layering As we scale processes we also add more process layers to the circuit geometry 2m Dlgllal lnlegialed Clmulls y 0 new We still have single diffusion and poly layers We have many more layers of metal sandwiched between layers of insulator It is this more aggressive geometry structur39ng coupled with smaller wire feature size versus length that makes wire modeling a challenge New materials are part of the solution my mnm up a a m we I Devlces Nature of Interconnect Real Data 1 h MA g 39 39 39 39 size While increases in die size facilitate longer line lengths the source of greater paras tic impact No of nets Log Scale t Local Inte rconnect sLocal sTechnology Global 39 sGlo al sDie Source Intel 3 10 100 tallvlceerqlsli9wsm 1 000 Length my 5 10 000 100 000 DEWS Wire i I W l W l l Allinclusive RLC model I l I Capacitanceonly model Dlgllal lnlegtaled Clrcmlslv Modeling1 Parasitic Wire models The lumped parameter modeling of resistive capacitive and inductive effects on interconnect are distributed over entire wire length This is necessary when wire length becomes much greater than its line width L gtgt WW ere we ects due to the We hav e relationship of the wire to ground and also between wires at different layers in the circuit geometry We end up with coupling effects in the layout that must be managed that are not present in schematic model These are complex models that fortunately we can simplify under certain conditions see next slide Devices Wire Modeling2 j I l Parasitic Wire model simplification W Induction can be ignored if the wire resistance is large RNe gtgt Lwe for longer lines A capacitance only model can be 1 used IF 1wires are relatively short W 2 wire cross section Wvwe x Hme is large OR 3 we use a low I resistivity interconnect material A simplified capacitance model consisting only of wiretoground capacitance ignoring interwire 1 effects can be used IF 1 inter quot 39 tion is large OR 2 wire separa If I Allinclusive RLC model Wires run together in material for short distance The specific values for when we use these model assumptions are to be Capacitanceonly model derived by authors in the text 2m 7 DJQllal lnlegialed Clmurls Devices Capacitance of Wire Interconnect l Capacitance Wire model simplification redux In the gure we see how we incorporate the capacitance wire assumption into the schematic view We have a transmitter an inverter with its device 4m M3 capacitances identified connected Maggi E to an output line that drives a fanout receiver load consisting of the transistors of another inverter We can model this as the inverter transmitter or driver coupled to a load consisting of a capacitance CL with voltages VW and Vom There is a relationship between CL Owe and the load values on the fanout that is to be developed Fannut Simpli ed Model C9 Digital lnlagralgd Crawls Devices Capacitance the Parallel Plate Model l Rectangular Wire geometry We can adopt a parallelplate capacitor model F wire width is much greater than dielectric thickness WWe gtgt td Electilcallleld lines To minimize the effect of resistance as K we scale the wire we must keep cross Balearic section WW X lere large Smaller line widths WN allow more dense packing of circuits onto geometry at crosspurposes c WL The WMe Hme ratio as it drops below unity we must incorporate the fringing component of the capacitance model along with the parallelplate component to obtain parameter Cwe S Capacitance is proportional to over1ap between conductors Inverser proportional to their separation Cu vie nl lluw 1 i u Digilal lnlegiated clmurlsw 9 Delices Capacitance Flinging Field Model I Cyhndncalwwe geumelvy We sxmpmvm Eeame v bv assummg we have a WeassumEPavamet unNerrgM wwe W n wvv7m mp2 Pavametevh vexsgwenasa mndmn aHmal mmpeuwe mm andhe ghl Seemmnmem 139 mm 7 Nate the mm mm 9w 2 mm madlym my 111m 11 r n aws Typical Permittivlty Values me WWW Mm mm mm mm MWEW m M mm mm 1llml lzl mammsmme m mmmlg nuns Capacitance Fringing versus Parallel Plate 1 The MudehngCummuum mmmmm amm WMaou m mm at cm as a mndmn m mmmmmmaemnm mm mm m Mm MW 7 7 yam m largev values m Wm mm the cm amalgamth mew mmmmes lasele um cm damnam Fm muev MW lesslham 5 c became Mme campanem vagmg capsmanna can mease avemH cm by gt1DXVavsmaHWm Wmme mm mmva m mevmnned mg mm 2 my Wng cm The Interwire Capacitanne Model I THEWHE mmmsmpehne vevsus thewwemtevcunnectmevavchy W mm mm m H mm capsmanna my m i W mg and We mm m y Emund Ammo Pvacesseshave manvmme avevs dense vpa ked E 1 ya mums m bmssta k mm mm cm w my Impact of Interwire Capacitance 1 The bunu h mevrvwe capacnancesbecame damnam m mummy mevcanned stvuduves mm s we Pvanaunced at my avevs mm 3mm We mama mnstam mewemnc an and vwemdmess Hm Wm e my mmensmns WW mam MmUkHunlt175HMEYVWVEE39EH mmgs asseen m the mm m mmmpm h mg gure mme pm wegenw shav sthe mnugmmn assummmn mums mncmsx n quotw WWW Campavems resuh Wm shde x1 2 m cm VS CW mraunwmew quot r Wiring Capacitances 025 pm for examples mwm r39 1 Wm mm wwmmw tsquot 5 beew The wst The Wye tmcknes see m Wire Resistance Made a The buttum hne Resmance m a we u we Myth and Hum cuss semnn avea H XW Assumesame red squsve Resuu 5013 R sue o my mm cm angmav genm em as my eapsensnee mnde m a squsve wvese 5 H s 5 am a cement any a gwen eemmmgvx arm can ems m shee vesw anm ewvessed m Ohmsrpevr Emem s mdependem m Ms abmme t heat R esxstance s R m R2 we Interconnect Resistance mavwmm mm Magma em mmmlwnyamwmermsm w u Reswswnyp Nummum mns1 onequot used vm Me a mevmnned malena nw ms and pmeess campaumhw cuppemssmenesmw mnssm hnmveh and s mung a mu e memmem use sses anhe n 25 mmmn Pmcess we have avg vames my mevmnned matena s p andMelaHmesaswves Nmeusema Smc s compound ensmespmees mngmand Pn v avevsawgmemp m maease vegmn s ennuuawnv We Interconnect the Polycide Gate Sdlmdzx wsu I xgPthgand an u Deswgn Ob acme Wanna be see m use my and Dmusmn malena s ss bane mndudnvs m ewen dune vesmance m mndudmg matena PHW and Dmusmn avevs Addasm mpnunmavev on me gale PnW mums and sham Dmusmn vegmns Cnnmmwly 2710 am hem man Pwly m nthWY N mug messes candudw v w veducmg R Il R snamngevhneanbm svkuencvdependem Mums e g yemmm cmck quotmew AA m1Gsz2querv3v l 25 Humans a Skin 2mm zpprnxim n suns ummm cuvvem avwn my sheH m venangu av vwe mmmmss m 1 Wwe cmss sewanmmnwmu ca m ahng VUe RPemnMengm m n 39 inns qu mm cvqu u EmplnyselediveTechnnlngy Sc Ii W Weave H and m We as W capsmaan u Llse ellerlnlercnnnetl Materials vevage vweJenglh zyels dmavewnng avevs wmch messes caps2n I22 2v a 5 W mmsw39 7 Example Intel 0 25 micron Process Beth hammyersametmmn m e Wand qutmuchhirqer 7m a 5 an mm he madelfwresrsmm m mmmwma m mummy mmmw Wm on may 5 m m ay s mu 7 Cumw Pmysmcun maxedquot l nmwh h mmsm y mu Wire Inductance Model in Inductance effects when M6 GI Low resistive materials and wider wires w at higher metal layers M5 Very high frequency switching in Analysis method M4 Rather than compute wire inductance in emodm from geometry use a perunitlength M3 relation between capacitance c amp 39 inductance 1 Eq 410 l a i I 1 ii ii M2 M1 quotWmquot Assume apprOXImate uniformity In I I I minun poly surrounding insulator matenal lbsan V Insulator material properties define the T i relationship permittivity permeability WNW in Line impedance Z Mug Inductance and resistance components Want the frequency at which inductance Mu component of Z becomes equal in value l to resistive component perunitlength l Digital lrilegieled circuits2nd 22 Devices Continuum of Wire Models med 5 Losslylless WireModel 1ldealWire 2Lumped C 3Lumped Type Do RC minant me per Transmission unit length Line Model rSlmple line Witn rleCult parasitics rleCult parasitics Distributed 0 Distributed ic Properties no parasitics distributed along iurnpe at no es we modei Wire modei Same Wage Wire engt are along ere lengtn is My mom Sway mom present at a l Wlfe lumped Wile C e educe transient hrough Wire Via tnrougn we as oggicautgrsvgpe Wlfe be aleftO dirruSiongq 4 i8 Wave c to itoc RC network and C 5 gm eVoltage at node l eLossless n r o e Elmore eLossy r effeas tis Lump as single 0 delay for RC tree Use 15 order FX Dirrugion egu olved vla partia e u gm e when Model rEarl in tne eWheri R values Use to model eWheri oai isto eWheri sWitcning is Used design process are srna i Wrt c interconnect minimize long line spee s ecorne Wnen rocusing on When operating wnen studwig delay and signal fast Wire rnateriai properties and at We WWW tne supply degradation Witn ioW R but behavior of tne sequences distrioution Appmmaied by inductance starts transistors VUSE m mm networ Wing Reiadde to dorninate delay Model gate Wires we mm behmior Limitations of e Doesn ttake Wire sti i nas e Lumped RC Distributed m is eLossless userui Mode reai properties of e uai volta e assurn tion compieX and he for PCB Wires interconnect into resent along al inaccurate for no clogedrorm Leggy reqwed account Wire segments long Wires solution only for Orlrchlp Wires rere doesn t number of N approxnnations e Slmpllfles down introduce delay 599mm GVOWS Generally use to distriouted rc Not userui for We tne PC isdder iine model 4 analyzing vxx configuration The Lumped Model Dominant C in Model axioms out Single parasitic component is dominant in that R is small relative to C laige area beneimateiias Lump capacitance into a single circuit element We use Klrchoffs current equal on at the node to form D MOdel t p gy Inedfferemialeaualisn Driver is modeled as voltage source with source resistance Load is modeled as capacitor vw at the end of the wire in Differential equation Kirchoff s current equation replacing for capacitance and Ohm s law components Assuming step input we know Reducing source R we resistsnce is s rnsior design concern form of transient 1elRC for 5 amp9 4 5 p752 the network time constant 24 Vac WPe e cwyedd VWdt o AppWig s quotslep nput Vn Digital lnlegieled circuiislii Devices The Lumped RC Model B Model axioms Lump total wire resistance of each wire segment into single R between nodes in network Lump total capacitance into single node capacitor to GND Single differential equ single RC time constant for solution B Model topology RC tree 1 single input node 2 between nodei and GND 3 lg zit gilt c Juliana mn39nxesmt no resistive loops Unique resistive path from source node s to any node i Elmore delay calculation Tr ZR Path resistance R Shared path resistance s to k i Elmore delay at node i Equ 413 DevlCeS AppW79 a quotstep Input Sharedpalh res stance D 1 99mm qtmetgsznd Lumped RC Model Elmore Delay Consider the simple nonbranched RC ladder network a good approximation of an R C wire Using 413 we reach a simplification where the sharedpath resistance is replaced by 39 Thi i Hm 39 quot he wire segments A wire of length L is partitioned into N Identical segments each with length LN Capacitance cLN Resistance rLN these are perunit length for each segment Using Elmore we compute the dominant time constant of the wire 72 Zak A V R 1 R2 RH i lRi RN N v vv v vvv vv VN l H A m u L Y represented approximately by the RC ladder network N N Time constant 239 can be derived for any node iin the network ID 2 C2 R ZCIRH rm C1R1CZR1R9 CR1R2R i i m 26 Denlees lgltallnlegreted utlsln The Elmore Delay Model RC Chain Vi rm mi quot39u nu vi rizL rm rm V Uslng 4 13 we reach A wlre of englh L ls partlloned Into N ldenllcal segments each wrlh englh LN Capacllance cLN Res stance rLN these are perrun rengln for each segment Uslng Elmore we surname the enrnnsnl llrne constant ofth wlre RN N 39 Vanquot RH 1Ri vvv vv VN T xDN2q2RJqu i e m Demces Lumpecl RC Model Dominant Time Constant Assume Wire modeled by N equallength segments 1quot 39391 mi I U39C 2n ic rel 3 quot 39 V u 39 3 v r 7 3 quot 39 39g is gm mo extractngthe u u i U quot g p39 39 r 39 Reformulating terms and inserting R IL and C rl For large values of N the N12N goes to 12 a 1 RF rcf M T T I N I w 39 r 39 39 tine modei 1 hi Y 39lng alSoukl39 Y r i All as the distributed rc line model 3 Tquot J 39 i t quotits quot depending on wire length N 23 Devices Digital lnlegialed Circuits Lumped RC Model Plugging It In We can now relate the wire model to the transistor model as follows 2 t Mneei tne lra SlSlUrS as mame MC 2 Determining tne pinnegetinn i e wile39 Emma 21 delay nflhe Wire tnen intElves series wi i s uwesr We tne analysis nflhe RC ladder network 2003 James P Davie Uriv 05 c metal lmlsgiatetlgws 29 Deltas Distributed rc Model Lumped RC model is pessimistic in its assumption so we increase the accuracy by distributing the resistance and capacitance throughout wire segments r and c de ned perunitlength A wire of length L is partitioned into N identical segments each with length LN Capacitance cLN Resistance rLN these are perunitlength for each segment Using Elmore we compute the dominant time constant of the wire 1 L i i The 39 g g39 Equ 417gt Equ 418 Digital integrated ciieutezid 3 Devices V uul r 39s represen s the distributed rc line mnslslng n e F Cladder Nelwm be0w Ely reduc ng engm A L asymplbllca ly in zem we gel diffuslnn equallbn e an aklrig pmxlmallbn and turn 0 5 ma ell Same as Equ 415 p 155 xv l5 voltage at a pamcular bmuLalngbelwre 39 and x l5 dlstarlce from me Slgrlal source to this point on thegvire Digital lnlegialed Clmull m Devices Stepresponse of RC Wire Model in Behavior assumption We reduce the perunitlength AL asymptotically to zero Lump total capacitance into single node capacitor to GND Single differential equ single RC time constant for solution in Plot meaning Response of the rcwire to an input step function 0 gt 1 V is voltage at a particular point along the wire and x is distance from the signal source to this point on the wire longittakes forthe signsstrength We see the signal n39se times of to reach the driven level here transitioning logic 0 to 1 the unit step response in the distributed rc network given different line lengths L Dlgllal lrllegialed 3litlllsquotDI Devlbee Reduction in Distributed rc Model in Behavior assumption We have roline of length L not inductance L driven by voltage source with series resistance RS representing the driving gate Apply Elmore s formula to obtain approximation of tp the total propagation delay from the time constant terms for the network As before RW IL and GM 0L again L is wire length l Delay calculation Fermiale this Like this Solve for time constant TD in terms of Elmore tree derivation of resistivecapacitive wire p 155 The delay introduced by wire resistance becomes dominant when RWQNyZ 2 RSQN or when L 2 2RSr z in U il39t39 rr nmlm I39JHI39CRHE Digit gi ed lmllll sz a Delices Distributed rc Line Heuristics u re delays should only be considered when gtgtt ofthe dnwh ate uneeeheemmm 4K we 9 9 reduce Me consolele Dime distributed Lwedc oi lcmodeIoexhelme L gtgt it San tumoed no models cm W he rector that gmems ms modeselemon R delay hecem es deminantrer intercennect is Me ielstlonsmp between propagation wiies lenger than Lem Therefure we use delays ortne wry gates sndtnst owe the Lum pee RC meuel line itseh u re delays should only be considered However Wecanookafmemeerlgmo when the rise falmlme atthe line givemoneomamemevhedwa input is smallerthah RC the nse fall ultra19mm A7 e me In lt RC u when hotmetthe chah e W the signal is slower than the propagation delay on e wire I Therefure WE USE Lumped C mudel in this ease in EmesP We pm as 9 WW rsu ZDDD tense Analysis Examples Rabaey text a Examplew p 144 Capacitance etheisiwie I FactulmZxVulCTllVlEecalculatlunduetubmhsidesmwlleEvllndelWllVlElnE UsesTable u p 1633nuTable as p m u Example 4 2 pp 1464 ceimuiheiusiiestslsneehemh 0e smeiestssneehmeiswspelvihes u Example543p M8 Reslswe 5km eheei analvsls meme 5le Meet ie uelemne at What he widths ti oeeemes nutlceable o 4 4 p t inductanceetmeialwiesetumeieitwulhs Calculate cw em alsu ushehtaeleiteiewhem Ex a 1 E nmvmu aiwhat upeialhe heeuencv and ENEquot WWE widthswe staii in see inductance u Example 4 5 p 152 turmeu eapaenanee elwiie ushe Klichu slaW chins law R39Ctlme constant a Example546p 5 p Elmeie calculatlun at R39Crlnuuced wie uelav ultleer luctuled quotENum u Exampl254 a 4 a Distnhuted in line calculatensthat reduce te Lumpeu RC Elmeie and Lumpeu c 35 D u Summary D The continuum ofwire modeling We looked at different models and how th address the issue of propagation delay through the interconnec network We used various techniques based on ronnulatin the Re time constant given a step input transition from logic to logic mrom the gate dnver39 of the line and loadquot on the other end M deling continuum 1wire model 2 lumped parameter models c alone RC a distributed rc line model A transmission line model lossless lossy These models progressrrom sim leto complex theiruse depending on the effects bang studied and e accuracy required Different automated tools may sl pport some set of these assumptions in the analysis capabilities provi ed to the designer a Examples from GM text the progression ormodeling results rorthe 25 micron cmos process

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