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Advanced Digital Design

by: Stanford Cummings DDS

Advanced Digital Design ECPE 174

Stanford Cummings DDS
GPA 3.84


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This 8 page Class Notes was uploaded by Stanford Cummings DDS on Monday October 26, 2015. The Class Notes belongs to ECPE 174 at University of the Pacific taught by Staff in Fall. Since its upload, it has received 59 views. For similar materials see /class/229910/ecpe-174-university-of-the-pacific in ELECTRICAL AND COMPUTER ENGINEERING at University of the Pacific.

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Date Created: 10/26/15
ECPE174 ADVANCED DIGITAL DESIGN LECTURE NOTES USING DEVELOPMENT SYSTEMS TO CREATE COMBINATIONAL CIRCUITS Circuits can be designed much the same as when using discrete logic 1 DESIGN all you need is Schematic Capture software or use PALASM or VHDL or Verilog just make sure the logic blocks you use are available in the software39s library you can create your own hardware macros to create your own ALUs for example 2 FUNCTIONAL SIMULATION checks for proper function but does not account for circuit delays not known yet not until actually in PLD 3 ROUTING a router determines how to con gure amp interconnect FPGA modules to produce your circuit It may require some help from you It may request circuit simpli cation It may not be able to get your whole design on 1 FPGA requiring you to split the designbetween two or more FPGAs 4 BACK ANNOTATION the development system determines the circuit delays and back annotates those delays into the simulation 5 SIMULATION The normal steps of logic design should be a block diagram schematic capture HDL computer simulation redesignre simulation until it works prototype and testing 99057 5 PROGRAMMING some PLDs can be programmed only once XILINX uses RAM however ALTERA uses true EPLDs however its largest PLDs also use RAM to store program data 6 TESTING if it doesn t work start over ANALYSIS State Machine designs LOTS of EXAMPLES 1 Is it a MEALY or a MOORE machine 2 Determine the State Diagram and State Table It may help to determine the Next State logic functions Ie the functions for Qinext and for the outputs This is called SYMBOLIC ANALYSIS DETERMINING Fmax EXAMPLES METASTABILITY If the possibility of not meeting SETUP or HOLD Times exists the behavior becomes nondeterministic That is the circuit exhibits metastability Later we will learn how to prevent metastability TIMING DIAGRAMS EXAMPLES CLOCK SKEW Clock skew occurs when the clock edge arrives at different FFs at different times Therefore the state transition is Not precise Glitches can occur on the output if more than one FF is supposed to change state Be aware of this as you design If only one FF can change state at each clock transition no problem Otherwise ask yourself quotCan the system withstand glitches at the outputquot It can if the output is going to a Lamp for example If it cannot then deglitch the output as shown later in the discussion of design implementation EXAMPLE Converting between D and JK ip ops CHAPTER 9 SEQUENTIAL DESIGN SYNTHESIS NOTE We will not take the time to study STATE REDUCTION We will assume that our Design Tools will handle this for us Note that implication Tables are used to eliminate redundant states However look at Problem 5 Page 293 and point out the EQUIVALENT STATES a and b Two states are equivalent making one of them redundant if both have the same outputs and both go to the same states given the same inputs DESIGN EXAMPLES RESETTING vs NONRESETTING Behavior A Resetting Example Detect three ls in a row X 0101111110 Z 0000010010 A Nonresetting Example Detect three Is in a row X 0101111110 Z 0000011110 DESIGN both machines using MOORE Machines NOTE that MEALY Machines can sometimes have fewer states and therefore be simpler but I personally fear their behavior DESIGN one of the above as a MEALY Machine and compare Compare at the output TIMING DIAGRAMS of the two 1 Generate a minimal resetting state diagram that detects an active1 signal pulse 010 or an active0 signal pulse 101 The output is active1 Do not include any unused states Show the implication table demonstrating that there are no redundant states Problem 91 2 Repeat Problem 1 but generate a minimal nonresetting state diagram 3 Examine a given state diagram e g on Page 293 and determine if it has any Equivalent States 4 Design a 2bit updown counter with enable Problem 98 5 Design a clock frequency divider eg dividing the clock by 6 Note how easy divideby2 or 4 or 8 are 6 Design a state machine that detects two Is in a row in an input X Examine SELFCORRECTING machines which get back into correct operation whenever they inadvertently enter an unused state 7 Design a state machine that detects three ls in a row in an input X 8 Design a state machine that detects two ls not necessarily in a row 9 Design a state machine that detects two ls but they cannot be in a row 10 Design a state machine the detects two ls and sets its output high for two clock cycles The input is ignored while the output is high 11 Design a state machine that samples the input in 3bit windows If a majority of the bits are high the output is set high and the circuit locks up holding the output high One Hot Design It39s simple just have one ip op per state It39s fast no Kamaugh maps Can often assign an output to be active in just one state and therefore the output is simply one of the FFQ outputs eliminating glitches in outputs But can get more complex IFL GREAT for PALs because can see state and output equations directly from state diagram THEREFORE design time is short no Kmaps BUT good ONEHOT design is generally a matter of judgment and trial and error EXAMPLES CHAPTER 10 SEQUENTIAL DESIGN IMPLEMENTATION DEBOUNCING switch inputs using an SR setreset latch just use two NAND gates and a SPST switch SYNCHRONIZING the Inputs RULE If branching transitions out of a state depend on a single asynchronous input the codes for the branch states should be logicadjacent ie they should differ in only 1 bit have only one ip op change state at a time otherwise one ip op may have its tsu met and another may not especially when the number of gate delays differs for each ip op input RULE Synchronize all input changes on the edge of the clock that does not change the state Best when clock has 50 duty cycle To do this use a FF on each input Run each signal to the D FF input and run an Inverted clock to the clock input Of course this assumes a relatively slowchanging input that has pulses that are at least as wide as the clock period If this is not the case Speed Up The Clock DEGLITCHING the Outputs Glitches are unwanted shortduration changes in the output of a state machine that occur as the machine changes state EX When one want an op HIGH in state 11 and the machine goes from state 01 to 10 but bit 1 changes faster than bit 0 smaller tp The problem can also be caused by variable gate delays SOLN Same as with asynchronous inputs that have not been made synchronous with a FF don t let more than 1 ip ip change states at a time In any case where you cannot avoid having more than 1 state bit change at a time you have 3 choices 1 Delay the output one clock cycle by latching it into FFs or register and clocking the FFs with the clock 2 Delay the output 12 clock cycle by latching it into FFs And clocking with an inverted clock 3 Delay as little as possible by using the regular clock But delaying it minimally with pairs of inverters Note that PROMbased outputs will have glitches as the PROM s address inputs change We often use a deglitching register on the outputs of a PROM as will see later when doing many State Machine design STATE CODE ASSIGNMENT We choose speci c state assignments to I prevent asynchronous inputs from throwing us into unwanted states an input change meets the Tsu of one FF but not the Tsu of another FF taking us for example from state 00 to state 01 when we want to go to state 11 2 prevent output glitches 3 simplify the IFL input forming logic 4 simplify the OFL output forming logic Note Development systems generally handle state assignment for you DEBUGGING 1 CHECK EVERY PIN OF EVERY 1C a Only output pins can be left unconnected all others must have a connection to either 1 Vcc 2 ground or 3 the output of another gate or IC b Make sure all Vcc inputs have 5 volts on them c Make sure all ground inputs are connected to ground d Trace all other inputs to their source to ensure that each connection is correct To Debug Sequential Circuits you must step your circuit through its states one state at a time checking the Present State and the Next State at each step In each state ask yourself 1 What should be the Next State 2 Is that state the Next State as shown on the D inputs to my flip ops 1 Turn the circuit clock off and note the state of circuit 2 Use a wire connected to a lamp as a quottest probequot To answer question 2 above put the quotprobequot on each D input to see what the real Next State will be If it s not the Next State you want as shown in your State Diagram you have a wiring error 3 Once you ensure that the D inputs are what you want them to be the Next State you want press the Clock Button to send a clock pulse to all the ip ops The circuit should go to the Next State as it was seen on the D inputs Now a new Next State will be present at the D inputs Repeat Step 2 4 If all the Next States are what you want them to be you have either a bad chip or a wiring error that is related to either 1 the clock input or 2 the Set or Clear inputs all tied HIGH we hope EXAMPLES 1 Implement a nonresetting sequence detector eg using a 4 16 decoder eg using gates and D FFs 2 Design a resetting Moore Machine that detects the number 9 In binary 3 Design a Mealy Machine to control an elevator Problem 105 4 Design a 4bit ripple upcounter using D FFs Timing Diagrams IMPLEMENTING STATE MACHINES IN SOFTWARE At the end of the semester we will look at the design of CPUs and even design on into a FPGA in the lab BUT here we are NOT talking about designing a computer BUT rather using one to as a state machine after all that s what it is to simulate and test a sequential design Note that a computer does have memory and the code acts as the decision logic Writing a program to test a sequential design is not as often done as it used to be because of today39s available simulation software it s built into PALASM for example HOWEVER it is still true that is sometimes faster easier andor cheaper to simply implement a sequential machine control system in a PC using either standard e g the parallel port or custom IO boards to interface to the ips and ops Compare uPbased systems For testing purposes the keyboard can be used to simulate inputs and the monitor can be used to display simulated outputs whether or not the final system will reside in the computer TWO REASONS why we would NOT use a computer to implement a state machine 1 The design is too simple to tie up a whole computer 2 The needed speed is too great for a computer to do the job BUT don t forget A PC may be an ideal solution to many problems 1 The are generally inexpensive 2 It is easy to just add an IO card amp then write the software in an HLL 3 The software is easily modi ed for changing requirements VERY LARGE STATE MACHINE DESIGN Such systems are often complex controllers that carry a system through many states or more often states of different duration In general we have no branching but we can for example in the case of a computer control unit design we just use a parallel loadable counter Note When states are longlasting and have much branching better to use a PC and do the job in software using delay loops You must know clock frequency and the number of states per instruction We can t use the techniques we ve been using so far too many FFs Kmaps huge state tables etc We use counters such as the 74LSl63 PROMS and latches to deglitch the outputs It39s simple use a large counter and have the counter output be the state number easiest to use a ROM to decode the state serving as the OFL EXAMPLE Specifications Repeat the following every 31100ns PROCl high for lOOns at 500ns 1000ns 1500nsuntil 10000ns PROC2 high for 200ns at 500ns 21000ns and 28000ns PROC3 high for 500ns at 800ns and 15000ns END high for lOOns at 31000ns RST an activelow reset sets quottimerquot to zero All outputs must be glitchfree DRAW a partial Timing Diagram Solution We can see that we need a resolution of lOOns therefore will use a clock of 10 MHz Therefore we will require 3 11 states 0 through 310 will need 9 bits 29 512 We will cascade three 74LSl63s 4bit synchronous counters with synchronous clear will activate the CLEAR a 5th op input on count of 3 10 next clock will clear We will use a 2Kx8 ROM to decode the outputs 11 input bits ground the top 2 bits 8 output bits nc on 3 of them


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