Advanced Digital Design
Advanced Digital Design ECPE 174
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This 8 page Class Notes was uploaded by Stanford Cummings DDS on Monday October 26, 2015. The Class Notes belongs to ECPE 174 at University of the Pacific taught by Staff in Fall. Since its upload, it has received 50 views. For similar materials see /class/229910/ecpe-174-university-of-the-pacific in ELECTRICAL AND COMPUTER ENGINEERING at University of the Pacific.
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Date Created: 10/26/15
ECPE174 Advanced Digital Design DIGITAL I REVIEW The Problems in digital design are 1 SPEED 2 TIMING 3 SIMPLICITY Now What39s All This Good For Gatebased design older engineer at Burroughs Do an example design MUXbased design me at Burroughs Do an example design PROMbase design me at Burroughs Do an example design PLDbased design late 1980s PROMs PALs FPGAs ASICs EEPLDs late 90s Do an example design Schematic capture TTL ICs amp macros Simulation HDL esp Verilog and VHDL simulation Waveformbased design simulation The need to stay current None of the subjects I teach existed when I graduated from college REVIEW DECIMAL BINARY AND HEXADECIMAL NUMBERS a Binary numbers unsigned integers signed integers OVERFLOW UNDERFLOW real numbers IEEE oating point standard b 2s complement arithmetic addition subtraction multiplication amp division c Hexadecimal numbers just group the binary bits into 4s d BCD numbers just translate each decimal digit into its binary equivalent e Coding ASCII codes 7bit ASCII codes text les are stored in ASCII code form note the stuff you see when using a utility to look at les in particular executable les a FAampa ASCII codes are what is sent to printers and over comm lines and to LCD displays BCD codes to 7447 ICs and then to 7segment LEDs BOOLEAN FUNCTIONS a Boolean algebra an example problem OPEN KEYl or KEY2 and KEY3 U Trut tables and mintermsmaxterms C F Canonical SOP lt maxterm getting SOP from truth tables lt minterm assign minterms t0 ls in op lt minterm FA B C ABC ABC AB C lt maxterm lt minterm Canonical POS lt minterm getting POS assigning maxterms lt maxterm to OS in op inverting the ips lt maxterm FABCAB C A B CA B C D ID ID Il OOOODgt h ih IOOl h ioow D IOD OD OD O oot t IOD ID IO l minterms l maxterms l m0 A B l M0 AB l mlA B l M1AB l m2 AB l M2 A B l m3 AB l M3 A B c Boolean Laws and Simpli cation EX minimize FAB B AB BB AB B BA l Bl B SOP or POS form EX minimize FA B C ABC ABC AB C from above B A C AC AC A BC B AC AC CA CA A BC B ACC CA A A BC B A C A BC ABC AB B C LOGIC FAMILIES a Standard logic gates and symbols NAND 7400 NOT 7404 AND 7408 OR 7432 etc b Logic families 7439 commercial quality as opposed to military 54 S Schottky LS lowpower Schottky ALS advanced LS HCHCT highspeed CMOS T TTL compatible AS advanced Schottky ACACT advanced CMOS T TTL compatible F fast polarized mnemonics AH active high AL active low cf A and A symbols AND OR etc we will stick with positive logic LOGIC CHARACTERISTICS TWO IMPORTANT CONCEPTS often missed by inexperienced engineers 1 LOADING 2 TIMING LOADING a Switching characteristics time from change in ip to change in op propagation delays TPHL TPLH b Timing considerations look at the speedlimiting problems with cascading ripple carry lbit adders and mention lookahead carry mention problem I had at Burroughs with high speed and long signal lines signal speed l ftns c Timing diagrams of sequential circuits Fmax maximum clocking speed d Logic device output circuits the pullup and pulldown driver are usually transistors the pullup transistor sources current but the collectoremitter resistance and the currentlimiting resistor drop voltage so the greater the current the lower the output IOH current pullup sources at 24 V out the pulldown transistor sinks current developing a voltage across the collectoremitter junction IOL current pulldown sinks at 04 v out TI39i state devices amp busses e FANOUT Maximum loading the loading that will pull VOH down to 24 v or pull VOL up to 04 v is the max loading under which the device will operate correctly The fanout is number of gates that a gate can drive without exceeding the max loading FANOUTH IOH IIH Pick the lowest of the two FANOUTL IOL IIL IOH highlevel op current sources current since it s negative04 mA 400 uA IIH max current input will sink when input is HIGH 20 uA S0 fanout H 40020 20 loads IOL lowlevel output current 8 mA IIL maX current input will source when input is LOW 04 mA S0 fanout L 804 20 loads True fanout is the minimum of fanout H and fanout L 10 for most TTL gates ie 10 unit loads ul or UL much higher for CMOS f NOISE MARGIN VOH min voltage out high 27 V VIH voltage in high the min voltage that will be seen by a gate as a HIGH 20 v S0 noise margin H 27 20 07 V VIL voltage in low the maX voltage that will be seen by a gate as a LOW 08 v VOL max voltage out low 05 v S0 noise margin L 08 05 03 V True noise margin is the minimum of noise margin H and noise margin L 03 V COMBINATIONAL LOGIC DEVICES The circuits discussed in this circuit are available as TTL ICs and as FPGA modules in Schematic Capture software a Multiplexersdemultiplexers 74LS150 single 161 74LS151 Single 81 74LS153 Dual 41 74LC157 Quad 21 b Encodersdecoders the 42 encoder decoded binary in encoded binary out the 83 encoder amp 38 decoder NOTE a decoder and a deMUX are the same thing decoder ips on the select lines 5V on the data ip deMUX ip on data line select lines select op source 74LSl39A dual 24 decoder or dual 14 deMUX 74LSl38A single 38 decoder or 18 deMUX 74LSlS4 single 416 decoder or 1 16 deMUX c Adders 74L8283 4bit adder with fast carry can be cascaded d Comparators 74L885 4bit magnitude comparator ops lt gt can be cascaded e ALUs 74L8181 4bit ALU can be cascaded COMBINATIONAL CIRCUIT DESIGN Still Review 1 Implementing combinational functions using gates EX Fabc ab c EX simplifying circuits by reusing logic Fabc ab c Gabc ab b 2 Kamaugh Maps EX Fabc E01267 EX Fabcd E0123481012 EX Fabcd a b39c d a bc39d ab c39d abc d a b39cd EX Fabcd ab ab c 3 Implementing combinational functions using MUXs no Kamaugh Maps needed EX Fabc E01267 EX Fabcd E0123481012 EX Fabcd a b39c d a bc39d ab c39d abc d a b39cd EX Fabcd ab ab c 4 Implementing combinational functions using ROMS no Kamaugh Maps needed EX Fabc E01267 EX Fabcd E0123481012 EX Fabcd a b39c d a bc39d ab c39d abc d a b39cd EX Fabcd ab ab c 5 Implementing a FULL ADDER 3 inputs ABCin 2 outputs SumCout SEQUENTIAL LOGIC DEVICES a Edge triggered ip ops D amp JK b Registers My favorites The 74LSl75 with inverted outputs The 74LSl73A with 3 S outputs clk loads G1 and G2 must be LOW for clk to load M and N enable 3S output Cascading my favorites no problem c Counters Ring counters EX 4bit 0001 0010 0100 1000 0001 Class Be able to design a ring counter using ip ops Twisted ring counters only one bit changes at a time EX 3bit 000 001 011111101100110 010 000 Class Be able to design a twisted ring counter d Ripple counters consists of cascaded JK masterslave ip ops each with 2 stages the first the master is loaded according to J amp K when the clock is high the second stage is loaded from the first stage on the hightolow clock transition the point is that the output of each JK ip op clocks the next ip op EX the 4bit JK ip op 74LS93 the op of 1st FF A must be routed to the clock ip B ofthe 2nd FF the chip counts pulses on the A input the count ripples through the ip ops EX Connect two 4 bit ripple counters 74LS163 to form an 8 bit ripple counter LAB 1 Note The input for the pulses is used to clock the first FF Note This chip is often used to diVide down a clock signal e Synchronous counters normal synchronous state machines actually nothing new therefore a master clock goes to all ip ops either edgetriggered D or JK now we can design a synchronous counter of any number of bits But we often nd it easier to cascade synchronous counter chips like the 74LSl6l EX Connect two 4bit synchronous binary counters 74LSl6l to form an 8bit counter Note Asynchronousclear counters are best used when counting pulses e g people ranges and you want to use an asynchronous powerup clear Note the clock input is the quotdataquot input it s the pulses we count EX Design a synchronous counter using one or more 74LS 163s and gates as needed that will count to 17 Note Synchronousclear counters are best used in state machines that repeatedly move through a series of states The terminal count synchronously moves us back to 0 f Shift registers 74LS91 8bit serial in serial out SISO 7494 just note the parallel in serial out PISO 74LS 194 4bit parallel in parallel out PIPO bidirectional EX Design an 8bit shift register with parallel out using 74LS 194
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