Computer Architecture CS 6810
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Marian Kertzmann DVM
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This 20 page Class Notes was uploaded by Marian Kertzmann DVM on Monday October 26, 2015. The Class Notes belongs to CS 6810 at University of Utah taught by Alan Davis in Fall. Since its upload, it has received 29 views. For similar materials see /class/229976/cs-6810-university-of-utah in ComputerScienence at University of Utah.
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Date Created: 10/26/15
Lecture 4 Advanced Pipelines Data hazards control hazards multicycle inorder pipelines Appendix A4A10 Hazards Structural hazards different instructions in different stages or the same stage conflicting for the same resource Data hazards an instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction Control hazard fetch cannot continue because it does not know the outcome of an earlier branch special case of a data hazard separate category because they are treated in different ways Data Hazards Time in clock cycles Value of CC 39I CC 2 CC 3 CO A DC 5 CC 6 CC 7 CC 8 CC 9 reg ster 2 3910 3910 39l 0 1O lOf ZC 20 20 2D 20 Program execution order in instructions sun 13251 3 and 312 2135 or 13 6 2 add 1482 52 SW 15 39IOOISZ39 Bypassing Time in clock cycles CCl CCZ CCS CC4 CC5 CC CC CCS CCQ Value Of register 2 10 10 10 10 10720 e20 A20 720 720 Value of EXMEM X X X 20 X X X X X Value of MEIWWB X X X X e20 X X X X Program execution order in instructions sub 32391 3 and 5 12 3155 or 13 6 2 add 31432 S2 SW l5 39IC OlSZ Some data hazard stalls can be eliminated bypassing Example add R1R2 R3 Iw R4 8R1 Rf Example R4 8R1 R1 8R2 ib Data Dependence Example Iw R18ltR2gt sw R18R3 Rf Summary For the 5stage pipeline bypassing can eliminate delays between the following example pairs of instructions addsub R1 R2 R3 addsublwsw R4 R1 R5 lw R1 8R2 sw R1 4R3 The following pairs of instructions will have intermediate stalls lw R1 8R2 addsublw R3 R1 R4 or sw R3 8R1 fmul F1 F2 F3 fadd F5 F1 F4 Control Hazards Simple techniques to handle control hazard stalls gt for every branch introduce a stall cycle note every 6th instruction is a branch gt assume the branch is not taken and start fetching the next instruction if the branch is taken need hardware to cancel the effect of the wrongpath instruction gt fetch the next instruction branch delay slot and execute it anyway if the instruction turns out to be on the correct path useful work was done if the instruction turns out to be on the wrong path hopefully program state is not lost Branch Delay Slots a From before b From target c From fall through DADD R1 R2 R3 DSUB R4 R5 R6 DADD R1 R2 R3 if R2 2 0 then if R1 0 then Delay slot DADD n1 n2 n3 Delay slot if R1 Othen OR R7 R839 R9 4 Delay Slot DSUB R4 F15 R6 4 becomes becomes becomes DSUB R4 R5 R6 DADD R1 R2 R3 if R2 0 then if R1 0 then DADD R1 R2 R3 DADD R1 R2 R3 if R1 0 then DSUB R4 R5 R6 OR R7 R8 R9 DSUB R4 R5 R6 ozmvamgnlmmlmm Slowdowns from Stalls Perfect pipelining with no hazards 9 an instruction completes every cycle total cycles num instructions 9 speedup increase in clock speed num pipeline stages With hazards and stalls some cycles stall time go by during which no instruction completes and then the stalled instruction completes Total cycles number of instructions stall cycles Slowdown because of stalls 1 1 stall cycles per instr Pipeline Implementation Signals for the muxes have to be generated some of this can happen during ID Need lookup tables to identify situations that merit bypassingstalling the number of inputs to the muxes goes up DIEX EXMEM MEMWB Data memory gt c2007 Heavier inc All nytamaezveu Detecting Control Signals Situation Example code Action No dependence LD R145R2 DADD R5 R6 R7 DSUB R8 R6 R7 0R R9 R6 R7 No hazards Dependence requiring stall LD R145R2 DADD R5 R1 R7 DSUB R8 R6 R7 0R R9 R6 R7 Detect use of R1 during ID of DADD and stall Dependence overcome by fonNarding LD R145R2 DADD R5 R6 R7 DSUB R8 R1 R7 0R R9 R6 R7 Detect use of R1 during ID of DSUB and set mux control signal that accepts result from bypass path Dependence with accesses in order LD R145R2 DADD R5 R6 R7 DSUB R8 R6 R7 0R R9 R1R7 No action required Multicycle Instructions Intugm unit EX LI FPe imeger multiply M1 E W will 62007 Elmer inc All quotmama Functional unit Latency Initiation interval Integer ALU 1 1 Data memory 2 1 FP add 4 1 FP multiply 7 1 FP divide 25 25 14 Effects of Multicycle Instructions Structural hazards if the unit is not fully pipelined divider Frequent RAW hazard stalls Potentially multiple writes to the register file in a cycle WAW hazards because of outof order instr completion lmprecise exceptions because of 000 instr completion Note Can also increase the width of the processor handle multiple instructions at the same time for example fetch two instructions read registers for both execute both etsc Precise Exceptions On an exception gt must save PC of instruction where program must resume gt all instructions after that PC that might be in the pipeline must be converted to NOPs other instructions continue to execute and may raise exceptions of their own gt temporary program state not in memory in other words registers has to be stored in memory gt potential problems if a later instruction has already modified memory or registers A processor that fulfils all the above conditions is said to provide precise exceptions useful for debugging and of course correctness Dealing with these Effects Multiple writes to the register file increase the number of ports stall one of the writers during ID stall one of the writers during WB the stall will propagate WAW hazards detect the hazard during ID and stall the later instruction lmprecise exceptions buffer the results if they complete early or save more pipeline state so that you can return to exactly the same state that you left at ILP Instructionlevel parallelism overlap among instructions pipelining or multiple instruction execution What determines the degree of ILP gt dependences property of the program gt hazards property of the pipeline Types of Dependences Data dependences an instr produces a result for another true dependence results in RAW hazards in a pipeline Name dependences two instrs that use the same names anti and output dependences result in WAR and WAW hazards in a pipeline Control dependences an instruction s execution depends on the result of a branch reordering should preserve exception behavior and dataflow Title Bullet 20
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