Computer Architecture CS 6810
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Marian Kertzmann DVM
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This 17 page Class Notes was uploaded by Marian Kertzmann DVM on Monday October 26, 2015. The Class Notes belongs to CS 6810 at University of Utah taught by Alan Davis in Fall. Since its upload, it has received 42 views. For similar materials see /class/229976/cs-6810-university-of-utah in ComputerScienence at University of Utah.
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Date Created: 10/26/15
Lecture 15 Virtual Memory and Large Caches Today TLB design and large cache design basics Sections 5354 TLB and Cache Is the cache indexed with virtual or physical address gt To index with a physical address we will have to first look up the TLB then the cache 9 longer access time gt Multiple virtual addresses can map to the same physical address can we ensure that these different virtual addresses will map to the same location in cache Else there will be two different copies of the same physical memory word Does the tag array store virtual or physical addresses gt Since multiple virtual addresses can map to the same physical address a virtual tag comparison can flag a miss even if the correct physical memory word is present 2 Virtually Indexed Caches 24bit virtual address 4KB page size 9 12 bits offset and 12 bits virtual page number To handle the example below the cache must be designed to use only 12 index bits for example make the 64KB cache 16way Page coloring can ensure that some bits of virtual and physical address match abcdef abbdef Virtually indexed cache lt cdef lt bdef Data cache that needs 16 index bits 64KB directmapped or 128KB 2way Cache and TLB Pipeline Virtual address Virtual 39 indexv Offset Virtual page number Physical page number Physical tag Physical tag comparion Virtually Indexed Physically Tagged Cache Superpages If a program s working set size is 16 MB and page size is 8KB there are 2K frequently accessed pages a 128 entry TLB will not suffice By increasing page size to 128KB TLB misses will be eliminated disadvantage memory wastage increase in page fault penalty Can we change page size at runtime Note that a single page has to be contiguous in physical memory Superpages Implementation oAt runtime build superpages if you find that contiguous virtual pages are being accessed at the same time For example virtual pages 6479 may be frequently accessed coalesce these pages into a single superpage of size 128KB that has a single entry in the TLB The physical superpage has to be in contiguous physical memory the 16 physical pages have to be moved so they are contiguous virtual physical virtual physical Ski Rental Problem Promoting a series of contiguous virtual pages into a superpage reduces TLB misses but has a cost copying physical memory into contiguous locations Page usage statistics can determine if pages are good candidates for superpage promotion but if cost of a TLB miss is X and cost of copying pages is NX when do you decide to form a superpage If ski rentals cost 20 and new skis cost 200 when do I decide to buy new skis gt lfl rent 10 times and then buy skis I m guaranteed to not spend more than twice the optimal amount 7 Protection The hardware and operating system must cooperate to ensure that different processes do not modify each other s memory The hardware provides special registers that can be read in user mode but only modified by instrs in supervisor mode A simple solution the physical memory is divided between processes in contiguous chunks by the OS and the bounds are stored in special registers the hardware checks every program access to ensure it is within bounds Protection with Virtual Memory Virtual memory allows protection without the requirement that pages be preallocated in contiguous chunks Physical pages are allocated based on program needs and physical pages belonging to different processes may be adjacent efficient use of memory Each page has certain readwrite properties for userkernel that is checked on every access gt a program s executable can not be modified gt part of kernel data cannot be modifiedread by user gt page tables can be modified by kernel and read by user 9 Intel Montecito Cache Two cores each with a private 12 MB L3 cache and 1 MB L2 Intel 80Core Prototype Polaris Prototype chip with an entire die of SRAM cache stacked upon the cores Example Intel Studies H H H Interconnect IO interface L3 Cache sizes up to 32 MB From Zhao et al CMPMSI Workshop 2007 12 Shared Vs Private Caches in MultiCore What are the proscons to a shared L2 cache L1 L1 L1 L1 5 L1 L1 L1 L1 I I I I I I I l I I L2 L2 L2 L2 L2 Shared Vs Private Caches in MultiCore Advantages of a shared cache Space is dynamically allocated among cores No wastage of space because of replication Potentially faster cache coherence and easier to locate data on a miss Advantages of a private cache small L2 9 faster access time private bus to L2 9 less contention UCA and NUCA The smallsized caches so far have all been uniform cache access the latency for any access is a constant no matter where data is found For a large multimegabyte cache it is expensive to limit access time by the worst case delay hence nonuniform cache architecture Large NUCA DDDDDDDDDDDD DDDDDDDDDDDD DDDDDDDDDDDD DDDDDDDDDDDD DUDE DUDE DEED DEED DUDE DUDE DUDE DUDE DDDDDDDDDDDD DDDDDDDDDDDD DDDDDDDDDDDD DDDDDDDDDDDD Issues to be addressed for NonUniform Cache Access Mapping Migration Search Replication Title Bullet
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