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Digital VLSI Design

by: Marian Kertzmann DVM

Digital VLSI Design CS 5710

Marian Kertzmann DVM
The U
GPA 3.78


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This 6 page Class Notes was uploaded by Marian Kertzmann DVM on Monday October 26, 2015. The Class Notes belongs to CS 5710 at University of Utah taught by Staff in Fall. Since its upload, it has received 22 views. For similar materials see /class/229981/cs-5710-university-of-utah in ComputerScienence at University of Utah.

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Date Created: 10/26/15
Quick Review Quick Review gt Continuous assignments to wire vars r assign variable exp r Result in combinational logic t Procedural assignment to reg vars wires r Always inside procedural blocks always H internal regs possibly output blocks in particularfor synthesis the parts of the module body are tblOthng executed concurrently 39 var39able exp ltcontinuous assignmentsgt 39b39 k39 g t variable lt exp lt3W3YS bIOCkSgt gt Can result in combinational or sequential endmodule logic Module name args b in 99 input define inputs Procedural Control State nents llultiWav Decieimns 39 conditional Statement gt Standard ifelseif syntax t if ltexpressiongt ltstatementgt t if ltexpressiongt ltstatementgt else ltstatementgt t else is always associated with the closest If ltexpressi0ngt ltstatementgt previous ifthat lacks an else else if lteXpreSSiOI7gt gt You can use beginend blocks to make it more ltstatementgt dear else if ltexpressiongt ltstatementgt else ltstatementgt else result regb Priori b vs Parallel Choice quot Priorit I vs Parallel Choice module priority a b c d sel z module parallel a b c d sel 2 input abcd inputabcd input 30 sel input 30 sel tput 2 output 2 reg z reg 2 always a or b or c or d or sel always a or b or c or d or sel begin begin if sel0 z a if sel3 z d D c B if sel1 z b w else if sel2 z 39 if sel2 z c else if sel1 z if sel3 z d else if sel0 z a endmodule endmodule Case Statements r Multiway decision on a single expression case ltexpresiongt gt gt ltstatementgt default ltstatementgt endcase simple counter nextstate logic onehot state encoding parameter 20 sO3 h1 reg20 state nextstate always input or state begin case state so if input nextstate 51 else nextstate so nextstate 52 s nextstate so endcase end 51 Larch Inference r lncompletely specified if and case statements cause the synthesizer to infer latches always cond begin if cond dataout lt datain end gt This infers a latch because it doesn t specify what to do when cond 0 gt Fix by adding an else gt In a case fix by including default Case Exam sle reg 10 sel reg 150 inO in1 in2 in3 out case sel 2 b00 out inO 2 b01out in1 2 b10out in2 2 b11out in3 endcase Weird Case Exam gtVerilog allows you to put a value in the case slot and test which variable currently has that value reg 20 currstate nextstate parameter s13 b001 523 b010 s33 b100 case 1 currstate0 nextstate 2 currstate1 nextstate 3 currstate2 nextstate 1 endcase Full vs Parallel gt Case statements check each case in sequence r A case statement is full if all possible outcomes are accounted for r A case statement is parallel if the stated alternatives are mutually exclusive gt These distinctions make a difference in how cases are translated to circuits gt Similar to the if statements previously descnbed Case fu ar examle llfull and parallel combinational logic module fullpar slct a b c d out input 10 slct 39 t i reg out ll optimized away in this example oraorborcord i really 239b10 endcase endmodule Case noifull ar exam e la latch is synthesized because case is not full module notfullpar slct 39 inpu 10 slct In ut c output out reg out ll NOT optimized away in this example always slct or a or b or c 0 out b 239b01 out lt c dcase endmodule Case fullnot ar exam ll because case is not parallel priority encoding II but it is still full so no latch llthis uses a casez which treats as don39tcare module fullnotpar slct a b c out always slct or a or b or c casez slct 39 7 b1 39 out lt a 239b1 out lt by default out lt c se endmodule S nihesis Result gt Note that fullpar results in combinational logic slctO slctl S nthesized Circuit r Because it s not full a latch is inferred slctO slctl S nthesized Circuit gt It s full so it s combinational but it s not parallel so it s a priority circuit instead ofa check all in parallelquot circuit 3 A Case notfullnotar ex ll because case is not parallel priority encoding ll because case is not full latch is inferred luses a casez which treats as don39tcare module fullnotpar slct a b c out always slct or a or b or c casez slct 239b17 39 out lt 3 239b1 out lt b endcase endmodule nos m39iler Directives You can give hints to Synopsys through comments in yourVerilog code gt They are ignored as comments by VerilogXL ll syn opsys fullcase t asserts that all possible clauses of a case have been covered no default case is needed gt better to just use default ll synopsys parallelcase gt Results in parallel evaluation of cases instead of serial priority encoding t Usually only used for mutually exclusive cases FSM Descri gt One simple way break it up like a schematic t A combinational block for nextstate generation t A combinational block for output generation t A sequential block to store the current state S nthesized Circuit gt Not full and not parallel infer a latch Case With Comiler Directives reg 1 0 in out reg 20 currstate nextstate parameter s1339b s2339b010 s33 b100 case in II synopsys fullcase 0out39 case 1 ll synopsys parallelcase fullcase currstateO nextstate 52 currstate1 nextstate 53 currstate2 nextstate Si Model 0 State Machines General yleyy mere detalls later SM Elk ln nut k n Nextistate my 7 tate alyyays pusedgeclk state nextistate alyyays state e negtlttestate lugl eumpute tstate and uutputlugl make sure every leeal varlable has an asslgnrnent ln thls black endrnudule state reglster madule riiaare dk Di my MW Hde rie wriihirialiarial lagictar iripm err en nag iineasiaie easetseie m sEI itiris riex7 alersii 1 Zw sa m elseriexi slalers HdetirieregvarslarslalerEEisler iiananeasieieia e u a reg n m state neaseie naennesieieyeeiseytwin sannnsweasm 1 lsyrichrariaus adiverhigh clear else riexiislale set always pasedge err endcase begin end it oh slate su Hassigri amsg as canliriuaus assign else state 7 neasieie my W s quot state iitsmxsan endriiadule er5ion Vei393ion Continued mudule muure elk ein insig uutsig WM Eik Bin mm define cumbiriatiuriai ingie fur nextistate mm mm always insig urstate define state erieudirigs as parameters parameter i u sEI Tenn si mm a 22 biu 53zibii SD ifirisigriegtlttistatesi g vars fur state register and nextistate ingie 51 Erinlfg nii sgtg 52 state next state 7 E SE nextisi 1 defirie state register Witn synchruriuus activerhigh clear 52 if W9 Migrate 3 always pusedge elk 5m 2 egiri if ei s define re reg i D else next e s s3 lflrislg nextistate si clr state su eise nextistate e su e te r nextistate eridcase a Ier Directives riuvv set the uutsig This cuuld alsu be dune in an always blucllt butintnateaseuutsigwuuienavetebe gt Can tell Synopsys which reg is the state ate register and which are the st Udefiried asareg encodings assign uutsig state si ii state s3 endmudule t This will let synopsys extract the FSM from th escription and apply different optimizations gt Not required but might result in faster circuits V II synopsys statevector ltnamegt VII synopsys enum ltnamegt From FSlvl Exam Unsunortecl for S nthesis u inputclki or r initial blocks use explicit resets output outsig ll de ne state encodings as parameters parameter 1 0 ll synopsys enum states s0 239b00 s1 239b01 s2 239b10 s3 239b11 ll de ne reg vars for state register and nextstate logic reg 10 P synopsys enum states I state reg 10 P synopsys enum states nextstate syn opsys statevector state II the rest is the same as before mod le moore clk clr insig outsig Delay synopsys WI Ignore 5 insig r release Dried Stuff 39 ional Always Blocks gt You cannot assign the same reg variable gt Be careful in more than one procedural block don t do this always posedge a out i 39 always sel if sel 1 ou in1 out in139 else out in2 else out in2 always posedge b gt Which one is a good mux out in Sync vs t e isvnc Register Reset The Big Picture synchronous reset activehigh reset 35133 always posedge clk 39 reset state s0 39 l e st te 39 C 39 I Structural V erilog Ensemble if reset state s0 else state s1 Existing Cadence Cadence Datapath Virtuoso Composer Layout Layout Schematic if e a H async reset activelow reset D always posedge clk or negedge reset


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