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# Digital VLSI Design CS 6710

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This 35 page Class Notes was uploaded by Marian Kertzmann DVM on Monday October 26, 2015. The Class Notes belongs to CS 6710 at University of Utah taught by Staff in Fall. Since its upload, it has received 33 views. For similar materials see /class/229984/cs-6710-university-of-utah in ComputerScienence at University of Utah.

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Date Created: 10/26/15

V Woutd be ntce 0 have V FUEL normattze a modet Of detay O ack O the dtmenstontess untts O tsotate fabrtcatton effects r em u z Eff U r L ts the detay er a mtntmum thverter drtvtng Bunk by Summnd ahethermthtmum twenerwtm he parastttcs Spmutt Hams r trr a u Eu pruness thts ts apprux Amps D K abuut detay tn terms at u r and seate tt te Whatever preeess We re nuttmhgthe Etmutt tn r chapter 1 ts un uur Web page Effort Delay 39 Dew of a gate d has MO components rThe effortdetay due to toad can be rurther broken down tnto two terms r Afthd part atteu parasmc delayp 39 f g h named the 917071 delay ur stage 977071 f the game s structure 7 r Tmat detay ts measured tn untts um and ts V gt sum Mme Mays 7 r h eteetrteat etrurt whteh captures prupemes d 7 uftuad andtranststur stZEs D 39 39 J E th to cm ts repentance that tuads the MM r r 0 t5 capacttahce mesemed at the mm m e gh p Computing Logical Effort ca 0 r Logtcat errort hormahzes the output drtve r capab w O a gate to match a m r DEF Lngtca effan ts the ram ufthe rhput tnvener U capacttance Ufa gate In that capacttance ufan mtener deltvertng the r Measure trorh detayvs fanout ptots t B r Or esttrhate by couhtthgtrahststorwtdths E E Loical Effort of Other Gates Electrical Effort r Logical effort of common gates assuming that PIN size ratio is gt Value oflogical effort g is independent of trans39 tor size gt It39s related to the ratios and the topology Number of inputs El t I ff nh t m d Gate Type 1 2 3 5 n 39 6 r a 6 cap 5 6 quotYe Inverter 1 capability ofthe transistors Via sizmg NAND 43 53 63 73 gt Electrical effort C 53 73 93 113 2n13 2 2 4 12 32 NOR MUX XOR nut in gt Note that as transistor sizes for a gate increase h decreases because Cm goes up Parasitic Dela Plots of Gate Dela r Parasitic delay p is caused by the internal capacitance ofthe at gt It39s constant and independent oftransistor size gt As you in rease the transistor size you also increase the cap ofthe gatesou edrain areas ich keeps it constant t For our pu nput N Estimation Estimation Deiny Estlmmion Delay Estimation Remember 1 m B Our pmeess 4Eps Remember m A Ourpmcess4 ps g hp l tCinBCmA Jleiayqup l innmm ZUUpS i39ivcimvrmm v i 4 sumeuniis I MquotCin lLInAI 1144 imL39units U ps Zps F04 Inverter delay p5 A 3 F04 NA D delay 7Zps Lucia syn p HISPACinBCiiml Z l Cm n 393 12 CmA4 eiJxmzml 4 A 2 e a unit 24nps A d umuimm begun ot39lugjmlxmmtitic mu Not mu g ll tumt mmme or both hcmmc NA c w emitmm Alr mms 24nps xmncr Namll mlsc incl higher mm net Ian iiiwmr 92 mm m wontoxin Nomtlm g h lcmt m amc t39nrboth buctmeAN u ulllec ummilmc b2 sllrdta proud same Exam le Ring Oscillator As technology advan 06 1 continues to r Estimate the frequency of an Nstage ring sh rink oscillator r Exact numbers are surprisingly difficult to get gt This table is very very rough Logical Effort g Electrical Effort h Parasitic Delay p Stage Delay d Period of osc Examle Rin Oscillator Examle F04 Inverter r Estimate the frequency of an Nstage ring r Estimate the delay of a fan outof 4 F04 scillator inverter u Logical Effort Electrical Effort Parasitic Delay Stage Delay coo Logical Effort g 1 Electrical Effort h 1 Parasitic Delay p 1 Stage e ay d 2 so dabs BOps Period 2N dabs 496ns Freq 200MHz Exam le F04 Inverter r Estimate the delay of a fanoutof 4 F04 inverter E The F06 neiavisaimm n m psmn e um Pmcess if r If cm x Cout 10x thus h 10 39 39 r g 93 Parasitic Delay p 1 t stageDelay d9hp5 gtdghp31o41341360ps Miiitismge Delay 39 Recall ntlc onlmmh than said hi hillnnu the delay dl catch tl surge along it critiuul pa i c s ut39lugicul clTurl rind clcnricul ian em be Mu to multistage paths gi 0tTptlli land will divert electrical el tbn Earn the main patli M Wu C mm 1 account hi i De ne a tl ultt ht39itg B nl a as t 31 h iciiii39paiii Cummiiii 39mlJMlh ElCuse The branchingi ciTon will llmdtry the electrical ciVnrl Ilccdcd ill that stage Tire brunch ctTan s ot39llle path is B nbiii mini eimrieai 1an H Coin iciiinN W Mus rtiricmbur tliltt tlcctntal emiri only is concerned Wlilt en39m arkng network on input drivers and Ouipm load Summary multistage networks Branchin r Logical effort generalizes to multistage gt Remember branching effort networks r Accounts for branching between stages in P r Path Logical Effort G HE C Canaan t mm Cmvmh Wm 39 B Hi7 r Path Effort F Hf Ugh t Path Electrical Effort H gt Now we compute the path effort gtCanwewriteFGH gtFGBH Multistae Dela Desininc Fast Circuits gtPath Effort Delay DZf DZdDP Delay is smallest when each stage bears effort A r Path Parasitic Delay PZp f h L g F 39 Path Delay D Zd DF P Thus minimum delay ofN stage path is D NF P This is a key result of logical effort r Find fastest pussibie dela r Deesri t require calculating gate sizes Minimizrnq Path Dela I Tim nbsolmc delay wrii me me parasitic delays reach singc ulm d ihcr However rrrr fnt39ur imf iI mi qYmi F rm IIIinImiA iun prrrpom 3m umsmc data an commit For rm N rgc network rhc mm Ivav n tum irlu39n urnh mgcm irr patr with the Amnexmgr u orr rirrrin gm39liii rm Minimum acirrrwiric pmh dlay gt P hrmim N I Nniclllzliifk than u H p Innngmiilsingicgalccqlmiun r Size ihc imnsismrs oi ihc uandZ garcs for the lhrcc stages drown th logic c bn G gu gl g m m m a 737 Branching rrun B L 10 no oifpnill loud Eircrrrcrri c 39on H CourCm CIC 7 Min ricirry achievable 3 G s39mm 3 Z pinv 1 1237 1 1 iz im a 100 I r a mmDNquotF W P Where gain capacitance of Z W quotL Musfc 12 C hoosc W accordingly Choosin Transistor Sizes Remember tlxn me ring mm mm is mirrred m lmnsi nr slz mum gm39liri i4quot Sr hm min i quot i gli To me mmsi ms mm m end ufpnih uml Dmpme Crrrrri m Cm r r quotmini Once Crniri rs know can distribute his among Irnnsismrs ui39rirm stach Ie continued i39llc em rn orcacrr gt12ng wilt be rmrnG39Bili 113739i0 l0i39 i33 43 Cm ol liisi gaicshmlld cqmi Cirilxstgaxcmun gi Cnuliii irrrrirri 43 CllS c Cin al39middic gate should equal 39in mrririic gar a Cm iarr germ11mm 4J3 C 43 Ail gnus have same inpur capacirarrcc disrrlbmc ii among immmn rer Load Another Exa L 5m rim imnsrslors oriiw nandl gums for mu ircc surges own S Hill logic umm i u 11 g1 g2 mm mm w a z 37 Branching clT39ori B LU no offth may Elccmcnl cl39l39nn n r ComCI G39B HW J rzpirrri 39r 3739I Xi39 r J2 01NIi Mm dchy achmvnblc 80 Load Examle 16f m Cha 1 quotquot quot Sue path from mm G E Hr quot39 2173913 8 39 A m B cln oflns gal should mull can Insg1lcmin Comm nminl z 1 Hum 4c Cm nfmiddlc gum slmuld cquulz I cu clnmmlcgm i Cinlllslgznclmin 11 m 3 6 t 40 mm 2c ouLCin 4 soc 4 s 13 3mm 5 MY Nolc mm cacll slag gels progressively lmgcr n s ypwnl H P m 1 1 Mlndclay 77 NW k P 7 J VMV 32pmvl 131mm Mm a mu nvlng A large 10 Exam 0 Ie 16 Continued Shlgc c un ul39e n mge should be nlln FW GBIW 64 4 Dclcmline Cin n usl Ange Com I mint 43 4 SC 4 I SC 39in ul millu lc mgc 7 5 391339Cmtzw mnln41 39 J IVSC H l 5C CIHIA g Z39Clllly lnln733 39ll l 504 7 1 Ya sclfConslshtul Logical Effort G 435353 10027 39 H 458 B 3 2 6 F GBH 125 f35 P 2 3 2 7 gt Work backward for sizes y Cmy 7 v V Pall logic cl39lhn G 7gn 39gl u g37 l SJ 4 I 710 ml Branch T 39l on B ram elcclncal dth ll 7 ComCm 72mm 7 2 Pull mg mam 7 F 7 G39B ll 7 pomp1392 7 409 ForMmdclmy mslusmgs hasc on 0quot 7 1409 7 L45 1 7g quot Com11mm I39ml IA y g 39 lezl mm 3 14 3 t 7 g onlymiminrss 13143 7 l5 Nuts Dun39t care aboutparasmcs fur gate sizing unlyxfyuu Wanttu know absolute delay Exam Ie 3stae oath gt Work backward for sizes y4553l5 15 x15253510 Misc Comments gt Note that you never size the rst gate t This gate is assumed to be x r If you were allowed to size it the algorithm would try to make it as large as possible gt This is an estimation algorithm gt Authors claim that sizing a gate by 15x too big or small still results in a path delay within of minimum thlogic clTon a 7 o gl g2 71mm 17 2 m Branch effort B Pall electriml mm H CmIlCin XCC R Palh stage c bn 7 F G EH 7 ZN 8 7 m Mm dclay ml N P n 16 pinv 4pinv pilw t 25 a 7 135 How man staes r Considerthree alternatives for driving a load 25 times the input capacitance t Three inverters in series iCiu SCC Pt gt Five inverters in series 1 a t a i we I 8 WW gtThey all do the Job but which one is on Miiutclny um i I 60 939 win v l piiw v 2pinV 25 1 s 7 i2 3 0mm 1 appears to be beltcr ilitin 0mm llL by A slight margin How man staes Choosin the Best of Staes r In all cases G 1 B 1 and H 25 gtYou can solve the delay equations to path deiay is N251N N pW determine the number of stages N that s 5 nus will achieve the minimum delay t N 3 D 11B units tApproximate by LoglF V N 5 D 145 units ath Effort Best n Deiay stage effort gt Since N3 is best each stage Will bear 7 F N D an effort of 25m 29 05 gt So each stage is 3x larger than the last gt In general the best stage effort is between 3 an 4 not e as otten stated rThe e value duesn t use parasitic i D 1 2 24747 3 4 5 6 10903920 25 3729 8 I gt How sensitive is delay to using exactly the best gt String ofinverters driving an offchip load number ofstages r Pad cap and load 40 r t Equivalent to 20000 microns of gate cap t Assume rst inverter in chain has 72u of input cap gt How many stages in inv chain r H 2000072 2777 gt From the table 6 stages is best r 24 lt p lt 6 gives delay within 15 of optimal 39 Stage em f 2777M 375 rvve can be Sluppyl r Path delay D 6375 6Pinv 285 a 4 I gtD114nsh40ps Summary gt Compute path effort F GBH gt Use table or estimate N log4F to decide on number of stages r Estimate minimum possible delay D NF N 2pi gt Add or remove stages in your logic to get close to N r Compute effort at each stage f F N gt Starting at output work backwards to compute transistor sizes Ciquot gifC0m Sumr nar r b Logical effort is useful for thinking of delay in circuits r Numeric logical effort characterizes gates r NANDs are faster than NORs in CMOS r Paths are fastest when effort delays are 4 b Path delay is weakly sensitive to stages sizes gt But using fewer stages doesn t mean faster paths r Delay of path is about logAF F04 inverter delays blnverters and NAND2 best for driving large caps t Provides language for discussing fast circuits gt But requires practice to master Limits of Loical Effort r Chicken and egg problem gt Need path to compute G gt But don t know number of stages without G r Simplistic delay model t Neglects input rise time effects r Interconnect t Iteration required in designs with Wire gt Maximum speed only gt Not minimum areapower for constrained delay gt Would be nice to have a back of the envelope method for sizing gates for speed b Logical Effort gt Book by Sutherland Sproull Harris gt Chapter 1 is on our web page gt First normalize a model of delay to dimensionless units to isolate fabrication effects b dabs d E U H b 1 is the delay of a minimum inverter driving another minimum inverter with no parasitics H b In a 06u process this is approx 40ps gt Now we can think about delay in terms of d and scale it to whatever process we re building the circuit in b Delay of a gate d has two components b A fixed part called parasitic delay p b A part proportional to the load on the output called the effort delay or stage effort f b Total delay is measured in units of 1 and is sum of these delays gtdfp b The effort delay due to load can be further broken down into two terms gtfgh b g logical effort which captures properties of U H the gate s structure b h electrical effort which captures properties of load and transistor sizes H b h ComCin b Cout is capacitance that loads the output b Cin is capacitance presented at the input gt So d gh p b Logical effort normalizes the output drive capability of a gate to match a unit inverter b How much more input capacitance does a gate need to present to offer the same drive as in inverter 21 b DEF Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current U H b Measure from delay vs fanout plots gt Or estimate by counting transistor widths H 2 A 4 2 A 2 Y B 4 A Y Y 1 B 2 1 cm3 cm4 cm5 g3l3 g4l3 g5l3 b Logical effort of common gates assuming that PN size ratio is 2 Number of inputs GateType1 2 3 4 5 n Inverter 1 NAND 43 53 63 73 n23 NOR 53 73 93 113 2n13 MUX 2 2 2 2 2 XOR 4 12 32 gt Value of logical effort g is independent of transistor size gt It s related to the ratios and the topology gt Electrical effort h captures the drive capability of the transistors via sizing gt Electrical effort h ComCin gt Note that as transistor sizes for a gate increase h decreases because Cin goes up b Parasitic delay p is caused by the internal capacitance of the gate gt It s constant and independent oftransistor size gt As you increase the transistor size you also increase the cap of the gatesourcedrain areas which keeps it constant 3 b For our purposes normalize pinV to 1 b Ninput NAND n kpinV b Ninput NOR n kpinV b Nway mux 2npinV gt XOR 4 pm Effon delay Normalized delayd V 1 A Pamsitic delay 0 I I 0 1 2 3 4 5 Electrical effon h Delay Estimation W Remember 1 in A B Our process N 40ps Aidelay gh p 1CinBCinA 1 l4CinACinA 141 Stime units N200ps A B Aidelay gh p 43CinBCinA 21 CiniB 43 I2 Cin A 4 Aidelay 43124 2 4 2 6 units N240ps NandZ worse because of higher parasitic delay than inverter Note that gh term was same for both because NANDZ sized to provide same currenl drive Delay Estimation W Remember 1 m A B Our process N 40ps Aidelay gh p 1CinBCinA 1 200ps l4CinACinA 1 4 1 5 time units Iin180nmN12ps F04 Inverter delay 60ps A B F04 NAND delay 72ps Aidelay gh p 43CinBCinA 2 CiiLB 43 l2 CiniA 4 Aidelay 4324 2 4 2 6 units N240ps NandZ worse because of higher parasilie delay than inver e l r Note that gh term was same for both because NAND2 sized to provide same current drive b As technology advances I continues to shnnk b Exact numbers are surprisingly difficult to get I b This table is very very rough Node 50025018013090 65 45 32 1 nm nm nm nm nm nm nm nm 40 22 12 1o 7 57 45 36 ps ps ps I08 p8 p8 p8 I08 b Estimate the frequency of an Nstage ring oscillator Logical Effort g 3 Electrical Effort h Parasitic Delay p Stage Delay d Period of osc b Estimate the frequency of an Nstage ring oscillator Logical Effort g 1 Electrical Effort h 1 Parasitic Delay p 1 Stage Delay d 2 so dabs 80ps Period 2Ndabs 496ns Freq 200MHz b Estimate the delay of a fanoutof4 F04 inverter Fi Logical Effort Electrical Effort Parasitic Delay Stage Delay QT 70 b Estimate the delay of a fanout of 4 F04 inverter 01 The F04 delay is about 200 ps in 06 pm process Logical Effort 9 1 60 ps in a 180 nm process Electrical Effort h 4 WWW Parasitic Delay p 1 Stage Delay cl gh p 5 blfCin xCout10xthush 10 gtg9l33 gtdghp31041341360ps MultiStage Delay Recall rule of thumb that said to balance the delay at each stage along a critical path Concepts of logical effort and electrical effort can be generalized to multistage paths Orgtfi Path logical effort 2 glg2g3 g4 Cout In general Path logic effort G H gi Path electrical effort H Cout Cin rsLgate Must remember that electrical effort only is concerned with effect of logic network on input drivers and output load Off Path Load D0 7 Off path load will divert electrical effort from the main path must account for this Define a branching effort b as Ctotal b Conpath Coffpath Conpath Cuseful The branching effort will modify the electrical effort needed at that stage The branch effort B of the path is B n bi b Logical effort generalizes to multistage networks gt Path Logical Effon G H g C t7 a b Path Electrical Effort H quot inf path gt Path Effort FHf Hgh gt Can we write F GH gt Remember branching effon b Accounts for branching between stages in ath 390 C C b on path off path C on path Note BZIIQ IlthH gt Now we compute the path effort gtFGBH E b Path Effort Delay DF 22f b Path Parasitic Delay 3 2 2p b Path Delay D 22d DF P DZ QP Delay is smallest when each stage bears same effort A f gihi FN Thus minimum delay of N stage path is DAFfP This is a key result of logical effort gt Find fastest possible delay b Doesn t require calculating gate sizes The absolute delay will have the parasitic delays of each stage summed together However can wus onjust Path ef m F for minimization purposes since parasitic delays are constant For an Nstagc network the path delay is least when each stage in the path bears the Name stage effort rimm go hi Minimum achievable path delay Dmin N FUN P Note that if N1 then C f p the original single gate equation Remember that the stage effort hi is related to transistor sizes fmin g0 hi FI N So hi min F N gi To size transistors start at end of path and compute Cini gi Cout i frnin Once Cini is know can distribute this among transistors of that stage Cin 7 cm 7 0 MOMZC T Size the transistors of the nandZ gates for the three stages shown Path logic effort G g0 g1 g2 43 43 43 237 Branching effort B 10 no offpath load Electrical effort H CoutCin CC 10 Min delay achievable 3 GBH1 3 3 2pinv 3 23711 3 3 210 100 minDNF 1 P The effort of each stage will be fmjn GBH 1 3 237quot 101O13 133 43 Cin of last gate should equal Cin last gate min gi Cout i fmjn 43 C43 C Cin of middle gate should equal Cin middle gate 2 gi Cin last gate min 43 C 43 C All gates have same input capacitance distribute it among transistors Where gate capacitance of 2 W L Mosfet C2 Choose W accordingly s L L C what changes U UL Let Load 8 Cin C Cin 7 Cin 2 Wow 8C T Size the transistors of the 11de gates for the three stages shown Path logic effort 2 G g0 g1 g2 43 43 43 237 Branching effort B 10 no offpath load Electrical effort H CoutCin 8CC 80 Min delay achievable 3 Gquot BH1 3 3 2pinv 3 237181 3 3 210 140 The effort of each stage will be fmin GBH 3 237108 1 3 267 83 Cin of last gate should equal Cin last gate min gi Cout i min 43 8C 83 4C Cin of middle gate should equal Cin middle gate 2 gi Cin last gate min 43 4C 83 2C Note that each stage gets progressively larger as is typical with a multistage path driving a large load Size path om Cm y A to B cmc Cinzz 45C Path logic effort G g0 g1 g2 43 43 43 237 Branch effort 151 stage 2 yyy 2 Branch effort 2nd stage 2 zzzz 3 Path Branch effort B 2 3 6 Path electrical effort H CoutCin 45CC 45 Path stage effort 2 F GBH 237645 64 Min delay NFW P 364 3 32pi11V 180 units 16 Stage effort of each stage should be mjn F1N GBH1N 64 13 4 Determine Cin of last stage 11312 g Cout min 43 45C 4 15 C Determine Cin of middle stage Ciny g 3Cinz min 43 315C 4 15C Is rst stage correct D CinA g 2Cinyfmin 43 215C4 C Yes selfconsistent gt Select gate sizes x and y for least delay from A to B D Logical Effort G Electrical Effort H Branching Effort B Path Effort F Best Stage Effort Parasitic Delay P Delay D Logical Effort G 435353 10027 Electrical Effort H 458 Branching Effort B 3 2 6 Path Effort F GBH 125 Best Stage Effort fI75 Parasitic Delay P 2 3 2 7 Delay D 35 7 22 44 FO4 gt Work backward for sizes y gt Work backward for sizes y45535 15 X 152 53 5 10 ll U l 1011 gate cap cm x Cin Z MW Cout 20u gate cap Cin y 7 Path logic effort G g0 g1 g2 g3 2153 43 1 209 Path Branch effort B 1 Path electrical effort H CoutCin 2010 2 Path stage effort 2 F GBH 20912 409 For Min delay each stage has effort F1W 409 4 145 z g Cout mjn 120145 14 y g Cinzfmin 43 14 145 13 x g Cinyfmin 53 13 145 15 Note Don t care about parasitics for gate sizing only if you want to know absolute delay gt Note that you never size the first gate b This gate is assumed to be fixed b Ifyou were allowed to size it the algorithm would try to make it as large as possible gt This is an estimation algorithm gt Authors claim that sizing a gate by 15x too big or small still results in a path delay within 15 of minimum 20 CiIIl Cboggtj The problem I 8C CinC Wow Option 1 T cm 090 8C Option 2 CinC gt0 8C Option 1 T Path logic effort G g0 g1 g2 163 1 2 Path Branch effort B 1 Path electrical effort H CoutCin 8CC 8 Path stage effort F GBH 2l8 16 Min delay N 17 N P 3 16 3 pinv 4pinv pinv 3 25 6 135 21 ti 5 c it M 90 D so Option 2 Epj I Path logic effort G g0 g1 g2 143 53 209 Path Branch effort B 1 Path electrical effort H CoutCin 8CC 8 Path stage effort 2 F GBH 20918 1609 Min delay 2 N F N P 3 1609 3 pi11V 2pinV 2pinV 326 5 128 Option 2 appears to be better than Option 1 by a slight margin b Consider three alternatives for driving a load 25 times the input capacitance gt One inverter b Three inverters in series gt Five inverters in series gt They all do the job but which one is fastest 22 a 4 F gtn all cases G 1 B 1 and H25 b Path delay is N25 N N P quotW gtN1 D26units b N 3 D 118 units b N 5 D 145 units gt Since N3 is best each stage will bear an effort of 25 3 29 gt So each stage is 3x larger than the last b In general the best stage effort is between 3 and 4 not e as often stated b The e value doesn t use parasitics U at quotF ifs NHquot 3 by llioiiusgmggl u lta i b You can solve the delay equations to determine the number of stages N that will achieve the minimum delay b Approximate by Log4F Path Effort Best Min Delay Stage effort F N D f 0583 1 106 8 058 583223 2 68114 2447 223822 3 114160 2844 822300 4 160207 3042 3001090 5 207253 3141 10903920 6 253298 3240 b How sensitive is delay to using exactly the best number of stages is S H 125 12 115 E 1 El 9 92 A 24 lt p lt 6 gives delay within 15 of optimal b We can be sloppy gt I like p 4 V gt String of inverters driving an offchip load gt Pad cap and load 40pf b Equivalent to 20000 microns of gate cap b Assume first inverter in chain has 72u of input cap H b How many stages in inv chain b H 2000072 2777 H gt From the table 6 stages is best b Stage effort f 2777 6 375 b Path delay D 6375 6Pinv 285 b D 114nsifr 40ps D 24 b Compute path effort F GBH gt Use table or estimate N log4F to decide on number of stages b Estimate minimum possible delay D NF N 2pi gt Add or remove stages in your logic to get close to N b Compute effort at each stage f F N gt Starting at output work backwards to compute transistor sizes Cin gifCout b Chicken and egg problem gt Need path to compute G gt But don t know number of stages without G b Simplistic delay model b Neglects input rise time effects b Interconnect b Iteration required in designs with wire b Maximum speed only gt Not minimum areapower for constrained delay 25 b Logical effort is useful forthinking of delay in circuits b Numeric logical effort characterizes gates gtNANDs are faster than NORs in CMOS b Paths are fastest when effort delays are 4 b Path delay is weakly sensitive to stages sizes gt But using fewer stages doesn t mean faster paths b Delay of path is about log4F F04 inverter delays 3 b Inverters and NAND2 best for driving large caps b Provides language for discussing fast circuits gt But requires practice to master 26

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