Fab & Char Tech for Nanostru
Fab & Char Tech for Nanostru ECE 6960
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This 7 page Class Notes was uploaded by Shyanne Lubowitz on Monday October 26, 2015. The Class Notes belongs to ECE 6960 at University of Utah taught by Staff in Fall. Since its upload, it has received 31 views. For similar materials see /class/230013/ece-6960-university-of-utah in ELECTRICAL AND COMPUTER ENGINEERING at University of Utah.
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Date Created: 10/26/15
Slide 1 Slide 2 ECECS 3720 Embedded System Design ECE 69602 and CS 6968 Chris J Myers Lecture 15 Serial IO Devices Introduction to Serial Communication Serial communication involves transmission of one bit of information at a time One bit is sent a time delay occurs next bit is sent Used to interface to printers keyboards scanners etc Universal asynchronous receivertransmitter UART is the interface chip that implements the transmission A serial channel is collection of signals or Wires that implement the communication Data terminal equipment DTE is the computer Data communication equipment DCE is the modem Slide 3 Slide 4 A Serial Channel Main Computer Serial channel UART gt DTE I V v 1 Interface Modem l 39 Idle 7 bit Start data l l Parity iS OP Stop cMos Level R3232 Level R3422 Level TrueMark 5 v TxD 712 v Prth 7 TxD es v FalseSpace 04 v TxD 12 v Prth 7 TxD 3 v De nitions A frame is a complete and nondivisble packet of bits Includes both information eg data characters and overhead start bit error checking and stop bits Parity is generated at the transmitter and checked at the receiver to help detect errors in transmission Even parity makes number of ls even dataparity Odd parity makes number of ls odd dataparity Bit time is the time between each bit Baud rate is total number bits transmitted per time Slide 5 Slide 6 B andwidth 0 Information is data user Wishes to transmit Characters to be printed 0 Overhead is bits added to achieve transmission 7 Start bits stop bits parity etc Bandwidth information bits frame total bits frame gtlt baud rate Various Serial Channels 7 Full Duplex UART TxDm Computer n nah 2 FNT L Half Duplex LSIZS L5125 UART I in raw n Compmer Tristate 1 g 2 Logic RXD mm Half Duplex r 7407 7407 UART I U1 l TxD Computer open in I 2 E colleclor RXD n mm Slide 7 Slide 8 A Desktop Network Serial B 1 68116812 SCI quot5 5C1 68116812 1 TxD 4 5 F5 RxD i 1r Wok5 68116812 SCI 68116812 7 TxD 5 5 RxD 1 68116812 SCI SCI 68116812 3 TXD 6 5 V 5 RxD g Other Types of Channels RS232 Cables DB 9EIA5 74 RI45EIA56l g g Slide 9 Gmuudmg Slide 11 Twislcd Wire R T Ground Shield l RS232 DB9 Pin Assignments Pin Signal Description True DTE DCE DCD Data Carrier Detect 12 In Out RXD Receive Data 12 In Out TXD Transmit Data 12 Out In Slide 10 Slide 12 DTR Data Tbrrninal Rdy 12 Out In Signal Ground DSR Data Set Ready 12 In Out RTS Request to Send 12 Out In CTS Clear to Send 12 In Out RI Ring Indicator 12 In Out omwmm wmw m C RS232 Interface MCOSHCUSCS PDl MCGSHC7ORXL36 PE TkD H MCG l n B AGE 1 lll nF 7 5 3 quotT In nF 51 MW lUUnF 100le T b C 1 AS l Dl C68HCSI2A4 PS MCKxSIlCSllAl PS3 MCGSHCQllBJZ PS MCOSHCUSCX PDU MC SHC39IOSXLSG PEI v8 Cl MCbSHCFlZAl PSI MCGBHCg 1 QB PSO Current Loop Channel SCI TxDula Not connected Slide 13 Slide 14 Modern Serial Interface MODEM Ground Phone Slide 15 Not connecled Ground Logic Originate Answer True 1270 HZ 2225 HZ False 1070 HZ 2025 HZ Optical Channel SCI TxData Slide 16 RxDalar No con necled Ground Digital Logic Channel MC68HC81 1A4 RxD MCGSHCWIBSquot Grol 5 ONIJQ i 2 F 439 7 Serial Communication Interface Most embedded microcomputers support SOL Common features include 7 A baud rate control register used to select transmission rater 7 A mode bit M used to select 8bit M0 or 9bit M1 data framesl Each device can create its own serial port clock with period that is integer multiple of the E clock periodl Transmitting in Asynchronous Mode Status Bits Generated by the Transmitter 0 Common features in the transmitter o Transmit Data Register Empty ag TDRE set when TXD data out ut in with TTL volta e levels Slide 17 39 p p 39 t g 39 Slide 19 SCDR empty clear by read1ng TDRE and wr1t1ng SCDR 10 or 11 b1t shlft reg1ster not d1rectly access1ble S 39 1 39 39 d 39 SCDR 39 o Transmit Complete ag TC set when transmit shift 7 ena commumcatlons am rengter wrlte register done shifting cleared by reading TC ag then only separate from receive reg though same address writing SCDR T8 data bit for 9 bit data mode Figures for Transmission Strip 765431105mn n ll Control Bits for the Transmitter We 5cm 0 Transmit Enable TE set to 1 to enable transmitter V l l l l l l l l l l l Sl39d 18 Sl39d 20 39 7 1 e 0 Send Break SBK set to 1 to send blks of 10 or 11 0st 1 e T I I 1 I o Transmit lnterrupt Enable TIE set to arm TDRE ag Mb him if 0 Transmit Complete Enable TClE set to arm TC ag i 1 2 3 4 5 o 7 s 9 101112131415i l l l l l l l l l l l l Idle TxD Slanbil 13u Slide 21 Slide 22 Pseudo Code for Transmission Process TRANSMIT Set TxDO Output start bit Wait 16 clock times Wait 1 bit time Set nO TLOOP Set TxDbn Bit counter Output data bit Wait 16 clock times Wait 1 bit time Slide 23 Set nn1 Goto TLOOP if nlt7 Set TXDT8 Output T8 bit Wait 16 clock times Wait 1 bit time Set TxD1 Output a stop bit Wait 16 clock times Wait 1 bit time Receiving in Asynchronous Mode 0 Common features in the receiver 7 RXD data input pin with TTL voltage levels 7 107 or 117bit shift register not directly accessible Slide 24 7 Serial communications data register SCDR read only separate from transmit reg though same address 7 R8 data bit for 97bit data mode Control Bits for the Receiver 0 Receiver Enable RE set to 1 to enable receiver 0 Receiver Wakeup RWU set to 1 to allow a receiver input to wakeup the computer 0 Receiver Interrupt Enable RIE set to arm RDRF ag 0 Idle Line Interrupt Enable ILIE set to arm IDLE agi Status Bits Generated by the Receiver 0 Receive Data Register Full ag RDRF set when new data available clear by reading RDRF and SCDR c Receiver Idle ag IDLE set when receiver line is idle clear by reading IDLE then reading SCDR c Overrun ag OR set when input data lost because previous frame not read clear by reading OR and SCDR 0 Noise ag NF set when input is noisy clear by reading NF ag then reading SCDR 0 Framing error FE set when stop bit is incorrect clear by reading FE then reading SCDR Figures for Receiving stop T05433108tm shift Clo ck Read SCDR S de 25 R H RxClk quot1quot31 quot2quot32 1 quot3quot33 Starlbi Ba x I RR H I R TRDSUJ X RDH l i DSCDR 327gtShingtOVRNd Required RDRF Pseudo Code for Receive Process RECEIVE Goto RECEIVE if RXD1 Wait for start bit Wait 8 clock times Wait half a bit time Goto RECEIVE if RXD1 False start Set nO RLOOP Wait 16 clock times Wait 1 bit time S de 26 Set bnRXD Input data bit Set nn1 Goto RLOOP if nlt7 Wait 16 clock times Wait 1 bit time Set R8RXD Read R8 bit Wait 16 clock times Wait 1 bit time Set FE1 if RXDO Framing error if no stop bit