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by: Fernando Schneider

Microprocessors EE 4390

Fernando Schneider
GPA 3.9


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Class Notes
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This 78 page Class Notes was uploaded by Fernando Schneider on Wednesday October 28, 2015. The Class Notes belongs to EE 4390 at University of Wyoming taught by Staff in Fall. Since its upload, it has received 18 views. For similar materials see /class/230381/ee-4390-university-of-wyoming in Electrical Engineering at University of Wyoming.

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Date Created: 10/28/15
EE439O Microprocessors Lessons 9 10 Serial Communications Interface Revised Aug 1 2003 Overview Fundamentals and Terminology Signals Multiple Serial Interface Serial Communications Interface SCI Transmitter Receiver Registers SCI Programming RS232 interface Revised Aug 1 2003 Fundamentals and Terminology Serial communication link single line connection data sent one bit at a time clock establishes rate of data transfer bit rate bits per second bit cell time to transmit a single bit BAUD rate bits per second NRZ line code transmit value for entire bit cell Revised Aug 1 2003 3 Fundamentals and Terminology cont ASCII American Standard Code for Information Interchange ASCII CHARACTER SET 7Bit Code MS Dig Ls 0 1 2 3 4 5 6 7 Dig G NUL DLE SP 0 P p 1 SOH DC1 l 1 A O a q 2 39STX D62 quot 2 B R b r 3 ETX DC3 3 C S c s 4 EOT 064 4 D T d t 5 END NAK 5 E U 9 u 6 ACK SYN amp 6 F V f v 7 BEL ETB 7 G W 9 w 8 BS CAN 8 H X h x 9 HT EM 9 I Y i y A LF SUB J 2 i z B VT ESC K k C FF FS lt L I 1 D CR GS M rn E SO RS gt N A n F S US I O 39 quot o DEL quotCopyright of Momv39g dzA gsEQODy Permissionquot lHVHO IIOSV Fundamentals and Terminology cont 0 Parity bit used to detect a single error 7 odd parity odd number of ones in character 7 even parity even number of ones in character Simplex transmit or receive data not simultaneously m mi muss issrgyiwmi Revised Aug 1 2003 Multiple Serial Interface 0 Two SCI channels and one SP1 channel Mmupu Send Interface M51 5m Cammumcahan Interface n scm T on MISC3150 4 MOSlMOMI 5 ml mphquot Interface n 5m DanDuzcunnRzgnu fnxPnnS DDR5 SCK c353 Revised Aug 1 2003 Serial Communications Interface SCI J MgLDULE 39 sci DATA VCK r r r V r r I rill ITTRANVSSIIT eHLFrREGIsIBR VlvvIGtsl4lsrlA2I391iol I 39 m AK 7 E 5 If F V 5 7 2 LOOPV To39 a j 397 CONTROL 7 RECEIVER U CO lt239 2 V V 0 5 3 P E quot 7 1 a M r 3 k i g r x r BREAK ALL 03 Sci mTERRUPT REQUEST 39 SCI INTERRU39PT REQUEST Figure 198 7 The SCI transmitteri Figure used permission oero torola Incorporated 39 39 7 Revised Aug 1 2003 Serial Communications Interface SCI Receiver mTERNAL BUS39 139 MODULE CLOCK gt 14 a 1 lBIT RECEIVE SHIFT REGISTER gt1H8765432110 E F m L FROM TPKD PIN OR TRANSMITTER 39 PARITY CHECKING SCI INTERRU39PT REQUEST V RDRF SCI INTERRUPT nEQUEST Figure 109 The SCI receiver Figure used withspermission of Mo torola Incorporated r Revised Aug 1 2003 Serial Communications Interface SCI Registers SCI Baud Rate Control Registers SCI Control Registers l 2 SCI Status Registers l 2 SCI Data Registers HighLow Revised Aug 1 2003 SCI Baud Rate Control Registers ER vaxcct fur ER vamuxfur M4EIMH1 M8UMH1 7 5 A A 7 1 u my H mm H mm Hm Hm Hs mn H we H snwx a a u u u u u n u u 7 6 5 A 3 j u W H saw H mm H mm H 53m H m M m H m u u u u u x u u Revised Aug 1 2003 10 SCI Control Registers 1 2 Address EIEICZEIEICA Regan SCICammlxegsm 1 ScuchSCICRI Revised Aug 1 2003 SCI Status Registers 1 2 Aamss snncmnncc Regsur scx Sutusregstexl scnsRlsclsm 4 Revised Aug 1 2003 SCI Data Registers HighLow Address snncmnnca Wu soDmgsaghscmcmm 7 6 5 4 3 2 n zllllllllllll n n n n n n Address snncmnncp Rem r Regan SCIDazaRegsmLavSCUDRLSCIDRL Revised Aug 1 2003 SCI Programming Initialize SCI Transmit Character set E aud rate configure SCXCRI andSCxCRZ far desiredSCI parameters clear the TDRE flag I etum from subroutine RTE p011 SCI Status Reg39ster 1 set date format m TDRE 1 i M Write to 501 data reg39ster HighGCxDRIIj andLaw SCXDRL 139 etum from subr autine HTS Receive Character p011 SCI Statue Regmr 1 Rm yes readfrom SCI data reg39ster High SCxDRIIj andLow SCXDRL r etum from subroutine RTE RCVIDCU Aug 1 AUUJ Example EX Write a subroutine to initialize the SCI Assume the MCLK 8 MHz and the data rate is 9600 BAUD Configure SClBDL BDH Configure SClCRl Configure SClCR2 Clear the TDRE ag in SClSRl two step process Read SClSRl Write to SClDR Revised Aug 1 2003 15 Example cont SClBDH SClBDL SClBDH 00 SClBDL 34 SClCRl M0 1 start 1 stop 8 data bits SClCR2 TE 1 7 Ham HH E Kasey u 7 5 5 4 3 1 H mm HH 5m HH 5m HH 5m HH mm H mm D n u u u s 5 4 3 2 m H mm HHSEm HHSERH leERm u u u u u 1 u lsER9 HH 5m HH u u 1 u H mm HH 5m HH u u Wm new Add mac 7 6 5 4 3 2 H a HmeHwa HH M Hme H m HH F H w 1 a 5 4 3 2 H u H m H m5 H m H m H TE RE H mm H say Rm u u u u u u u n m n 7 5 4 3 z 1 u Hum H Tc HRDRF H mm H 0R HH m H FE H n H c H 1 u o u u u 7 s 5 A j H u H Rm HH Rm HH m HH m4 HH m HH mm H mm HH mu H Example cont SCI Initialization Example Assume M 8 MHz 9600 BAUD de ne register locations and masks SC lBDH 00C8 Baud Register High location SClBDL 00C9 Baud Register Low location BAUDHI 00 Baud Register High mask BAUDLOW 34 Baud Register Low mask SClCRl 00CA Control Register 1 location SC1CONT 00 Control Register 1 mask SClCR2 00CB Control Register 2 location SC1MASK 08 Control Register 2 mask SClSRl 00CC Status Register 1 location SC lDRL 00CF Data Register Low location Revised Aug 1 2003 17 Example cont SCI Initialization Example Assume M 8 MHZ 9600 BAUD area scitestabs de ne name of absolute area org 4000 main J SR sciinit swi Revised Aug 1 2003 Example cont sciinit initializes SCI system Assume M 8 MHZ 9600 BAUD sdjmtzLDAA STAA LDAA STAA LDAA STAA LDAA STAA LDAA STAA RTS BAUDLOW set BAUD rate SClBDL BAUDHI SClBDH SCICONT set MODE SC 1CR1 SC1MASK enable transmitter SC 1CR2 SCISRI clear TDRE bit 2 step process SCIDRL 1 read SCISRI write SCIDRL return from subsroutine Revised Aug 1 2003 19 RS232 Standard Electronic Industry Association EIA Standard Evolved from 1960 standard EIA232D Four aspects Electrical speci cations voltage level rise time fall time Functional speci cations of each signal Mechanical speci cations number of pins connector shape connector dimension Procedural speci cations RS232 voltage levels 12v l I W J l 12v Sta 39 daRevised mgl ilmy idle stop idle 20 RS232 Standard cont VuSVDE f smwnm V T 5 Wm WM 2 71 mm mm 1 52 WNW m m 40 mm m a 40 mm mm 40 Revised Aug 1 2003 EE439O Microprocessors Lessons 16 18 68HC12 AnalogtoDigital ATD Converter System Revised Aug 1 2003 Overview Analogtodigital fundamental concepts 68HC12 ATD system description ATD registers control registers status registers result registers test registers ATD programming Revised Aug 1 2003 Analogtodigital fundamental concepts Transducer interface design Big picture conversion process sampling rate encoding quantizing and resolution data rate successive approximation converter Revised Aug 1 2003 Analogtodigital fundamental concepts Transducer Interface Design We live in an analog world Physical variable requires conversion to digital representation ie light pressure temperature gt voltage gt binary Requires transducer for conversion Transducer requires interface to microprocessor such that it lls conversion Window VRH VRL Revised Aug 1 2003 AnalogtOdigital fundamental concepts Transducer Interface Design cont gtxlt V2max V2m1n K B gtllt Vlmax Vlmin K B X2 v min HEmax mm 3 Miu39ocordIcDer V1 V1 System 39ll ma X1 DC Offset Bias 13 Revised Aug 1 2003 AnalogtOdigital fundamental concepts Big Picture V RH 42m 39 1 Ia J mat in mg 1 V BL I I I I I I I I Revised Aug 1 2003 Analogtodigital fundamental concepts conversion process COIlVCI39SiOIl pI39OCCSS sampling rate encoding quantizing and resolution data rate Revised Aug 1 2003 Analogtodigital fundamental concepts conversion process sampling rate strobe light example Nyquist criterion sample signal at a minimum frequency of twice the highest frequency content of the sampled signal rs gt 2 fh Time interval between samples TS 1 t antialiasing filter use LPF with fcutoff fh phone company samples human voice at 8 KHZ uses 4 KHz LPF to prevent aliasing Revised Aug 1 2003 Analogtodigital fundamental concepts conversion process encoding Provides unique binary code for every discrete voltage step between VRH and VRL n 2b encaded bimyvalue Revised Aug 1 2003 Analogtodigital fundamental concepts conversion process quantizing resolution data rate Quantization number of discrete levels the analog signal is divided into between VRH and VRL More levels provide better representation of sampled signal EX VRH 5 VDC and VRL 0 VDC quantization 256 levels voltage per step 5V 0V256 steps 1953 mVstep Resolution voltage per step Resolution VRH VRLnumber of steps VRH VRL2b Data rate d fsb Revised Aug 1 2003 10 Analogtodigital fundamental concepts conversion process successive approximation gm 5 an v L 0mm 0375 v ngv u r Oenszsv 175v my 13110337 mm M 312st Womm 2m momsv msv X 131 WOme 125 v nu Ouznv m 0mm mus pa mg mg was my 55m w 68HC12 ATD system description 7 RC DAC ARRAY AND COMPARATOR l VRH VHL VDDA VSSA ANALOG MVUXV AN D SAMPLE BUFFER AMP D I E ATD 0 Z 8 ATD 1 D Z ATD 2 E I Q ATD 3 Z lt ATD 4 quotQquot 0 ATD 5 2 ATD 6 ATD 7 CLOCK SELECTPRESCALE ENTERNAL BUS P RT D A DATA INPUT REGISTER Figure 910 Alialog to digital ATD block diagram The eight ATD REFERENCE SUPPLY AN7PAD7 AN6PAD6 ANSPADS AN4PAD4 AN3PAD3 AN2PADZ lt AN lPAD I 4 ANOPADO system analog inputs are located on pins ANOPADO to AN7PAD7 7 Figure used with permission of Motorola Incorporated Revised Aug 1 2003 12 68HC12 ATD system description cont Eight ATD analog inputs on PORTAD PAD 70 Inputs fed to analog multiplexer Single signal fed to successive approximation converter Initiate conversion by writing to control register Upon conversion complete appropriate ags set in status registers Results available in results register Revised Aug 1 2003 13 ATD registers control registers con gures ATD for speci c operation ATDCTLO ATDCTLS status registers twobyte register containing ATD status ags ATDSTAT result registers contains binary weighted result after conversion ADROH ADR7H test registers used in special modes Revised Aug 1 2003 14 ATD registers control registers Used to tailor an ATD conversion sequence We will concentrate on control registers ATDCTL 2 4 and 5 Revised Aug 1 2003 15 ATD registers control registers ATDCTLZ Memory address 0062 7 ADPU onoff switch 0 0 off 1 on 0 after processor reset 7 must wait 100 us after on prior to using ATD 7 AFFC ATD Fast Flag Clear 0 0 normal clearing write to ATDCTLS 0 l fast clearing cleared when rst result register read Regsur An agrtarDigmCanvaneramxalRegsterZ ATDCTLZ Adam sums Revised Aug 1 2003 ATD registers control registers ATDCTL4 Memory address 0064 Controls sample timing for conversion sequence Regsur AnuagrtarDigmCanveneramxalRegster4ATDCTL4 Adam sum Revised Aug 1 2003 ATD registers control registers ATDCTLS 0 Used to configure conversion mode for ATD 0 Memory location 0065 7 S8CM select 8 channel mode 0 four 1 eight conversions 7 SCAN enable continuous scan 0 single 1 continuous conversion 7 MULT enable multiple channel conversion 0 single channels 1 multiple channels 7 CDCCCBCA specify channels for conversion Regsur An agrtarDinganvenzrCamalReggerS mucus Adriess sums Revised Aug 1 2003 Table 174 Multichannel Mode Result Register Assignment ATD registers 53 quot w so as an control registers a o o ATDCTLS cont ATD registers status registers twobyte register containing ATD status flags ATDSTAT contains series of ags that indicate status of the ATD Sequence Complete Flag SCF indicates specified conversion is comp ete CCX 3 bit counter which indicates channel currently undergoing conver51on CCFX Conversion Complete Flag for each result register Ragnar An agtaDigtal CamenersutusRegster ATDSTAT Address sums u Regan AnuagtaDigtalCamenexsutusRegsLexATDSTAT Address sum Revised Aug 1 2003 20 ATD registers result registers 0 After conversion results placed in ADROH7H Unsigned weighted binary result l2FS l4FS l8FS 0 VDC contents ADRXHZSG VRH VRL ngsm An agrtangtalCamenexResu Reg er ADREIH Address suu7u ngsm An agrtaDigtalCamenerResultRegstex 1 munx Address suu72 ngsm An agrtaDigtalCamenexResultRegsterZ ADRZH Address suu74 ngsm An agrtaDigtalCamenexResultRegstexZ ADRZ Address suu76 ngsm An agrtaDigtalCamenexResultRegsLexAADRAIl Address suu72 ngsm An agrtangtalCamenerResu Reg erS ADRSH Address suu7A ngsm An agrtaDigtalCamenerResu Reg er ADR H Address suu7c ngsm An agrtaDigtalCamenerResultRegstex7 ADR7H Address suu7E Revised Aug 1 2003 ATD Programming Structure chart ATD Convener mam ATDJN l DELAWO5 CONVERT Flow chart InmaHZe Program nmanze ADC ADC WarmUD 105 US Revised Aug 1 2003 22 ATD Programming File Name voltmeterc File Created 04 14 02 File Modified Authors Abbie Wells Carrie Hernandez LCD Portions This program will create a simple voltmeter using the onboard analog to digital converter in the HC12 It will perform one conversion and then the user will have to manually restart the program to convert another voltage The voltage will then be displayed to the LCD include lthc12hgt include ltstdiohgt define DECIMAL OX2E define macro for a decimal point in ASCII define V 0X56 define macro for a quotVquot in ASCII void delaylOOusvoid void ADCconvertvoid void delay75msvoid Revised Aug 1 2003 23 void mainvoid printfquotHELLOnquot ATDCTLZ 0X80 printfquotADC2nquot delay5ms printfquotwarmed upnquot O ATDCTL3 ATDCTL4 i 0x01 printfquotreadynquot ADCconvert ATD Programming Revised Aug 1 2003 power up the ADC and disable interrupts wait for ADC to warm up select active background mode select sample time 2 ADC clks and set prescaler to 4 2 MHZ perform conversion and change to usable value 24 ATD Programmmg void ADCconvertvoid function to perform a single conversion void ADCconvert0 unsigned int sumadr unsigned int avgbinvoltage unsigned int intvoltage unsigned int onesint unsigned int tenthsint unsigned int hundrethsint char tenths char hundreths ATDCTLS 0X03 sets up ADC to perform a single conversion 4 conversions on a single channel and store the results ADROH ADR3H whileATDSTAT amp OX8000 OX8000 Wait for conversion to finish printfquotx x x Xnquot ADROH ADRlH ADR2H ADR3H sumadr ADROH ADRlH ADRZH ADR3H avgbinvoltage sumadr4 intvoltage lOOavgbinvoltage2565 onesint intvoltagelOO ones charonesint 48 tenthsint intvoltage onesintlOOlO tenths chartenthsint 48 hundrethsint intvoltage onesintlOO tenthsintlOl hundreths charhundrethsint 48 printfquotcccVnquot ones tenths hundreths Revised Aug 1 2003 25 ATD Programming 9999999999999999999999999999999999999kkkkkkkkkkkkkkk lOOus delay based on an 8MHz Clock void delayilOOusVoid int i for 10 ilt400 i asmquotnopquot 5 ms delay based on an 8MHz Clock void delay75msvoid int i for 10 ilt800 i delayilOOus Revised Aug 1 2003 26 EE439O Microprocessors Lessons 23 24 Exceptions Resets and Interrupts Revised Aug 1 2003 Exceptions Resets and Interrupts Polling vs Interrupts Exceptions Resets and Interrupts 68HC 12 Exceptions Resets Interrupts Maskable and Nonmaskable 68HC 12 Interrupt Response Exception Vector Exception Priority Programming an Interrupt Service Routine Revised Aug 1 2003 Exceptions Resets and Interrupts Polling versus interrupts polling constantly monitoring for ag to set program is tied up waiting for ag inef cient use of processor interrupt processor tells program when event has occurred program can be executing other tasks ef cient use of processor EX sequentially ask question vs you ask me Revised Aug 1 2003 Exceptions Resets and Interrupts Resets returns 68HC12 to known wellde ned state after detected fault poweron reset Computer Operating Properly COP reset Clock Monitor reset External reset Interrupts planned but unscheduled high priority event nonmaskable may not be turned off by user maskable turned on and off by user with I bit in CCR Revised Aug 1 2003 4 Exceptions Resets and Interrupts I bit controlled with CLI and SEI command CLI Clear Interrupt Mask turns interrupt system on SEI Set Interrupt Mask turns interrupt system off Need to turn on speci c interrupt locally 7quot ES 5 4 3 2 1 CI 3 x H I N zjv c I II A A A A A A Errg PE 0 mid Stap Disable Ha r Carry V Dwa 39uw External Interrupt Mash Ere m Megan9 Int2 7 m Mask Revised Aug 1 2003 Exceptions Resets and Interrupts cont mzskzhb JRQ nm Ttmhuwp Txmachmnzl meOvdlmv Pu szAccumuhmr Revised Aug 1 2003 68HC12 Interrupt Response interrupt service outi Revised Aug 1 2003 68HC12 Interrupt Response 0 Interrupt Vector location of ISR located in upper 128 bytes of memory user must tie Vector to ISR Interrupt Priority determines order of execution when multiple interrupts occur 0 Interrupt Service Routine ISR user written response routine to interrupt event Iii14 lil t upl angel1 MM with ISR Mauro h LluluJI39ne 53955 wrle LBS mnmul maul mgdzalzir Emmy 1 mmI39J 1 CU mammal L 3339 vm n a warl rmvrmzl E rumplqu mural nmururm I In mm Mnrquot cltu minim3 3515 up slvnahll ueru amt5 slme Equipglen Talus1n II mac 525 11 LL m LT C39CH 1 Iozce er nllzm Adenwls l L h ri iif a grim nlnm quat upn ng felcm 111an wrist rm h m 41 Imam rnguni L ul t m5 In m J 16 mungI same IIILI39H railing us pang m a pmrrsan uln nth1 rl MI In39 Tl39 l g39llfulm ulm up39 agent 42131 radHr krnegazn malnu im I1h An den me 1 m mum 511 y levmtge matquotif 1n arrwls bunsh xukgruu Julx herb m 1 am xigum 39rm E J l 68HC12 Interrupt Response Interrupt Priority quotCopyright of Motorola Used by Permissionquot Revised Aug 1 2003 Programming an Interrupt Service Routine Determine how interrupt is enabled global CLI local enable bit Initialize Vector Table directive approach EVB SetUserVector Initialize Stack Enable interrupt Write the specific ISR Revised Aug 1 2003 10 Programming an Interrupt Service Routine an example Initialize the microprocessor for the interrupt Initialize the stack this is done through compiler settings Initialize any other necessary systems on the HC12 Initialize the interrupt vector table You will need to use a special header le and code Header file is on your computer and is called abbieh change name Code to set up your function to be an interrupt service routine will be similar to the following T his part declares your function as an interrupt service routine pragma interrupthandler toggleisr Revised Aug 1 2003 ll Programming an Interrupt Service Routine an example 0 This part lls the appropriate vector with the address of your interrupt service routine pragma absaddress OXOBZA void TimerChannel2interruptvectortoggleisr pragma endab saddress 0 Make sure the interrupt you will be using is cleared to start 0 Initialize local interrupts Initialize the interrupt system using the CLI command With this header le use CLI Do this step last so that you aren t inadvertently setting off interrupts before you nish initializing the system Write the interrupt service routine to handle the interrupt Revised Aug 1 2003 12 Programming an ISR an example Table 1 RAM Interrupt Vectors Interrupt Name BDLC Key Wakeup J ATD SCI SPI Pulse Accumulator Input Edge Pulse Accumulator Overflow Timer Overflow Timer Channel 7 Timer Channel 6 Timer Channel 5 Timer Channel 4 Timer Channel 3 Timer Channel 2 Timer Channel 1 Timer Channel 0 Real Time Interrupt IRQ XIRQ SVV Unimplemented Instruction Trap COP Failure COP Clock Monitor Fail Reset Reset Revised Aug 1 2003 RAM Vector Location OB10OB11 OB12OB13 OB16OB17 0B18OB19 OB1AOB1B OB1COB1D 0B1EOB1F OBZOOB21 0B220823 0B240825 0B26OBZ7 0B280829 OB2AOBZB 0B20OBZD 0B2EOBZF OBBOOB31 0B320833 0B340835 0B36OBB7 OB3SOB39 OB3AOBBB 0B30OB3D OBEFOBFF Programming an Interrupt Service Routine an example Example In this task you will need to simultaneously generate two square waves with different frequencies For one wave use the month and day of your birthday and for the second use the month and day of your Lab TA s birthday Verify that the waves are being generated simultaneously and that they have different frequencies with the oscilloscope Revised Aug 1 2003 14 Programming an Interrupt Service Routine an example include ltabbiehgt void togglelisrvoid function prototype void toggle2isrvoid pragma interrupthandler togglelisr define as interrupt pragma interrupthandler toggle2isr pragma absaddress OXOB28 void TimerChannel3interruptvectortoggle2isr void TimerChannel2interruptvectortogglelisr pragma endabsaddress Revised Aug 1 2003 15 Programming an Interrupt Service Routine an example void initializevoid void mainvoid initialize TMSKl OXOC TFLGl OXFF CLI while 1 Define function initialize Initialize the timer system Initialize interrupts Continuous loop Wait for interrupts Revised Aug 1 2003 16 Programming an Interrupt Service Routine an example Function initialize enables the timer and sets up the M Clk void initialize CLKCTL 2 0X02 Set M clock to divide by 4 2 MHz CPU master clock divider 0047 TMSKZ 0x00 Disable TOI Prescale O T108 2 OXOC Make 082 output compare TSCR 2 0X80 Enable the timer TCTL2 OX5 0 Revised Aug 1 2003 17 Programming an Interrupt Service Routine an example void togglelisrvoid TFLGl 2 0X04 TC2 2 9091 void toggle2isrvoid TFLGl 2 0X08 TC3 2 4854 Revised Aug 1 2003 EE439O Microprocessors Lesson 4 Programming Model Assembly Language Instruction Execution Cycle Revised Aug 1 2003 Overview Programming Model Motorola Assembly Language Instruction Execution Cycle Revised Aug 1 2003 Pro gramng Model 0 Two 8 accumulators 4 bl 4 WI 0 Que 16rbe accumulator 0 l rbxtmdex registerx QIU o l rbxtmdex register 1 0 16m stack pormer 0 164 program counter w H l0wlt 7 SXHINZVC Cond lon CodeRegxster Revised Aug 1 2003 Programming Model cont A B 8bit accumulators collectively D 16bit register X Y 16bit index registers SP 16bit stack pointer PC 16bit program counter CCR 8bit Condition Code Register Revised Aug 1 2003 Programming Model cont 0 Condition Code Register Reference Appx A 7 6 5 4 3 2 1 o ISIXW l39lNlZlVlCl LT T carryBorrow Stop Disable Half Carryquot over ow External Interrupt Mask Ze ro Negative Interrupt Mask Kevlseu Aug 1 AUUQ Programming Model cont S disables STOP 39 N3 negatiVe ag instruction Z zero ag X enables nonmaskable V over ow ag interrupt C carry ag H half carry ag from lower nibble to upper Flag act1V1t1es nibble 1 sets I enable maskable terru ts 0 resets m p no change A determined by operation Revised Aug 1 2003 Motorola Assembly Language Label OpCode Operands Comment start LDAA FC load acc A Label name for a memory location Op Code mnemonic action part of instruction Operand access to data for instruction Via addressing mode cc indicates comment follows can also be used at the beginning of a line Comment Revised Aug 1 2003 Assembly vs C Assembly better HW control faster C more readable TopDown Design more ef cient programming do not need to know HW details Revised Aug 1 2003 Instruction Execution Cycle ccodc Revised Aug 1 2003 The Big Picture ICC12 host PC filename c I filenameh Compller filenameasm l lename asm gt assembler filename lst filename sl 9 v comm link Via SCI A4 EVB HW daughter fab SW card area DEBUG 1 2 1 uvlbuu nus 1 UUJ ICC 1 2 Speci c Items area nameabs org 1000 main 100px sample program Revised Aug 1 2003 Sample Code File Name introlabs File Created 040802 File Modified 041302 Authors Abbie Wells Introductory Lab Exercise to demonstrate uses of the HC12 Teaching Platform and familiarize the user with assembly code Basic arithemetic operations will be performed results and CCR contents stored to memory and CCR contents displayed to the LEDs area introlababs org 4100 main PORTT OOAE Create label for Port T DDRT OOAF Create label for DDRT TSCR 0086 Create label for TSCR Initialize Port T to be an output port Revised Aug 1 2003 Memory Map A4 Evaluation Board Table 35 FactoryCon guration Memory Map Address Range Description Location 80000 01FF CPU registers onchip MCU Soaoa soeFF user codedata 1K onchip RAM MCU SOAOO SOBFF reserved for DBug12 1000 1 FFF user codedata 4K arrchip EEPROM MCU 4000 7FFF user codedata 18K extemal RAM U4 USA 8000 9FFF available for user programs39 32K extemal EPROM U7 USA SAOOO SFD7F DBug12 program SFDBO SFDFF D Bug12 startup code39 SFEOO SFE7F useraccessible functions SFEBO SFEFF D Bug12 customization data39 sFFOO FF7F available for user programs39 FF80 FFFF reserved for interrupt and reset vectors 39Code in these areas may be modi ed Requires reprogramming of the EPROMs refer to Appendix E Customizing the EPROMs Copyright of Motorola Used by Permission Revised Aug 1 2003 13


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