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by: Jameson Treutel II

DigitalSystemDesign CEG360

Jameson Treutel II
GPA 3.57


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This 18 page Class Notes was uploaded by Jameson Treutel II on Thursday October 29, 2015. The Class Notes belongs to CEG360 at Wright State University taught by TravisDoom in Fall. Since its upload, it has received 17 views. For similar materials see /class/231076/ceg360-wright-state-university in Computer Engineering at Wright State University.

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Date Created: 10/29/15
Section IV Digital System Organization CEG 360560 EE 451651 Digital System Design D law a u Nat Department of Computer Science and Engineering Wright State University Msm M nixum warm Hugsrd Acknowledgements 7 These slides wa e developed with the aid of aiamples found in 7 my and Cnmputer Desigi Fundamentalsquot e M Mums Mann Digital Desigi Pnnnples and Pmeneesquot e JuhnWakerly e The original version ofmany othese slides were kindly provided by 7 Dr Rnger L Hagg 21 e Frentiee Hall ine ard et cisxsnisn Ensst mm Outline 1 Cnrnpiex System Desigr e jo meTrand39er szd Design e Memnry Hierarchy cisxsnisn Ensst xuannx Introduction How are complar systems deslgied7 er matlsamlcrooperatlohv How are reglstaruansferrlevel opethms conirolle 7 How 15 control organlzed implemented 7 How doesplpellnlng Work7 what IS the relauonshlp between a Crprogam and the hshueuohs that executedby themlcroproeess 7 d m a eomplor dlglml systemv or am 115qu ofmoda anSC archltecture as Why lsmemory organlzedhlemmhlcally7 ciexsntsn mum xulann t Complex System Design 1 e A dlgltal system IS a sequmtlal clrcultwlth speclfledbehavlor e Ammmpmcessuns adtgltal system a Speclfylng large digital systems Wth state tables may be exceptlonally dlmeult due to the number of states myolyed e As m eumputerprugammmg must mudular herareheal appruaeh e The system is paruauuedmtu mudular subsystems Each subsystem prfaxms a we usuueu ruusuau wnh spesrueu Interface 7 lutereumeeauu the yahuus subsystems Lhuugh data and cuntxul 31215 results m a dlgtal system ugtal systems are designed usmg a ciexsntsn mum mtswa Complex System Design 2 a Most dlg zl systems are partitioned mto two tooleyel modules 7 Data Uruturlgtatapath pa39furmsdatarpmce e certaul Urut determmes the sequence u e Datapathsaresequmtlalsyst ssmgupem uhs these uperaauu ems e the system statels de ned by the euuteuts quhereglsters e the fuueauh ltylsthe set ufde ned uperaauusthat canbeperfurmed uh the euuteuts ufthe registers 7 Elementary uperaauus are usually hutuut always perfurmedm parallel uh a mug ufblts m uue clunktlnk A mlcroop eratloh IS an elementary m the datapath They fall mto four raussermremuperaa f mpuimanury tu am 7 Arithmetic operath performed on data stored gmaal eateg les d i uus trans erhmary ata 39nm uhe regsterurdata ther mmmup eraauus perfurm anthmeae uh data m regsters e Luglcmcmuperanuns erfurmhltmampulaauusuu datamreglsters P e 5th meruupemauus shl datamreglsters mm mm xusum Interaction between Data and Control Units Control signals e stgnalsthatacttyate data processmgfun L 7 Tu aeayat asequence ufsuch up sequence nfenntml sgnalstn the t t l Cuntxul Dumb lnputs Data Outputs Cuntxul Outputs Data inputs c ons emanns the ennanl umt senrs Lhepmpa39 datapath e The ennanl umt uses these 331315 in detennmmg the spen c sequence uf npemannstn be perfumed e Other signals parts ofthe system such as memory and tnputoutput logic btnan mum humusY RegisterTransfer Level Design e An approach to specify analyze and design systems too complex touse the sizieeizblebased approaches commonly uullzed ln slmple designs The RegrsteeTransferLeyel RTL approach 15 charactenzedby e A 6431 systemls newed as dudedtnte adata subsystem anda eenael subsystem e The state ufthe data subsystem cunslsts ufthe mutants ufthe repsters e The funcnun ufthe stem per armed as asequence afrepsterttansders e Aregutertmmf ns aaansfermaaenpertenned enthe datum wh e e datum is transferred 39nm me 139 ste te anuther e The sequence afrepster amsfests eenaelledby the eenael subsystem Ice can be designed as a sequence ofregtster agams ASM charts etc e Each transform upemiluns e The ennanl untt implements the RTL destgn Lhruugh mtemnpemanns Cinxindin mum hulaan RTL Languages 1 z Thenotauon forregtstertmnsters are suf clm y completeto describe any digital system at the reng transt leyel e e Wn as repsteraansfer languag Registers are denotedby uppercase letters somettmes followedby numbers that tndtcate the function othe register g El R1AR PC MA etal e mdlvldual bits can be dented using parenthesls and bit nurnbes er labels 7 e e g Rum REI7 n PCL PCH ata transfer 15 denoted m symbolic form by the means of the replacement operaer 7 e g R2 7 R1 Cinxindin mum mtswa R TL Languages 2 um asmmmea vjxuxixmutunnhw I 4 a Lg mm m mm R TL Languages 6 R TL Languages 4 Cumpmev Datapath Cumpmev Datapath Cumm Wm Mm sxuhmmnnu um Muu mmummn mg mum at kl uht A 39 T quotw vvum Symbuh Nmauun m Cumvu Pwpehned Da apa h quot39 Datapa h t Twmmg r W pu m mm k m m 92 c2 I 21 ilzriu namaaamzm 9 Cam Primingil silzgi L 2 M WauuiEtilus 05 a 3323 namaaamzm 02322 05 a aavamaaa 9 a Ca AS mp e Mumrcyde Cumpmev Dwagvam we Pwpehned Cumvm Um rr r mm 5 v m AV 9me 5515 3 E25 maim E E Outline Complai System Deslgq 7 Regsmrrmnsfer Level Desxgn 7 Datapaths The Camml Wm Pipe 11 7 Cuntxulumt Hardwm 1 Issues m CompukerDesxgi r CISCvs RISC 7 Memury Hmrzrchy cEcxsnasn Ener hulan n A simple computer architecture v Germs Computer Sysrem 7 Current archnectures are perfumznce driven and vary may Processor 7 Umpmcessur sysLErns g ASIC Apphcauon Specx c Integated Cmur 7 Ferfurms aspem ctask nut agena39al purpuse prunessure g Vuuduu 7 IO Devxce 7 Accesses data devices 3 g Graphics Adapter stk Cuntxuller at 31 cmmn mum hulan x A simple microprocessor FFU Internal Cache m 1 gt CPU MMU CeanIPmcessmg Umt 7 Cuntml UmL Integer Dazapazh LuadSture Integer ALU z Floating PomLUmL 7 Fluatmg FumtDatapaLh Intanal Cache 7 SRAM fur Instructmn Cache mama and Data Cache a che 7 Memory MmagemmLUmL 7 Cuntxuls cummumcauun with Mam Mammy and umag g m mm mm W Instruction Set Architecture Microprocessors can only perform emain opaau s ne on 7 en wneh npeahnns will he parfui39med zndinwhaturder thuughtheuseufa rugam 7 Aprayam Eunsit E 3 s uf asequmce ufmachineexecutable insnuehnns 7 mxtmcmmis a eniieehnn ufbits that instructs the cumputa39 tn parfurm a speeise upa a un 7 The set ufinsh uchuns that a nameniar micmpmcessur ean Examte is its msmnnn se Insmnnn se archxtectwe Athumugh nesmphnn ufthe insh u lun set uf a cumputer setdirectly 7 Cumpila s cunvenpmgams speeisen in higeievei languages mm the insh uctiun set equivalent amashne langmgepmgzm eeennn mum nnnmv n Computer Instructions 1 e HigheLevel Language 7 c A e a so 7 Memmymansfer Equivalent MemA 7 MszB1 Mzm MemEEAEIEI 7 MzmEAEIE MemEEAIUJ e Machine7Levei Equivalmt hi 7 Assem y human readable ex Machine fur a Simple architecture Land R2 13 mm LaadRZ c EZEAIU n2 7 R2 a Star A R2 1 The bits of a machine instruction are divided intofield 7 eg EZEADB r E Operanun 1oaiquot Z DesnnanunAddress RZ BABE Address Field 7 The uperanun eld hpsnde de nes the funnat fur the inmchun esnnn mum nnnmv xx Computer Instructions 2 z Thee are three basic types ofcompuier instructions 7 Regscer Instructiuns uperate nnvaiues stared inregsta s Anthmziic shit and Lagic insmwnans 7 ane Instructmns muve databetween memeny and mysta s y uftvm pussiblenextinitmmurs tn Execute anhsh eh candnmn Uncandmaml hnheh Jump ohiyehs address is phat the aihzx apnnd is was s EeqkzmA 7 Hummus nMme huesmmhnhnmhmnnnw 7 new Winnhmmsmmmmheminaxnseennun mine eeennn mum nnnmv is Instructions Vs Microoperations what IS the dllrerence between a computer mstmctlon and a hard are mlcroop aatlehv e Cumputennsh uchun sh upended sturedm blnzrym the cumputa s memmy e The cuntxul umtuses the address Dr addresses prumded hy the pmgzm cuunter 12c tn remeve the nee msdueaeh hem memu The cuntml umt then deeedes the msaueaeh elds tn perfmh the required mlemepesaaehs fur the Execuuun uf eaeh e mstxu 7 Thus m mltrupmgzmmed cuntxul eseh cumputer msaueaeh ememhds tn amlempmgaml cEstnasn mum hullan m Instruction Formats 7 Dltferentlnstmctlons have dltferent types oflnstructlon formats 7 Regster lmplled lmmedlate DirecL IndlrecL Relaave lndexd Add 113112 R1 at n 15 93 as 32 cEstnasn mum hullan n The Instructionexecution Cycle 7 Intr Instructlon decode ID stage 7 The nmmunlsrecumzed urdecuded e Detemnne the msdueadh funnat hy exammmg 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advancmg as qu1ckly as m1croprocessortechnology T epaformancebotilened1snowmanorybandw1dLh cEstnain mm 11m N r Modern RISC Processors 7 Secondgmaauon RISC processors have Lakm advantage of 1mproved manufacmnng processes 1o 7 1 Make the deck rate faster 7 z Duphcate funcuunal ums cc a11DWpara11e1 Execunun ufm saucaarrs Snpxscalex 7 3 1ncrease are numba39 uf sages 1r are prpe11rre perplpelmzd r Modem RISC processors are now mtroducmg 7 1 Mars addressrrg mudes e W39hatw l the nail generauorr 1nLroduce7 7 Speculanve Data Processerm Memory 121M Trace Caches et a1 77 Gianna mm 11m 1v 1


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