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Computer Organization

by: Felton Hintz

Computer Organization CEG 320

Felton Hintz
GPA 3.71


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Class Notes
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This 3 page Class Notes was uploaded by Felton Hintz on Thursday October 29, 2015. The Class Notes belongs to CEG 320 at Wright State University taught by Staff in Fall. Since its upload, it has received 13 views. For similar materials see /class/231087/ceg-320-wright-state-university in Computer Engineering at Wright State University.

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Date Created: 10/29/15
Chapter 8 InputOutput a 0 basics c Keyboardinput av Monitoroutput a Interrupt driven 0 CS Realities 0 Computers do morethanjust executeyour program lO Interrupts Wxiywsuullnivznity nllzynfEngnnling Hana5m HIEIi mDamcpmsaameeamm emanatest IO Basics 0 Definitions Input transfer datafrom the outside world to the computer keyboard mouse scanner baracode reader etc 0utput transferdatafrom the computerto the outside monitor printer LED display etc Peripheral any IO device including disks 0 LC3 supports only a keyboard and a monitor WxiywSuuUnivznityLnllnanIng nearing mm5m Elm m Bananampmsam a ham am one A st Device Registers a VG Interface 7 Through a set of Device Registers Status register device is busyidIeerror Data register data to be moved tofrom device 7 The device registers have to be readwritten by the CPU a LC3 KBDR keyboard data regl er KBSR15 keyboard readynew character available KBDR70 charactertyped ASCII DSR display status register 39 DSRI15 monitor ready DDR70 characterto be displayed ASCII WxightSlzuUhivznitynll ynf ng nearing CEGZZDSln Um m namuwmsaam a ham am one A st Addressing Device Registers a Special IO Instructions Read orwrite to device registers using specialized IO instructions a Memory Mapped IO Use existing data movement instructions Load amp Store Map each device register to a memow address fixed CPU communicates with the device registers as if they were memow locations Frame buf fers Large areas of Memow Mapped IO forvideo display 0 LC3 Uses memow mapped IO xFEDD KBSR Keyboard Status Register xFE02 KBDR Keyboard Data Register XFED4 DSR Display Status Register XFE06 DDR Display Data Register XFFFE MCR Machine Central Register Memorymapped Input EGnnszn Wxigasuu Univenity nllzyn Ingmnn39ng mm 9mm amp owe Assemth c DxDnnmCnmpumxScun ampiEn39 c Mmom EGnnszn Wxigasuu Univenity nllzynfEng men39ng m npnzu39ing amp owe Assemth c DxDnnmCnmpumxScun ampiE 39 c Memory mapped Output Synchronizing CPU and IO o Problem 7 Speed mismatch between PU and gr GataMDR CPUru ms at up to 46Hz Whileall lO is muchslower 7 Example Keyboard input is both slow and irregular We need a protocol to keep CPU amp KBD synchronized WW Two cornrnon approaches is Polling handshake synchronizationl e um checks the KBD Readystatus bit 7 irset CPU reads the data register and resets the Ready bit 7 Repeat 5 lsu MuR Rwrwm 7 Makes CPUrIo interaction seem to be synchronous o Interruptdriven IO 39 s allowed 7 The CPU attends to the device in an orderly fashion more later Warpasaauhwmryoiiegarmgmag cmzmSm Warpasaammaymiegarmgmemg momisa GEEK or orrmowmsamomwmg Camp orgmmuy 7 m i or orrmowmsamomwmg Camp orgmmuy Polling vs Interrupts Who s driving Polling Algorithm n Polling PU in charge a nputllteyb0ardl a CPUchecksthe ready oitor s tus register as per prograrn instructions rheCPU ioopschecking the Ready pit if KBSR151thEri load KBDR7 EItD a register When bitis set a new character isayaiiable CPUioadsthe characterwaitinginthe keyboard data register 6 Output monitorl CPUioops checkingthe Ready pit when pitis set dispiay is ready ror nextcharacter CPUstores a character in display dataregister r irthe lO deyice isyery siow CPU iskeptbua waiting o Interrupt peripherai in charge t d which seryicesthe interruptingdevice 7 There can be dirrerent priority ieyeis or interrupt r Specializedinstructionscan maskaninterruptlevel MaiasimimmmycaiiegOrangutang comma Warpasaammaymiegmagma ccmim MET or orrmowmsamomwmg Camp orgmmuy 9 mm r p prrmowmsamomwmg Camp orgmmuy 1n Polling details Simple Polling Routines r Keyboard START LDI R1 A Loop if Ready not set a when key is struck BRzp START ASCH code or characteriswritten to KBDR7 oieastsigniricantbyte ofdam LDI R0 B If set load char to R0 register BR NEXTTASK KBSR15 Ready Bit isset to 17 thisiocksthe keyboard A F LL xFE00 Add39ess of KBSR rheCPU checksReady Bit andreads KBDR B F LL xFE02 Add39ess of KBDR when KBDR is ready ready bitis cleared and keyboardis unlocked Input a character 39om keyboard 0 Monitor 7 when CPU is ready to output a Character START LDi R1 Y A Loop if Ready not set CPU checkstR15Ready Bitunui itissettolreadyl BRzp START CPUwrites character toDDR7 o STI R0 B If set send char to DDR BR NEXTTASK character A F LL XFE04 Add39ess of DSR MonitorseB DsR15 to 1uniockedreadywhenthe character has been B F LL xFE06 Add39ess of DDR dispiayed anditisreadyror a new character Output a characterto the monitor wngiasmmyemrmuegsimmering momim wngiasaamyemrmuegdogma momim m i Dx orrmcanipmsaemaampmmng Camp orgmssemu 11 m r Dx orrmcanipmsaemaampmmng Camp OxguAssemhly 12 Keyboard Echo combine the above START LDI R1KBSR Loop if KB not ready BRZp START LDI R0KBDR Getcharacter ECHO LDI R1DSR Loop if monitor not ready BRZp ECHO STI R0DDR Send character N EXTTASK KBSR FILL XFEOO Address of KBSR KBDR FILL XFE02 Address of KBDR DSR FILL XFE04 Address of DSR DDR FILL XFE06 Address of DDR mam KTETE JSJEQEEZ ESEZZEEEW 5321 11 13 Example Print a string LEA R1 STR Load address of string LOOP LDR R0 R1 0 get next char to R0 BRZ DONE string ends with 0 LP2 LDI R3 DSR Loop until MON is ready BRzp LP2 STI R0 DDR Write next character ADD R1 R1 1 Set addressto next char BR OP STR STR NGZ quotCharStringquot There has got to be a better way 1 Later we will talk about how InterruptDriven 0 can be used to make this entire process much more processorefficient way sue Univenity nllzgenf Eng liming cEGmm m g DxDmmCmnputzzSciznc2 g lInginazring Cmnp0g giAnzmlly 15 DONE HALT 12m S3 1 W hat a bout PC PCs use Memory Mapped IO Mth Interrupw Wxight Suteunivenitv Cn zgznfEng DDnmnCmnputzz SciznnefgiEng39luzerin Em ring s Cmpmgkmgmuy Practice problems 87 813 814 816 was sum univznity n zgznf Eng min cEGmsm m1 Dhnmchnpmsmcemngmmg ampoxwmmb 17


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