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by: Candida Medhurst I
Candida Medhurst I
GPA 3.9


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Class Notes
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This 12 page Class Notes was uploaded by Candida Medhurst I on Thursday October 29, 2015. The Class Notes belongs to EE 3109 at University of Texas at El Paso taught by Staff in Fall. Since its upload, it has received 50 views. For similar materials see /class/231277/ee-3109-university-of-texas-at-el-paso in Electrical Engineering & Computer Science at University of Texas at El Paso.

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Date Created: 10/29/15
Lesson 3 Karnaugh Maps ComputerAided Digital Design EE 3109 Gopi K Manne Fall 2007 Three Variable Karnaugh Maps minterm positions Three Variable Karnaugh Maps legal circles ZA B CA B cA39B C39 BC A o 1 oo 0 0 zA cA B 01 1 o 11 m 0 1o 1 o Karnaugh Maps 7 re uctionorder depen en 7 still necessary to sanity check results 0 Need other more systematic methods 7 Karnaugh Maps graphical representation 7 QuineMccluskey method computer algorithm 0 Boolean Algebra no guarantee minimized expression d d t Three Variable Karnaugh Maps example ZA BBC Three Variable Karnaugh Maps example ZA B C A B C A B CA BC oooo Three Variable Karnaugh Maps wrap around ZA B c A BC BCA 0 1 zA39c39 00 K1 0 01 0 0 11 0 0 10 m o Three Variable Karnaugh Maps y A l 2 AC AB ZA CAB oo 0 0 Proof of consensus term m being redundant 11 1 100W Four Variable Karnaugh Maps minterm expansions AB CD 00 01 11 10 Three Variable Karnaugh Maps ZA39B C A BC ABC AB C ZC Sample Problem 1 5 min Four Variable Karnaugh Maps Zabcd E m0189 ZB C Four Variable Karnaugh Maps example 2 Four Variable Karnaugh Maps example 3 Z C39 D C D zmo145a91213 ZD C Four Variable Karnaugh Maps example 4 sample Problem 2 5 min 2 C D A B A C B C Simulation timing Hazards l lime oo Hum 04 Lesson 1 Introduction to Digital Logic Design ComputerAided Digital Design EE 3109 Gopi K Manne Fall 2007 Numbering systems Western World Decimal or base 10 Tne s st thatwe all Knuw and take rer granted 7 lg preoaolv plEKEd oecause ertne nurnoerer nngers en nurn an nangs o Mayans Vigesimal or base 20 7 nag cunceptufzeru and nag a rnegern pusltlunal nutatlurl 7 Alluwed rerrepresentlng a large range very srnall to very large numbers 7 pesltlenal nutatlurl alluws rerlen arltnm etc 0 Computers and Digital Systems Binary or base 2 7 Easytu lrnplern entpnvslcallv7 nlgn or law vultage on ere 7 alluvvs rer use or Euulearl man and pmlusupner s leglc true erralse nlgn or law one erzere on or err o Hexadecimal System Base 16 7 one Hexageclrnal digit represents reurolnarv glglts u 7 9 A7F Sample Problems 1 5 min Convert 100001 2 to decimal Convert 101 1001 1 102 to Hex Convert 2525m to binary Why Digital Systems 0 Accurate depending on number of digits used 7 CD Muslc rs orgral7 vrnvl Records were analog 7 mo vroeo and Allle 7 mp3 quallty depends on sampllngamount or blts o Reliable 7 Error Correction oaoaorlrnes 7 Dlscrete values wlth Large Noise Margln o Technolo y 7 can be lmplemented as rasr oneao cvos semlconductors Binary Codes BCD clock example 0 Binary Coded Decimal 842 1 weighted code 7 used with simple LED displays watch display etc 12 4 ll 0001 0010 10100 0101 values 1010through 1111 not legal values Lesson 1b Logic Gates Basic Operations Inverter o inversion operation AKA tne complement an un uniy single vanab indicated by a prime 0 uruvemare prime is easiertu use 7 he lnvErSan UM ls El and the lnvErSan Elf El ls i invenercunsists Elf tWEI transistors in CMOS aanxmeammumis anei uperatiun e unn I A 2 II 0 9 quotII Basic Operations Logical AND 0 ANDfunctlon rfurrned untwu ur inure buulean variables it and uniy it butn inputs are an a multiplicatan sym bul altnuugn nut multiplicatlun used ui Mu adlacentvanablesare assumedtu beANDed ism EE 3 indicated by canb Basic Operations Logical OR 0 OR function uperatiun perfumed u EIqu indicated by a addltlun symbul wean mused n MD Dr inure buulean variables cine it Either ur butn urtne inputs is nine altnuugn nut addltlun Basic Operations Logical NAND o NAND function nverse quND functan uutputis Item in it and uniy it butn inputs are nine Sample Problems 2 5 min Convert a NAND gate into a INVERTER Hint no gates necessary A Exclusive Or Logic gate XGBY XY X Y 23 Exclusive NOR Logic gate XNOR l XEY XYX Y X GBY SAD B Also known as an EquwalenceOperation or Bit Compare Sample Problem 3 5 min Convert a XOR gate into a INVERTER Hint no gates necessary A 1 z B B Sample Problem 4 5 min Convert a XOR gate into a BUFFER Hint no gates necessary A 0 z B B Logic Networks Fabca b abcbc a Truth Tables FABC AB c B C AB 0 ooogt ot ouj 0 0 0 1 0 1 0 0 Sample Problem 5 5 min FABC AB C 1Truth Table 2Logic Network Circuit Diagram Lesson 1c Maxterms and Mi nterms Minterm expansion in mnotation ZA BCABC ABC rewritten in mnotation Zabc ms m6 m7 BCma BC39m6 BCm7 Lesson 1d Boolean Algebra Theorems Design by Truth Table based on 1 s oftable ZA BCABC ABC ZABBC BC BC BC Maxterm expansion Z abc ab c a bc a bc rewritten as maxterm expansion Zabc M0 M1 M2 M b c MH b c M1 b c M2 b c M lc M5 Theorems Basic Theorem X X1 1 0 Idempotent Law XXX X XX o Involution Law x 39 x 0 Laws of Complementarity XX391 X X39FO Theorems 2 Communitive Law X YY X XYYX o Associative Law X Y ZX Y Z o Distributive Law XYZX YXZ XYZXY XZ XYZXYZ o Demorgan39s Law X1 X2 X339 X139 X239 X339 X1 X2 X3 X139 X239 X339 Sample Problems 6 5 min F ABCC B lll XY Y XY YX Y FABC B Lab Full Adder Cell adds three 1 bit numbers two numbers 0 one carryin from previous stage provides 1 bit sum and carry out Theorems 3 Simplification 1 XYXY X XYXY X 2 XXYX XXYX o 3 XY YXY XY YXY Lesson 1e 4bit AdderSubtracter Binary Addition Addition Tabie ButCarry One to next coiurnn 4bit binary adder using Full adder Carry But Carry One to ex column 4bit Binary Adder 1 1 0 gtFuIIAdder 110 A3A2A1A0 333231Bo 011 1 5453525150 1010 EISum Binary Subtraction SubtractionTable 1 1 1210 1100 610 0110 But borrow One from next column 0110 6 Sign and Magnitude system 1001102 4510 magnitude same in this cage aign bit 1 oi 0001102 610 One s complement 0001102 610 1110012 610 formal conversion gt N Example Zn1 11111 N 6 00110 simple conversion gt flip all bits 2quot 1 N Two s complement 0001102 610 1110102 610 formal conversion gt N N 1 Example Zn1 11111 N 6 00110 add 1 00001 Binary Subtraction 1210 1100 610 0110 1100 1010 0110 610 2 s Complement N 6 0110 N9 m Ignore the last carry add 1 0001 1010 Sum What is the equation for Z in terms of B AdderSubtractor 0 Combine adder and subtractor with one control input 0 Add 1 Adds B with A 0 Add 0 Subtracts B from A A2 S4 A1 Ao u 4blt ss 33 Adderl 32 gt 52 33 Subtractor 51 SO 4bit Binary Subtractor 1 312 ii ii Full C2 Full C1 Full C0 Full Adder Adder Adder Adder S4 53 52 1 0 Ignore the last carry out 1 Hint Second 0 Use EX OR Operation Z 0 Lab Instructions 0 Create new project for lab 1b 0 When Adding Symbol gt use the symbol name first lab Lesson 4 Sequential Circuits ComputerAided Digital Design EE 3109 Gopi K Marine Fall 2007 Set Reset Latch cross coupled clock less more on this later 0 effects ofS orR are immediate transparent Present StateFuture State 0 Q Past state Present state T gge ng Falling Edge Triggered Raising Edge Triggered Flip Flops 1Bit Memory Device 0 SR Latch No clock 0 SR FlipFlop o D FlipFlop Have clock input Output changes at the rising edge or at the falling edge 0 T FlipFlop 0 JK FlipFlop SR FlipFlop Ck Clock D FlipFlop T FlipFlop toggle 011Ao toggle toggle tirne JK FlipFlop JK FF J K Q Q o u o o o o o o 1 1 Q o 1 o o u 1 u 10J0 0 0 1 1 o gggmbobetweenSeR aridT op 1 o 1 0 0 1 1 J K is iegai andtoggies 1 0 1 1 1 1 1 1 o 1 Q 1 1 1 o Additional Inputs setreset o PrEN Cer D PrEN and 0er are asynchronous and take errect irnrnediateiy oyerriding tne clack and data Witnout these an syncnronous reset inust be irnbiernented in tne cone or lugi reeding tne D input Clk D PreN Cer 0 x x 0 Not allowed x x 0 1 1 yanabies ending in N or x x 1 o o cud D 1 1 Q Counters 0 One ofthe simplest forms of state machine 7 state ofa circuit means the value ofthe flops and latches e the next state is the values in the next clockc cle o deterrnined by current state atieast and aiso circuitinouts o use next state information to design inputs to FF and latches st cornrnoniy in an ascending order Witn Wrap around 7 can be descending 7 can be any arbitrary sequence userui rorcontroi 7 can be seyerai sequencese one orwnicn is cnosen based on inputs State Table for JK FlipFlop Use Kmaps to find equations 4bit Counter for Ja KaJb Kb Jc Kc Jd Kd


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