Computer Architecture CS 5513
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This 1 page Class Notes was uploaded by Mireya Heidenreich on Thursday October 29, 2015. The Class Notes belongs to CS 5513 at University of Texas at San Antonio taught by Staff in Fall. Since its upload, it has received 9 views. For similar materials see /class/231408/cs-5513-university-of-texas-at-san-antonio in ComputerScienence at University of Texas at San Antonio.
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Date Created: 10/29/15
Ali Tekeoglu 01094052 Power4 System Microarchitecture Review This paper has introduced a new 32way symmetric microprocessor and a new 39 J to 39 chips of a iiiiu They speci cally point out that Power4 should not be recognized as a new chip but as an architecture within which a set of chips are designed together to make up a system r Until Power4 IBM has made its designs by having more complex designs that yield higher instructions per cycle instead of embedding higher clock rate but for Power4 microarchitecture they also used the high clock rate approach by making the processor run at 11 GHz and 13 GHz concluding in impressive results in some key performance benchmarks While designing the new chip they had some guiding principles These were Symmetric Multiprocessor optimization since the server is a high throughput multitasking environment processing variety of different information at one time Engineers begin with the full design in their mind to optimize the system so they have designed all the peripheral parts of a processor in accordance with the new processor in order to get full performance of it They have improved their design to allow even higher processor 1 39 if the 39 39 imp v 3 become available They have implemented Reliability Availability and Serviceability into their designs by eliminating outages providing redundancy and allowing system to bypass problems if possible They have also tried to compensate the needs of both technical and commercial performance in a single design Binary compatibility with the previous versions of the 32bit and 64bit PowerPC versions is established in order to keep their customers software intact In the paper they have demonstrated the internal design of the microprocessor chip There have one Power4 chip in which there are two core processors with three L2 caches one L3 controller and other busses with controller units They have designed the 32way multiple issue processor in such a way that 4 Power4 chips are packaged into a module containing 8 cores and 4 of these modules come together to constitute a multiple issue processor with 32 core processors Designers of Power4 have put in serious amount of branch prediction mechanisms in order to prevent the loss of cycles at a miss prediction The mechanisms used are not new they are implemented in some other previous systems Power4 uses a multilevel branchprediction scheme to predict whether conditional branch is taken or not taken They have a register called Instruction Fetch Address Register that takes the address of the next instruction from Instruction Cache They have divided the instructions into groups that are executed together at parallel Since the instructions are executed out of order and they should be forced to confirm to the original order and since it is hard to obtain it in instruction by instruction they have chosen to divide the execution into groups of instructions Whenever there is an exception the machine is restored to the oldest group before the exception
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